PBGA封装的耐湿热可靠性试验研究

塑封电子器件作为一种微电子封装结构形式得到了广泛的应用,因此湿热环境下塑封电子器件的界面可靠性也越来越受到人们的关注.为了研究塑封器件及其所用材料在高湿和炎热(典型的热带环境)条件下的可靠性,采用耐湿温度循环的试验方法,以塑封球栅平面阵列封装(PBGA)器件为例进行测试.试验结果表明,芯片是最容易产生裂纹的地方,试验后期器件产生的裂纹主要出现在芯片和DA材料界面处及芯片、DA材料和EMC材料三种材料的交界处.空洞缺陷是使界面层间开裂的主要原因,在高温产生的蒸汽压力和热机械应力的作用下,界面上的微孔洞扩张并结合起来,导致器件最后失效.     

湿热环境下吸潮对QFN器件可靠性的影响研究

由吸潮引起的微电子塑封器件失效已经越来越多地引起人们的关注.选用QFN器件作为研究对象,首先进行QFN器件在高温高湿环境下吸潮17 h、50 h、96 h试验;然后利用有限元软件分析和模拟潮湿在QFN器件中的扩散行为,并建立湿气预处理阶段应力计算模型;最后,通过试验与仿真相结合,分析潮湿对封装可靠性的影响.研究表明:微电子塑封器件的潮湿扩散速度与位置有着重要的关系;在高温高湿环境下,微电子器件吸潮产生的湿热应力在模塑封装材料(EMC)、硅芯片(DIE)和芯下材料(DA)的交界处最大;QFN器件在高温高湿环境下吸潮产生的裂纹主要出现在硅芯片与DA材料交界面的边界.     

QFN器件在湿热环境中的界面裂纹分析

因吸潮而引起的界面破裂是塑封电子器件失效的一个重要原因。通过吸潮实验、无铅回流焊环境实验和湿热老化实验研究了QFN塑封器件内部界面裂纹情况。结果表明,未吸潮的器件经历无铅回流焊后很少产生裂纹,吸潮器件在吸潮期间未产生裂纹,但经历无铅回流焊后器件产生裂纹的几率达100%;裂纹在芯片、芯片粘结材料(DA)和塑封材料(EMC)的交界处的破坏程度最大;产生的裂纹的位置和扩展方向与结合材料的特性、结合界面的强度紧密相关。     

集成湿热及蒸汽压力对PBGA器件可靠性的影响

塑封器件在高温焊接之前的存储过程中，会吸收环境中的潮湿水分，这些潮湿水分在随后的焊接高温下会汽化因而产生蒸汽压力。本文将首先对PBGA器件内部潮湿水分高温下产生的蒸汽压力模型进行讨论，并结合湿／热一机械应力得到集成应力，最后分析蒸汽压力、集成应力对PBGA封装可靠性的影响。分析结果表明：在蒸汽压力、集成应力计算中，芯片、DA材料和EMC材料三相交界处发生了应力集中，如果在此界面存在初始裂纹，那么在这些局部集中的力的作用下，极易使裂纹扩展导致层间开裂。     

湿热环境下EMC尺寸对PBGA器件可靠性的影响

塑料封装器件由于湿热导致层间开裂是影响器件可靠性的关键问题之一。采用有限元分析软件模拟和计算了不同的模塑封材料(EMC)尺寸的PBGA(塑封焊球陈列)器件在358.15K、RH60%条件下吸潮168h和398.15K、RH0环境下干燥50h后器件内部的应力对界面可靠性的影响。结果表明,在吸潮情况下,EMC厚度为0.85mm的器件的界面可靠性最低,最大湿应力为0.528MPa;在干燥阶段,EMC厚度为1.25mm的器件的界面可靠性最高,最大湿应力仅为0.124MPa。     

废旧塑封芯片分层热力学仿真研究

废旧塑封芯片的界面分层会严重影响其回收重用价值,一直是废弃电器电子产品(WEEE)资源化研究中关注的热点问题.基于有限元仿真方法,分析了废旧QFP塑封芯片在线路板拆解温度下的翘曲变形和各材料界面应力分布.研究表明,拆解温度过高时,芯片翘曲过大容易导致材料膨胀力失配,造成界面分层;在粘结层、衬底和模塑料的结合区域应力水平非常高,较易发生分层;模塑料在拆解温度下为玻璃态,与管芯及衬底的结合强度均降低,其界面角点均为较易发生分层的位置.     

PBGA中环氧模塑封装材料的热力学应力分析

本文采用有限元模拟的方法,对塑封焊球栅阵列PBGA的再回流焊接过程及其后的热循环进行了仿真,其中环氧模塑封装材料EMC采用了粘弹性和线弹性两种材料模式。仿真中主要对EMC再回流焊接过程产生的残余应力和热循环载荷下的热应力／应变进行了分析;也讨论了EMC材料模式对应力值的影响。结果表明:线弹性模式的EMC的应力值明显高于粘弹性模式的;在热循环载荷下EMC中应力水平并不高,但开裂应变却非常高,因此在EMC中很可能引发疲劳裂纹。     

集成湿热及蒸汽压对塑封QFN器件的层裂影响

针对微电子封装器件的界面层裂失效问题,利用有限元法,集成湿热及蒸汽压力的作用对塑封QFN器件的界面层裂失效问题进行了建模分析,探索了塑封QFN器件参数的优化组合。结果表明,通过对各参数的优化,如EMC的αv为12×10–6/K,引线框架的E为110GPa等,界面危险裂纹尖端点的J积分降低到优化前的1/10~1/100。研究中还发现,封装器件的参数优化组合不唯一,很有必要探讨并选择一种能适合于这种多优化组合设计的方法。     

EMC材料特性对SCSP器件应力及层裂的影响

利用动态机械分析仪测定环氧模塑封(EMC)材料的粘弹特性数据,使用有限元软件MSCMarc分别模拟了EMC材料粘弹性、随温度变化的弹性以及恒弹性三种情况下,SCSP器件在–55～+125℃的等效应力分布及界面层裂。结果表明:125℃和–55℃时最大等效应力分别出现在恒弹性模型、粘弹性模型顶层芯片的悬置区域;将EMC材料视为恒弹性性质时等效应力比粘弹性时大了15.10MPa;–55℃时EMC材料粘弹性模型中裂纹尖端的J积分值比恒弹性模型增长了45%左右,容易引起分层裂纹扩展。     

模塑封器件模塑化合物与铜的界面裂纹扩展

针对环氧模塑化合物(EMC)与铜的界面沿特定路径的准静态界面裂纹扩展问题,利用ANSYS建模仿真了单个位移及循环位移载荷条件下界面裂纹扩展;以界面裂纹扩展的J积分为分析目标,分别在铜材料为线弹性和弹塑性的两种工况下,分析了循环位移载荷对界面裂纹扩展的影响规律。结果表明,在弹性条件下,循环载荷卸载过程裂纹尖端张开角为0,界面闭合;弹塑性条件下,卸载过程裂纹张开角不为0,界面不闭合,且屈服应力越小,两种材料的界面间隙越大,J积分数值越小。     

Evaluation of solder joint reliability in flip-chip packages during accelerated testing

The microstructural investigation and thermomechanical reliability evaluation of the Sn-3.0Ag-0.5Cu solder bumped flip-chip package were carried out during the thermal shock test of the package. In the initial reaction, the reaction product between the solder and Cu mini bump of chip side was Cu₆Sn₅ intermetallic compound (IMC) layer, while the two phases which were (Cu,Ni)₆Sn₅ and (Ni,Cu)₃Sn₄ were formed between the solder and electroless Ni-P layer of the package side. The cracks occurred at the corner solder joints after the thermal shocks of 400 cycles. The primary failure mechanism of the solder joints in this type of package was confirmed to be thermally-activated solder fatigue failure. The premature brittle interfacial failure sometimes occurred in the package side, but nearly all of the failed packages showed the occurrence of the typical fatigue cracks. The finite-element analyses were conducted to interpret the failure mechanisms of the packages, and revealed that the cracks were induced by the accumulation of the plastic work and viscoplastic shear strains.     

Numerical modeling of interfacial delamination propagation in anovel peripheral array package

Interfacial delamination, due to the presence of dissimilar material systems, is one of the primary concerns in electronic package designs. The mismatch in the coefficient of thermal expansion between the different layers in the package can generate high interfacial stresses upon heating or cooling of the structure during fabrication, assembly, or in field use. These stresses, if sufficiently large, can compromise the adhesive integrity of the interface. The propagation of the resulting delamination along an interface can degrade or completely destroy the functionality of the system. The focus of this study is to examine the potential for interfacial delamination propagation in current and future versions of a novel peripheral array package. Two-dimensional (2-D) and three-dimensional (3-D) numerical models were constructed of this package with cracks embedded along a critical interface. The energy release rate associated with interfacial fracture was determined by employing the global energy balance and the crack closure technique. The fracture mode mixity was determined using the crack surface displacement method. These critical fracture parameters were compared with experimentally determined interfacial fracture toughness data to determine the possibility of delamination growth. A material parametric study was also completed using the numerical models with pre-existing delaminations to identify material property trends that would lower the potential for failure. Also, the effect of plastic behavior on interfacial crack growth was studied through J-integral calculations     

Prediction of Delamination Related IC & Packaging Reliability Problems

This paper presents our effort to predict delamination related IC & packaging reliability problems. These reliability problems are driven by the mismatch between the different material properties, such as thermal expansion, hygro-swelling, and/or the degradation of interfacial strength. First of all, a test technique is presented to measure the interfacial strength between packaging materials. Secondly, several reliable non-linear Finite Element models are developed, able to predict the reliability impact of delamination on wire failures, different package structures, and passivation cracks in IC-packages.     

Thin layer acoustic image interpretation and metrology for microelectronics using a broadband model

A broadband model is proposed to describe the nature of ultrasonic pulses in multilayered systems with a sub-wavelength thickness layer. Experimental results are presented to illustrate how delaminations and cracks with foreign material or moisture ingress can appear to be well-bonded and why acoustic images of interfaces with thin layers can sometimes give erroneous indications of the bond state. Applications of this model for delamination analysis of a geometrically complex package are demonstrated. The model can not only predict ultrasonic pulses in the time and frequency domain accurately (the forward problem), but can also provide a theoretical framework for solving the inverse problem, namely, measurement of the thickness and material properties of sub-wavelength thick coatings and layers.     

Evaluation of die edge cracking in flip-chip PBGA packages

Increasing die size and large coefficient of thermal expansion (CTE) mismatch in flip-chip plastic ball grid array (FC-PBGA) packages have made die fracture a major failure mode during reliability testing. Most die fracture observed before was die backside vertical cracking, which was caused by excessive package bending and backside defects. However, due to die edge defects induced by the singulation process and the choice of underfill material, an increasing number of die cracks were found to initiate from die edge and propagate horizontally across the die. In order to improve package reliability and performance, die edge cracking has to be eliminated. An extensive finite element analysis was completed to investigate die edge cracking and find its solutions. A fracture mechanics approach was used to evaluate the effect of various package parameters on die edge initiated fracture. Strain energy release rate was found to be an effective technique for evaluating die edge initiated fracture from singulation-induced flaws. The impact of initial flaw size and a variety of package parameters was investigated. Unlike in die backside cracking, the dominant parameters causing die edge horizontal fracture are more closely related to local effects.     

超声波清洗引入的芯片金属化裂纹机理分析

对某塑封器件进行破坏性物理分析(DPA),发现芯片表面存在玻璃钝化层裂纹和金属化层划伤的缺陷。对缺陷部位进行扫描电子显微镜(SEM)检查和能谱(EDS)分析,通过形貌和成分判断其形成原因为开封后的超声波清洗过程中,超声波振荡导致环氧塑封料中的二氧化硅填充颗粒碰撞挤压芯片表面,从而产生裂纹。最后,进行了相关的验证试验。研究结论对塑封器件的开封方法提出了改进措施,对塑封器件的DPA检测及失效分析(FA)有一定借鉴意义。     

On the mode II popcorn effect in thin packages

Experiments were carried out using P-TQFP-176 packages to study the mode II popcorn effect in thin packages. The doming of the package backside was measured as a function of time and temperature. The measurements were performed using a line projection method. An "accelerated" increase in the doming was found to correlate with the onset of the package crack propagation. It was shown that when a constant critical doming angle is reached, package cracks begin to propagate toward the surface. This critical doming angle was found to be temperature independent between 170°C and 215°C. Furthermore the development of the package doming with time was described by a simple model based on the moisture diffusion from molding compound and die-attach material in combination with a bimaterial plate theory. The water content of the die-attach layer after preconditioning was calculated from the model and it was found to be in good agreement with the results of a three dimensional finite element simulation     

Influence of temperature, humidity, and defect location ondelamination in plastic IC packages

The modified J-integral and the stress intensity factor based on linear elastic fracture mechanics can be applied to predict the growth of interfacial delamination in integrated circuit (IC) packages. One of the key parameters required is the interfacial fracture toughness. This paper describes the measurement of the interfacial fracture toughness as a function of temperature and relative humidity using a three-point bending test. The interfacial fracture toughness was found to decrease with temperature and relative humidity. It is proposed that delaminations propagate from very small voids or defects present at the interface. The effect of the location of these interfacial defects or cracks on delamination was studied. The IC package evaluated in this paper was an 80-pin quad flat package with a 0.2 mm defect or crack at the edge or at the center of the interface. It was found that as the temperature of the package was increased, the stress intensity factor of the edge crack was higher than that of the center crack. However, whether the edge crack will propagate first as temperature is increased depends on the ratio of mode II interface toughness to that of the mode I interface toughness. For the package under investigation, it was established that when this ratio is less than 2.69 the edge crack would propagate first, otherwise the center crack would. For small defects, it was found that the water vapor pressure developed at the interface did not have a significant effect on the value of the crack-tip stress intensity factor     

Effects of Phase Change of Pb-Free Flip-Chip Solders During Board-Level Interconnect Reflow

The impact of phase change (from solid to liquid) on the reliability of Pb-free flip-chip solders during board-level interconnect reflow is investigated. Most of the current candidates for Pb-free solder are tin-based with similar melting temperatures near 230 degC. Thus, Pb-free flip-chip solders melt again during the subsequent board-level interconnect reflow cycle. Solder volume expands more than 4% during the phase change from solid to liquid. The volumetric expansion of solder in a volume constrained by chip, substrate, and underfill creates serious reliability issues. The issues include underfill fracture and delamination from chip or substrate. Besides decreasing flip-chip interconnect reliability in fatigue, bridging through underfill cracks or delamination between neighboring flip-chip interconnects by the interjected solder leads to failures. In this paper, the volume expansion ratio of tin is experimentally measured, and a Pb-free flip-chip chip-scale package (FC-CSP) is used to observe delamination and solder bridging after solder reflow. It is demonstrated that the presence of molten solder and the interfacial failure of underfill can occur during solder reflow. Accordingly, Pb-free flip-chip packages have an additional reliability issue that has not been a concern for Pb solder packages. To quantify the effect of phase change, a flip-chip chip-scale plastic ball grid array package is modeled for nonlinear finite-element analysis. A unit-cell model is used to quantify the elongation strain of underfill and stresses at the interfaces between underfill and chip or underfill and substrate generated by volume expansion of solder. In addition, the strain energy release rate of interfacial crack between chip and underfill is also calculated