Novel degradation effects in dynamically stressed p-channel MOSFETs

The hot carrier degradation of p-channel MOS transistors under dynamic operation modes is studied. Dynamic degradation of submicrometer transistors is compared with the results of conventional static stressing. The application of inverter-like waveforms to the devices under test allows the identification of anomalous degradation modes, which are not consistent with the usually reported hot-carrier-induced punch-through in p-channel transistors. A simple model for the interpretation of the observed effects is presented. The implications of the experimental results for a correct characterization of hot-carrier damage and device lifetime prediction are discussed     

Strained CMOS Devices With Shallow-Trench-Isolation Stress Buffer Layers

In this brief, shallow-trench-isolation (STI) stress buffer techniques, including sidewall stress buffer and channel surface buffer layers, are developed to reduce the impact of compressive STI stress on the mobility of advanced n-type MOS (NMOS) devices. Our investigation shows that a 7% driving current gain at an NMOS device has been achieved, whereas no degradation at a p-type MOS (PMOS) device was observed. The same junction leakage at both the NMOS and PMOS devices was maintained. A stress relaxation model with simulation is thus proposed to account for the enhanced transport characteristics.     

Optimization of LDD devices for cryogenic operation

The optimization of lightly doped drain (LDD) devices to maximize hot-carrier device lifetime at cryogenic temperature is studied. The hot-carrier-induced device degradation behavior and mechanisms of the various LDD and conventional devices are investigated. Carefully designed LDD devices can have better device reliability at low temperature compared to the conventional devices. However, the device lifetime is very short at low temperature for all the devices, and the difference in device lifetime between LDD and control devices is not appreciably large. The degradation behavior of both LDD and non-LDD devices at 77 K does not follow the simple behavior modeled by substrate current. For a given device, the maximum degradation is not observed at the bias condition for maximum substrate current. The optimum LDD design depends on the specific stressing bias conditions at 77 K     

Back-gate bias effect on the subthreshold behavior and theswitching performance in an ultrathin SOI CMOS inverter operating at 77and 300 K

The effect of back-gate bias on the subthreshold behavior and the switching performance in an ultrathin SOI CMOS inverter operating at 300 and 77 K is investigated using a low-temperature device simulator. The simulation results show that the nonzero back-gate bias induces hole pile-up at the back interface, which causes opposite effects on the NMOS and PMOS subthreshold characteristics at 300 and 77 K. Throughout the transient process, at 300 K, for V_B=-5 V operation, hole pile-up at the back interface always exists in the NMOS device. Compared to the zero back-gate bias case, at V_B=-5 V, the risetime of the SOI CMOS inverter is over 5% shorter at 77 and 300 K and the falltime is 5% longer. Prepinch-off velocity saturation in the NMOS device dominates the pull-down transient as a result of the smaller electron critical electric field     

Digital CMOS IC's in 6H-SiC operating on a 5-V power supply

A CMOS technology in 6H-SiC utilizing an implanted p-well process is developed. The p-wells are fabricated by implanting boron ions into an n-type epilayer. PMOS devices are fabricated on an n-type epilayer while the NMOS devices are fabricated on implanted p-wells using a thermally grown gate oxide. The resulting NMOS devices have a threshold voltage of 3.3 V while the PMOS devices have a threshold voltage of -4.2 V at room temperature. The effective channel mobility is around 20 cm ²/Vs for the NMOS devices and around 7.5 cm²/Vs for the PMOS devices. Several digital circuits, such as inverters, NAND's, NOR's, and 11-stage ring oscillators are fabricated using these devices and exhibited stable operation at temperatures ranging from room temperature to 300°C. These digital circuits are the first CMOS circuits in 6H-SiC to operate with a 5-V power supply for temperatures ranging from room temperature up to 300°C     

AC/DC characterization of NMOS and PMOS hot-carrier-induceddegradation under AC/DC stress

The AC/DC measurements of NMOS and PMOS I_dsat shifts are compared following DC stress. The results of the I _dsat shifts are found to be the same. The AC I_dsat measurements were performed under a variety of different conditions (varying frequency, amplitude, and base level) and showed that hot-carrier-induced interfaced states are shallow and fast (<20 ns). AC versus DC stressing was also examined. In PMOS devices, pulsed drain stress was found to be generally quasi-static, while pulsed gate stress produced enhanced device degradation under certain bias conditions. In NMOS transistors AC drain stress was found to be quasi-static in strong device saturation, while AC gate stress resulted in significantly enhanced degradation. In weak device saturation, both gate and drain pulsing resulted in early catastrophic device failure     

Analyzing hot-carrier effects on cold CMOS devices

The operation of discrete and integrated CMOS ring oscillators was evaluated over the temperature range 77-300 K. Gate delays typically decreased by a factor of two at 77 K. Hot-carrier effects were enhanced by low-temperature operation, and transistor transconductance degradation occurred at low temperatures, which did not occur at room temperature as measured in the forward and inverse transistor curves. In marked contrast to dc stressing, ac stressing caused very little circuit degradation at low temperatures. By modeling the low-temperature phenomena at the MOSFET source junction, both hot-electron and hot-hole carrier effects were analyzed.     

The impact of device type and sizing on phase noise mechanisms

Phase noise mechanisms in integrated LC voltage-controlled oscillators (VCOs) using MOS transistors are investigated. The degradation in phase noise due to low-frequency bias noise is shown to be a function of AM-PM conversion in the MOS switching transistors. By exploiting this dependence, bias noise contributions to phase noise are minimized through MOS device sizing rather than through filtering. NMOS and PMOS VCO designs are compared in terms of thermal noise. Short-channel MOS considerations explain why 0.18-/spl mu/m PMOS devices can attain better phase noise than 0.18-/spl mu/m NMOS devices in the 1/f/sup 2/ region. Phase noise in the 1/f/sup 3/ region is primarily dependent upon the upconversion of flicker noise from the MOS switching transistors rather than from the bias circuit, and can be improved by decreasing MOS switching device size. Measured results on an experimental set of VCOs confirm the dependencies predicted by analysis. A 5.3-GHz all-PMOS VCO topology demonstrates measured phase noise of -124 dBc/Hz at 1-MHz offset and -100dBc/Hz at 100-kHz offset while dissipating 13.5 mW from a 1.8-V supply using a 0.18-/spl mu/m SiGe BiCMOS process.     

γ辐照导致中波碲镉汞光伏器件暗电流退化的机理研究

针对红外探测器在空间应用中受到高能粒子辐照后暗电流退化的问题,开展射线对中波碲镉汞（HgCdTe）光伏器件暗电流影响的研究。在室温和77 K温度下,利用60Co-射线对HgCdTe器件进行辐照试验,辐照试验结束后对低温辐照器件进行77 K低温退火和室温退火。通过比较辐照前后和退火后器件的I-V特性、R-V特性和零偏动态电阻R0参数,分析了辐照对HgCdTe器件暗电流的影响机制。试验结果表明:在总剂量为7 Mrad（Si）照条件下,器件暗电流未出现明显的退化;在77 K温度辐照条件下,器件暗电流随着总剂量的增加而增加,且暗电流退化幅度与辐照过程中的偏置有关。研究表明暗电流的退化源于辐照在器件中造成电离损伤,导致器件HgCdTe化层中的界面态和空穴陷阱电荷密度增加。     

Punchthrough behavior in short channel NMOS and PMOS 6H-siliconcarbide transistors at elevated temperatures

An experimental investigation of the effects of high temperature on short channel NMOS and PMOS transistors in 6H-SiC is reported. Punchthrough characteristics are presented and examined at room temperature and 300°C. The punchthrough current increases dramatically for scaled PMOS transistors at high temperature while the temperature dependence of electrical characteristics for short channel NMOS is small. The results presented in this paper also provide insight into design criteria for short channel silicon carbide (SiC) devices intended for operation at elevated temperatures     

CMOS Integration of Dual Work Function Phase-Controlled Ni Fully Silicided Gates (NMOS:NiSi, PMOS:Ni2Si, and Ni31Si12) on HfSiON

The CMOS integration of dual work function (WF) phase-controlled Ni fully silicided (FUSI) gates on HfSiON was investigated. For the first time, the integration of NiSi FUSI gates on n-channel MOS (NMOS) and Ni₃₁Si₁₂ FUSI gates on p-channel MOS (PMOS) with good V_t control to short gate lengths (L_G=50 nm, linear V_t of 0.49 V for NMOS, and -0.37 V for PMOS) is demonstrated. A poly-Si etch-back step was used to reduce the poly-Si height on PMOS devices, allowing for the linewidth-independent formation of NiSi on NMOS and Ni-rich silicides on PMOS with a two-step rapid thermal processing (RTP) silicidation process. The process space for the scalable formation of NiSi on NMOS and Ni₂Si or Ni₃₁ Si₁₂ on PMOS devices was investigated. It was found that within the process window for linewidth-independent NiSi FUSI formation on 100-nm poly-Si NMOS devices, it is possible to control the silicide formation on PMOS devices by adjusting the poly-Si etch-back and RTP1 conditions to obtain either Ni₂Si or Ni₃₁Si₁₂ FUSI gates. A reduction in the PMOS threshold voltage of 90 mV and improved device performance (18% I_on improvement at I_off=100 nA/mum) was obtained for Ni ₃₁Si₁₂ compared to Ni₂Si FUSI gates, as well as a V_t reduction of 350 mV when compared to a single WF flow using NiSi FUSI gates on PMOS     

Operation of short-channel depletion-mode MOS devices atliquid-nitrogen temperature

Experimental observations that depletion-mode MOS devices optimized for room temperature can also work well when immersed in liquid nitrogen are reported in which the classical impurity freeze-out effect seems to vanish on short-channel devices if the drain voltage is not too small. This is attributed to field-assisted ionization mechanisms such as the Poole-Frenkel effect, with possible enhancement by self-heating. The MINIMOS 4 device simulator was modified to introduce this effect and then to check the validity of this assumption by comparison with experimental results. To prove that it is possible to take advantage of this effect a 3-bit feedback adder, used as a benchmark circuit, has been processed in an enhancement-depletion 0.5-μm NMOS technology optimized for room temperature wherein the cooling from 300 to 77 K results in an improvement from 1 to 1.3 GHz for the maximum clock frequency of operation     

Hot-carrier-induced interface state generation in submicrometerreoxidized nitrided oxide transistors stressed at 77 K

The hot carrier degradation at 77 K of silicon MOSFETs fabricated with reoxidized nitrided oxide (ONO) gate dielectrics has been investigated. Measurements have been performed at both room and LN₂ temperatures on n-channel FETs for both ONO and conventional SiO ₂ films. It is found that the hot-carrier immunity of ONO transistors is substantially larger than that of conventional SiO₂ devices, and that the degree of improvement is much larger at room temperature that an 77 K. While the interface state generation does increase dramatically as a result of 77-K stressing, the dominant degradation mechanism can be attributed to a large increase in the drain resistance of the device due to localized charge trapping at the drain side of the channel     

DIBL in short-channel NMOS devices at 77 K

Detailed experimental and two-dimensional numerical simulation results on drain-induced barrier lowering (DIBL) versus channel length at 300 and 77 K in short-channel NMOS devices are presented. It is found that by decreasing the temperature from 300 to 77 K. DIBL in NMOS devices with effective channel lengths (L) from 0.5 to 2.0 μm is improved for the range of L<0.6 μm and L>1.2 μm, but is worse for L between 0.6 and 1.2 μm. The new version of the two-dimensional device numerical simulation program MINIMOS 4.0, which includes device modeling at cryogenic temperatures, was used to investigate this unique characteristic. The measured DIBL characteristics can be explained physically as the transition from surface DIBL through the subsurface DIBL to the bulk DIBL or punchthrough effect at 300 K, but almost a surface DIBL for the whole range of channel length variation at 77 K. Design considerations for the channel doping profile for low-temperature operation based on keeping the same DIBL and V_TH as required for room-temperature operation are briefly discussed     

Low-frequency noise measurements on submicrometre n-channel and p-channel MOSFETs at various operating regions

Silicon founders give in their MOS transistor card models some low-frequency noise parameters for SPICE-based circuit simulators corresponding to pure 1/f ^a or flicker noise, with a very close to unity. MOS transistors used in analogue circuit applications are usually devices with large channel length and width. In low-noise applications, methods such as correlated double sampling are used to suppress the low frequency noise generated by them. Nevertheless, the transistors presently are submicrometre devices exhibiting very different low-frequency noise behaviour. In this paper, experimental low-frequency noise results obtained at room temperature on NMOS and PMOS transistors fabricated using a 0.7 μm process are presented. Both large and small devices on the same process are considered. All regions of operation of transistors are considered. We show that the low-frequency noise behaviour of small area MOSFETs is very different from that of large area devices and that the spectrum is the summation of Lorentzian spectra generated by the switching of individual active traps.     

A low-temperature NMOS technology with Cesium-implanted load devices

A 2-µm enhancement/depletion-type NMOS technology designed for operation at liquid-nitrogen temperature is described. A cesium oxide implant has been used to realize load devices that are not degraded by the freeze out of mobile carriers that occurs in the bulk of conventional depletion-mode transistors at low temperature, Unloaded ring oscillators, fabricated using this technology, have an average propagation delay of 360 ps/stage and a power dissipation of 190 µW/stage with a 2.5-V power supply at 77 K; this represents an improvement in speed of a factor of 2.5 over a conventional NMOS technology operating at room temperature. Simulations predict a further decrease in delay to 200 ps/stage for a 2-/µm process may be achieved through optimization of the Cs-implanted load device without compromising noise margins.     

MOS晶体管中辐照引起的陷阱正电荷的强压退火

电离辐射在 MOS结构的 Si O2 层中建立正陷阱电荷 ,这些正陷阱电荷在正强栅偏压( + 2 0 V)下迅速减少 ,这是由于正栅压引起硅衬底中的电子向 Si O2 层隧道注入 ,从而与陷阱正电荷复合 .正栅压退火不仅对 N沟 MOS结构非常有效 ,对 P沟 MOS结构也有一定的影响 .给出了辐照后的 NMOS和 PMOS晶体管在强正栅压下退火的实验结果 ,阐明了正栅压下的“隧道退火”机理 .     

An enhanced MOSFET threshold voltage model for the 6–300 K temperature range

An enhanced threshold voltage model for MOSFETs operating over a wide range of temperatures (6–300K) is presented. The model takes into account the carrier freeze-out effect and the external field-assisted ionization to address the temperature dependence of MOS transistors. For simplicity, an empirical function is incorporated to predict short channel effects over the temperature range. The results from the proposed model demonstrate good agreement with NMOS and PMOS transistors measured from fabricated chips.     

Strong carrier freezeout above 77 K in tellurium-doped buried-channel MOS transistors

Semiconductor devices are almost universally based on an assumption of full ionization of dopant impurities, a natural condition at room temperature for conventional shallow-energy-level (activation energy ∼ 0.05 eV) dopant species. At temperature T < 30 K for conventional dopants, freezeout of the equilibrium carrier density becomes severe and uncompensated dopants are in the neutral charge state. The high resistivity of such frozen-out regions might have useful applications for device structures. However, the temperature (< 30 K) required makes such applications generally impractical. Freezeout-induced high-resistivity regions at 77 K would be considerably more interesting. We demonstrate strong freezeout of a buried-channel MOS transistor at 77 K using tellurium as the channel dopant.     

Performance and physical mechanisms in SIMOX MOS transistorsoperated at very low temperature

The performance and the physical properties of SIMOX (separation by implantation of oxygen) MOS transistors are studied from room to liquid helium temperatures with particular emphasis on the behavior of carrier mobility, threshold voltage, subthreshold swing, leakage current, and kink effect. Various SIMOX substrates, such as partially depleted films annealed at low or high temperature and ultrathin films (100 nm), are analyzed and compared. Enhancement- and depletion-mode devices with different doping levels, channel lengths, and geometries are considered. The front and back channels are activated independently in order to assess the electrical quality of both interfaces. Comparison with bulk Si transistors reveals a number of interesting features of SIMOX devices, which are explained using comprehensive models. The advantages of low-temperature operation of SIMOX transistors are related to the decrease in subthreshold swing and leakage, increase in mobility, and reasonable shift of the threshold voltage. The performance of ultra-thin-film devices is excellent over the whole range or temperatures, whereas partially depleted transistors exhibit optimum performance at 77 K