A 0.6V 1.07 μW/Channel neural interface IC using level-shifted feedback

This paper presents a 16-channel low-power neural interface IC for in-vivo neural recording applications. Each recording channel consists of two AC-coupled close-loop amplifiers: a low noise amplifier (LNA) amplifies the weak neural signal by 26 dB, and a programmable gain amplifier (PGA) provides an additional gain of 8 dB–26 dB. The LNA employs a current-reusing telescopic topology to reduce noise for achieving a better noise efficiency factor (NEF). To further reduce the power consumption, we propose a level-shifted feedback (LSFB) technique to lower the operational supply voltage. Theoretic analysis shows that the proposed amplifier with LSFB halves the minimum required supply voltage compared to conventional AC-coupled close-loop counterparts without degenerating the noise performance. The prototype chip is fabricated in 65 nm CMOS process. Operating under a single 0.6 V supply, each recording channel consumes 1.07 μW. The input-referred noise integrating from 10 Hz to 10 kHz is 5.18 μV, and the NEF/PEF is 2.94/5.19.     

低功耗全集成微电子神经桥接电路的设计

神经传导束中断是脊髓损伤后功能障碍的主要原因。微电子神经桥是利用微电子芯片或模块旁路受损神经传导束,重建因神经通路中断而丧失的功能。设计了一种基于0.5μm CMOS工艺的低功耗、全集成微电子神经桥电路,版图面积为1.21 mm×1.18 mm。详细介绍了微电子神经桥核心单元电路低功耗两级运算放大器和输入/输出轨至轨运算放大器的设计。仿真结果表明,微电子神经桥接系统的通频带完全覆盖神经信号的频谱范围,增益可调至足够大,适用于神经信号探测和功能电激励。系统在±2.5 V供电情况下,功耗仅为3.4 mW,低功耗和系统全集成使得微电子神经桥向最终实现体内植入迈进了一步。     

Highly integrated 60 GHz transmitter and receiver MMICs in a GaAs pHEMT technology

Highly integrated transmitter and receiver MMICs have been designed in a commercial 0.15 /spl mu/m, 88 GHz f/sub T//183 GHz f/sub MAX/ GaAs pHEMT MMIC process and characterized on both chip and system level. These chips show the highest level of integration yet presented in the 60 GHz band and are true multipurpose front-end designs. The system operates with an LO signal in the range 7-8 GHz. This LO signal is multiplied in an integrated multiply-by-eight (X8) LO chain, resulting in an IF center frequency of 2.5 GHz. Although the chips are inherently multipurpose designs, they are especially suitable for high-speed wireless data transmission due to their very broadband IF characteristics. The single-chip transmitter MMIC consists of a balanced resistive mixer with an integrated ultra-wideband IF balun, a three-stage power amplifier, and the X8 LO chain. The X8 is a multifunction design by itself consisting of a quadrupler, a feedback amplifier, a doubler, and a buffer amplifier. The transmitter chip delivers 3.7/spl plusmn/1.5 dBm over the RF frequency range of 54-61 GHz with a peak output power of 5.2 dBm at 57 GHz. The single-chip receiver MMIC contains a three-stage low-noise amplifier, an image reject mixer with an integrated ultra-wideband IF hybrid and the same X8 as used in the transmitter chip. The receiver chip has 7.1/spl plusmn/1.5 dB gain between 55 and 63 GHz, more than 20 dB of image rejection ratio between 59.5 and 64.5 GHz, 10.5 dB of noise figure, and -11 dBm of input-referred third-order intercept point (IIP3).     

用于脑电信号记录的低噪声低功耗放大器

为了满足脑电信号(EEG)记录阵列的应用需求,设计了一种全差分的低噪声、低功耗放大器电路.该电路利用亚阈值区晶体管作为伪电阻,与输入电容和反馈电容形成高通通路,有效抑制了输入信号的直流失调电压,无需片外隔直电容,实现了电路的全集成.放大器中的跨导放大器(OTA)采用亚阈值晶体管进行设计,实现了较大的输出摆幅、良好的功耗和噪声性能.放大器电路采用SMIC 130 nm 1P8M混合信号工艺实现,芯片面积0.6 mm2.测试结果表明,在电源电压0.6V时,放大器可处理信号带宽为10 Hz～7 kHz,等效输入噪声的均方根值为3.976 μV,噪声有效因子为3.658,总功耗仅为2.4 μW.     

用于功率放大器的随温度可调负压偏置电路

设计了一种应用于GaN功率放大器栅极调制的随温度可调负压偏置电路。电路由电压基准模块、温度传感器模块、比较器阵列以及误差放大器及其对应的功率管与反馈电阻等组成,通过基准电压与温度传感器输出电压的比较,输出数字控制信号到反馈电阻中的可变电阻模块,改变可变电阻阻值进而改变电路输出电压,实现芯片电压随温度可调。电路结构简单、易于实现、应用方便,同时电路中引入了修调电阻结构,极大提高了基准输出精度。电路芯片面积为1.10 mm×0.64 mm,采用0.5μm CMOS工艺进行了流片并完成了后期测试验证。结果表明,芯片可实现输出电压的随温度可调,有效解决了GaN功率放大器在相同的栅极偏置电压下输出功率随温度升高而减小的问题。     

Exploiting low complex digital predistortion to improve wideband nonlinear satellite downlinks

With the increasing demand for higher data rate, increasing throughput requires wider bandwidth. Due to the nonlinear effect of power amplifier, severe nonlinear distortion effects will appear onboard satellite. Digital predistortion (DPD) scheme is usually employed to compensate for the distortions and memory effects introduced by traveling wave tube amplifier (TWTA) and output multiplexing filter (OMUX). In conventional predistorter, the signal loss of band‐limited feedback signal output through OMUX is usually ignored. Actually, it will affect the linear effect of TWTA. In order to solve the problem as to improve wideband nonlinear satellite downlink, this paper introduces a novel spectral extrapolation method based on deep neural network to recover the band‐limited feedback signal. On this basis, an advanced orthogonal matching pursuit algorithm is adopted in the nonlinear TWTA model construction to further reduce the DPD complexity. The proposed setup effectively compensates the distortions and is well suited for systems that generate data bits on satellites.     

低功耗无线动物神经信号采集模块设计

文中根据RF无线射频原理,提出了一个适用于小体型动物的纯模拟、低功耗的无线神经信号采集模块设计方案。相比于数模混合方案,纯模拟的实现方案具有尺寸小、功耗低以及结构简单等优势。整个采集模块可以分为模拟前端放大和无线数据传输两部分。通过选用低功耗、低噪声的仪表放大器INA333和运算放大器OPA333构成模拟前端放大电路的两级放大结构,降低了电路的功耗和尺寸。通过添加反馈电感实现的反馈增强效应降低了Colpitts振荡器功耗。采用三极管极间电容对振荡器进行FM调制构成纯模拟无线数据传输电路,使得采集模块具有小尺寸、低功耗以及无线数据传输的特点。电路仿真以及实验测试结果均表明,该模块可以完成动物神经信号的无线采集,具有一定的实用性。     

微电容超声换能器的前端专用集成电路设计

针对微电容超声换能器(CMUT)微弱电流信号检测的要求,设计了一种用于CMUT的前端专用集成电路——运算放大器(OPA)电路。运算放大器电路采用两级放大结构,第一级采用全差分折叠-共源共栅结构,输出级采用AB类控制的轨到轨输出级,在运算放大器电路反相输入端和输出端通过一个反馈电阻实现CMUT电流信号到电压信号的转换。采用GlobalFoundries 0.18μm的标准CMOS工艺进行了仿真设计和流片,芯片尺寸为226μm×75μm。仿真结果表明,运算放大器的开环增益为62 dB,单位增益带宽为30 MHz,在3 MHz处的输入参考噪声电压为2.9μV/Hz^1/2,电路采用±3.3 V供电,静态功耗为11 mW。测试结果表明仿真与实测结果相符,该运算放大器电路能够实现CMUT微弱电流信号检测功能。     

Gigahertz-band high-gain low-noise AGC amplifiers in fine-line NMOS

The design and test results of a single-chip NMOS automatic gain control (AGC) amplifier are described. The amplifier has a maximum flat gain of 50 dB, dynamic range of 70 dB, and a noise figure of 11 dB. The flat response from near DC to a 3-dB bandwidth of 1 GHz does not require tuning of any peaking circuits. The chip is also capable of operating at 3 GHz with unity gain delivering -8 dBm into a 50-/spl Omega/ load. The global feedback scheme designed for this chip stabilizes it against large shifts in threshold voltage and ambient temperature variation of 170/spl deg/C. This feedback scheme can provide stable DC feedback for a forward amplifier gain of at least 60 dB. Application of this application in the design of low-noise high-speed fibre-optic systems is envisaged.     

开关式低压CMOS温度传感器的设计与实现

介绍了一种基于0.18μm CMOS工艺,具有开关功能的低压集成温度传感器。该温度传感器利用半导体pn结的电流电压与温度有关的特性,获取双极晶体管基极-发射极电压差值ΔVBE,采用仪表放大器进行后级放大。仪表放大器由两个采用折叠式共源共栅结构,带有PD开关信号的运算放大器作为反馈系统,放大倍数为7。用ADE工具,对整个电路在工作电压1.8 V、偏置电流20μA下进行仿真,得到其精度为1.58 mV/℃,再在不同工艺角下进行仿真验证。版图总面积为320μm×280μm。该设计已经在一款数字视频芯片中得到实现,用于实时检测芯片温度。实际测试结果与模拟仿真结果基本相同。     

信号源内阻在模拟电路中的作用

本文从单级放大电路、多级放大电路、负反馈放大电路三个方面，分析了信号源内阻对电路的影响。指出多级放大器输入阻抗应尽量高，输出阻抗应尽量低；串联负反馈信号源内阻越小越好，并联负反馈信号源内阻越大越好。     

短波红外焦平面弱信号读出的高帧频模拟链路设计

针对短波红外焦平面阵列探测器弱信号耦合、高帧频输出和噪声抑制的要求, 文中设计了512256面阵探测器读出电路（ROIC）的高帧频模拟信号链路结构。完整的模拟信号链包含运放积分型（CTIA）单元输入级、相关双采样、电荷放大器和互补型输出级。在低温模型基础上,进行了前仿真和提取版图寄生参数的后仿真。仿真得到输出动态范围为2.8V,8路输出的工作帧频高于250Hz。基于CSMC-6S05DPTM0.5m 工艺完成流片,读出电路ROIC芯片的测试结果与仿真结果基本一致,为短波红外焦平面探测器弱信号读出提供了有效的设计选择。     

基于水声器耦合的低频功率放大器的设计

低频功率放大器作为电子设备的后级放大电路,它的主要作用是将前级的音频信号进行功率放大以推动负载工作,获得良好的声音效果。基于此,设计了水声信号发生系统中的低频功率放大电路,该电路以前级放大芯片NE532、功率放大,TDA2030芯片和直流稳压电源为核心,实现了对小信号的功率放大,经multisim仿真,该电路工作稳定正常,输出波形无失真,在输出功率以及放大增益等方面均满足设计要求。     

A CMOS current-mode operational amplifier

A fully differential-input, differential-output, current-mode operational amplifier (COA) is described. The amplifier utilizes three second-generation current conveyors (CCIIs) as the basic building blocks. It can be configured to provide either a constant gain-bandwidth product in a fully balanced current-mode feedback amplifier or a constant bandwidth in a transimpedance feedback amplifier. The amplifier is found to have a gain-bandwidth product of 3 MHz, an offset current of 0.8 μA (signal range ±700 μA), and a (theoretically) unlimited slew rate. The amplifier is realized in a standard CMOS 2.4-μm process     

多通道神经信号再生集成电路

介绍了一个六通道的神经信号再生集成电路.每一个通道均由检测电路和激励电路组成.检测电路用低噪声、高共模抑制比的仪器放大器从神经元的上端探测神经信号.激励电路中,采用反相运算放大器来进一步放大神经信号,放大的神经信号通过一个缓冲器来激励受损神经的下端神经元,实现了神经信号的传递,从而实现再生的功能.电路采用CSMC0.5 μm CMOS工艺设计,整个六通道的芯片版图面积为1.9 mm×1.6 mm.电路的后仿结果如下:在士2.5 V的供电电压下,单通道电路的功耗为3.9 mW;在100 Hz到7 kHz的频率范围内,等效输入噪声为25.4 nV/sqrt(Hz);增益带宽积达到7.6MHz,可实现60 dB到110 dB的可调增益,输出阻抗为6.2 Ω.     

A synchronous phase-lock loop detector for integrated AM radio

A synchronous phase-lock loop AM detector has been realized on a single chip in a bipolar process with an f/SUB T/ of 400 MHz. The circuit accepts input signals at an IF frequency of 450-500 kHz with effective values between 20 and 100 mV. The phase-lock loop capture range is about 150 kHz. AM signals with over 80% modulation depth can be demodulated with less than 1% harmonic distortion in the audio output signal. The power dissipation of the chip is 120 mW at 8 V. The total chip size is 1900/spl times/1300 /spl mu/m/SUP 2/. Since the VCO and the 90/spl deg/ phase shift are completely realized on-chip, large signals at the IF frequency do not occur at the pins of the IC, and parasitic feedback of such signals to the IF amplifier input is minimized.     

数控功率放大器的设计与实现

介绍了数控功率放大器的设计与调试结果。该数控功率放大器的作用在于对前级电路产生的信号进行转换、滤波、功率放大等处理,将其转换为换能器所需的大功率正弦信号,并通过Pc机在外部控制其放大增益。该电路以单片机、集成6阶Butterworth低通滤波芯片以及大功率运算放大器为核心,通过标准RS-232接口与PC进行通信,具有信号放大增益实时可调、对干扰信号具有良好的抑制作用等优点。经调试,该电路工作稳定,输出波形无失真,在输出功率、放大增益以及波纹系数等方面均满足设计要求。     

A CMOS 140-mW fourth-order continuous-time low-pass filter stabilized with a class AB common-mode feedback operating at 550 MHz

A 550-MHz linear-phase low-pass continuous-time filter is described. The operational transconductance amplifier (OTA) is based on complementary differential pairs in order to achieve high-frequency operation. A common-mode feedback (CMFB) based on a Class AB amplifier with improved stability at high frequencies is introduced. Results for the stand alone OTA show a unity gain frequency of 1 GHz while the excess phase is less than 5/spl deg/. The filter is based on G/sub m/-C biquads and achieves IM3 <-40 dB for a two-tone input signal of -10 dBm each. The power consumption of the fourth-order filter is 140 mW from supply voltages of /spl plusmn/1.65 V. The chip was fabricated in a standard 0.35-/spl mu/m CMOS technology.     

Injection-locked oscillator chain: a possible solution tomillimeter-wave MMIC synthesizers

An injection-locked oscillator (ILO) monolithic-microwave integrated-circuit (MMIC) chain-a cascade of low- and high-frequency-band ILOs-is proposed for simple and cost-effective millimeter-wave local oscillators and synthesizers. Primary 5, 20, and 50 GHz-band ILO MMICs are designed and fabricated as an ILO-chain chip set. Improvements made to the active combiner/dividers (A-C/D's), the heart of the MMIC, in the external feedback path for an amplifier to suppress spurs at the output port of 5 and 20 GHz band ILOs, and enhance the loop gain and layout flexibility at millimeter-wave frequencies. Fabricated 5 and 20 GHz-band ILO MMICs are chain-connected to confirm the design techniques. The ILO chain provides a 20 GHz-band output signal for an injection signal of 571 MHz, as well as a very low level of spurs of less than -45 dBc around the output signal. The measured results show that the proposed ILO chain is extremely suitable for developing full millimeter-wave MMIC frequency synthesizers     

A SiGe BiCMOS burst-mode 155-Mb/s receiver for PON

In this paper, we present an integrated 155-Mb/s burst-mode receiver (BMR) for passive optical network (PON) applications. The chip has been designed to receive optical signals over a wide dynamic range (-30 to -8 dBm) and temperature range (-40°C to +85°C). The chip was implemented using a 0.8-μm 35-GHz SiGe BiCMOS technology and occupies an area of 4.3×4.9 mm² with a power consumption of 500 mW from a supply voltage of 5 V (3.3 V for the digital PECL output). In the receiver analog front end, we used a low-noise wide-band transimpedance amplifier followed by a nonlinear gain stage to cover a wide signal range without changing the transimpedance gain. The circuit dynamically adjusts the receiver threshold voltage through a feedback loop, thus optimizing the pulsewidth distortion and canceling the optical as well as the electrical offset voltages