准循环LDPC码的半并行译码器设计

利用准循环LDPC码的结构特点,使用半并行结构的译码器可以实现复杂度和译码速率的有效折中.提出了一种半并行结构的实现方法,并通过FPGA上的实现验证了性能.     

适用于准循环LDPC码译码器的新型循环移位置换结构设计

循环移位置换单元是准循环LDPC码的部分并行译码器的重要组成部分。该文研究并证明了Reverse Banyan交换结构在实现信息循环移位时各个基本交换单元的连接规律。基于该规律设计了基于可预置选路算法的无阻塞循环移位置换结构。相比Benes交换结构和Reverse Banyan交换结构,提高了信息循环移位交换的速率,且占用较少的硬件资源和面积。最后设计了一个出线转换单元,该单元适用于各种循环移位交换结构。     

A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes

This paper presents a memory efficient partially parallel decoder architecture suited for high rate quasi-cyclic low-density parity-check (QC-LDPC) codes using (modified) min-sum algorithm for decoding. In general, over 30% of memory can be saved over conventional partially parallel decoder architectures. Efficient techniques have been developed to reduce the computation delay of the node processing units and to minimize hardware overhead for parallel processing. The proposed decoder architecture can linearly increase the decoding throughput with a small percentage of extra hardware. Consequently, it facilitates the applications of LDPC codes in area/power sensitive high-speed communication systems     

基于Min-Sum近似算法的QC-LDPC译码器

由于BP算法中的非线性运算较复杂,实现中通常采用Min-Sum近似简化译码算法.针对译码过程中需要存储大量信息的问题,本文提出了一种基于Min-Sum近似算法的QC-LDPC译码器.通过重新安排Min-Sum近似算法中的运算,并将校验节点信息以一种压缩冗余的形式表示,大大减少了译码器所需的存储空间.针对QC-LDPC码校验矩阵准循环的特性,译码过程中以块为单位对信息进行更新,且可以实现多种消息传递调度策略.为进一步减少存储空间,对变量节点信息采用了非线性量化,根据密度演进理论对量化规则进行了优化.     

Decoder Design for RS-Based LDPC Codes

This brief studies very large-scale integration (VLSI) decoder architectures for RS-based low-density parity-check (LDPC) codes, which are a special class of LDPC codes based on Reed-Solomon codes. The considered code ensemble is well known for its excellent error-correcting performance and has been selected as the forward error correction coding scheme for 10GBase-T systems. By exploiting the shift-structured properties hidden in the algebraically generated parity-check matrices, novel decoder architectures are developed with significant advantages of high level of parallel decoding, efficient usage of memory, and low complexity of interconnection. To demonstrate the effectiveness of the proposed techniques, we completed a high-speed decoder design for a (2048, 1723) regular RS-LDPC code, which achieves 10-Gb/s throughput with only 820 000 gates. Furthermore, to support all possible RS-LDPC codes, two special cases in code construction are considered, and the corresponding extensions of the decoder architecture are investigated.     

可配置LDPC译码器中低复杂度移位网络的设计

针对可配置LDPC译码器,提出了一种低复杂度的移位网络结构,明显降低了硬件实现的复杂度。基于结构化LDPC译码器的两个特点:输入端的个数是一个常数的倍数、所有移位都是循环移位,提出易于实现且延迟很小的移位网络控制信号生成算法。此外,针对IEEE 802.16e标准的LDPC译码器,设计了采用这种结构的移位电路。基于SMIC 130nm工艺进行仿真,综合结果表明,该电路占用的芯片面积为0.11mm2,最高频率为430MHz。     

一种改进的基于有限域的准循环LDPC码设计方法

结合有限域方法和具有简单递归编码特性的Tam结构,提出了一种新的准循环LDPC码构造方法.该方法首先利用有限域方法构造出校验矩阵,并得到其相应的指数矩阵,接着采用具有Tam结构的校验矩阵对应的二元基矩阵,两者进行掩膜运算(mask),得到新的指数矩阵,最后构造出的准循环LDPC码兼具有限域方法的良好纠错特性和Tam结构的简单递归编码特性.仿真结果表明,所提方法构造的准循环LDPC码的BER(Bit Error Rate)性能要优于Tam码和802.16e码.     

高码率LDPC码译码器的优化设计与实现

本文以CCSDS推荐的7/8码率LDPC码为例,提出了一种适于高码率LDPC码译码器的硬件结构优化方法。高码率的LDPC码通常也伴随着行重与列重的比例较高的问题。本方法是在拆分校验矩阵的基础上,优化常用的部分并行译码结构,降低了高码率LDPC码译码时存在的校验节点运算单元(CNU)与变量节点运算单元(VNU)之间的复杂度不平衡,并由此提高了译码器的时钟性能。实验证明,本文方案提供的结构与常用的部分并行译码结构相比,节省硬件资源为41％;采用与本文方案相同的硬件资源而未经矩阵拆分的部分并行译码方案的码速率为本文方案的75％。     

同步部分并行结构的准循环LDPC码译码器

该文根据准循环LDPC码的结构特点,提出了一种同步部分并行结构的译码器。在译码器中,校验节点处理单元和变量节点处理单元同时并行工作,使得迭代过程中新产生的软信息能够被提前使用,加快迭代的收敛速度。同时,采用差分演化的方法对各节点处理单元的起始位置进行优化,进一步提高了译码器的性能。仿真结果表明,该方案在译码性能和复杂度上都要优于现有其他方案,适合高速译码器的实现。     

基于FPGA的不可分层LDPC码译码器

针对不可分层LDPC码无法采用分层译码算法的问题,设计了一种新型的LDPC码分层译码器。与传统分层译码器的结构不同,新结构在各层间进行并行更新,各层内进行串行更新。通过保证在不同分层的同一变量节点不同时进行更新,达到分层译码算法分层递进更新的目标。选用Altera公司的CycloneⅢ系列EP3C120器件,实现码率3/4,码长8 192的(3,12)规则不可分层QC-LDPC码译码器的布局布线,在最大迭代次数为5次时,最高时钟频率可以达到45.44 MHz,吞吐量可以达到47.6 Mbps。     

High-Rate Nonbinary Regular Quasi-Cyclic LDPC Codes for Optical Communications

The parity-check matrix of a nonbinary (NB) low-density parity-check (LDPC) code over Galois field GF(q) is constructed by assigning nonzero elements from GF(q) to the 1s in corresponding binary LDPC code. In this paper, we state and prove a theorem that establishes a necessary and sufficient condition that an NB matrix over GF(q), constructed by assigning nonzero elements from GF(q) to the 1s in the parity-check matrix of a binary quasi-cyclic (QC) LDPC code, must satisfy in order for its null-space to define a nonbinary QC-LDPC (NB-QC-LDPC) code. We also provide a general scheme for constructing NB-QC-LDPC codes along with some other code construction schemes targeting different goals, e.g., a scheme that can be used to construct codes for which the fast-Fourier-transform-based decoding algorithm does not contain any intermediary permutation blocks between bit node processing and check node processing steps. Via Monte Carlo simulations, we demonstrate that NB-QC-LDPC codes can achieve a net effective coding gain of 10.8 dB at an output bit error rate of 10^-12. Due to their structural properties that can be exploited during encoding/decoding and impressive error rate performance, NB-QC-LDPC codes are strong candidates for application in optical communications.     

800Mbps准循环LDPC码译码器的FPGA实现

本文提出了一种适用于准循环低密度校验码的低复杂度的高并行度译码器架构。通常准循环低密度校验码不适于设计有效的高并行度高吞吐量译码器。我们通过利用准循环低密度校验码的奇偶校验矩阵的结构特点,将其转化为块准循环结构,从而能够并行化处理译码算法的行与列操作。使用这个架构,我们在Xilinx Virtex-5 LX330 FPGA上实现了(8176,7154)有限几何LDPC码的译码器,在15次迭代的条件下其译码吞吐量达到800Mbps。      

Memory-Efficient and High-Throughput Decoding of Quasi-Cyclic LDPC Codes

We propose turbo-sum-product (TSP) and shuffled-sum-product (SSP) decoding algorithms for quasi-cyclic low-density parity-check codes, which not only achieve faster convergence and better error performance than the sum-product algorithm, but also require less memory in partly parallel decoder architectures. Compared with the turbo decoding algorithm, our TSP algorithm saves the same amount of memory and may achieve a higher decoding throughput. The convergence behaviors of our TSP and SSP algorithms are also compared with those of the SP, turbo, and shuffled algorithms by their extrinsic information transfer (EXIT) charts.     

Construction of Irregular LDPC Codes by Quasi-Cyclic Extension

In this correspondence, we propose an approach to construct irregular low-density parity-check (LDPC) codes based on quasi-cyclic extension. When decoded iteratively, the constructed irregular LDPC codes exhibit a relatively low error floor in the high signal-to-noise ratio (SNR) region and are subject to relatively few undetected errors. The LDPC codes constructed based on the proposed scheme remain efficiently encodable     

低复杂度校验节点调度的LDPC串行译码算法

置信传播算法（BP）是低密度校验码（LDPC）一种常用的译码算法。为了改善动态调度算法（IDS）在提高BP算法译码性能时复杂度较高的缺陷,提出了一种基于校验节点的串行消息更新策略（Min2-CSBP）。该策略定义了一种基于校验节点的可靠度测度并能近似表征对应的校验节点的可靠程度。可靠度测度仅用于确定消息更新的次序,而在消息更新的计算中仍然采用精确的概率值。每次迭代中对可靠度按升序排序并按此顺序进行消息更新。随后,对Flood算法、CSBP算法、NW-RBP算法及Min2-CSBP算法进行了复杂度对比。仿真结果表明:在使用LDPC短码时,Min2-CSBP算法比Flood算法及CSBP算法显著提高了误码率性能,并减少了迭代次数。      

High Performance Non-Binary Quasi-Cyclic LDPC Codes on Euclidean Geometries LDPC Codes on Euclidean Geometries

This paper presents algebraic methods for constructing high performance and efficiently encodable non-binary quasi-cyclic LDPC codes based on flats of finite Euclidean geometries and array masking. Codes constructed based on these methods perform very well over the AWGN channel. With iterative decoding using a Fast Fourier Transform based sum-product algorithm, they achieve significantly large coding gains over Reed-Solomon codes of the same lengths and rates decoded with either algebraic hard-decision Berlekamp-Massey algorithm or algebraic soft-decision K?tter-Vardy algorithm. Due to their quasi-cyclic structure, these non-binary LDPC codes on Euclidean geometries can be encoded using simple shiftregisters with linear complexity. Structured non-binary LDPC codes have a great potential to replace Reed-Solomon codes for some applications in either communication or storage systems for combating mixed types of noise and interferences.     

基于素域构造的准循环低密度校验码

该文提出一种基于素域构造准循环低密度校验码的方法。该方法是Lan等所提出基于有限域构造准循环低密度校验码的方法在素域上的推广,给出了一类更广泛的基于素域构造的准循环低密度校验码。通过仿真结果证实：所构造的这一类准循环低密度校验码在高斯白噪声信道上采用迭代译码时具有优良的纠错性能。     

Optimal Overlapped Message Passing Decoding of Quasi-Cyclic LDPC Codes

Efficient hardware implementation of low-density parity-check (LDPC) codes is of great interest since LDPC codes are being considered for a wide range of applications. Recently, overlapped message passing (OMP) decoding has been proposed to improve the throughput and hardware utilization efficiency (HUE) of decoder architectures for LDPC codes. In this paper, we first study the scheduling for the OMP decoding of LDPC codes, and show that maximizing the throughput gain amounts to minimizing the intra- and inter-iteration waiting times. We then focus on the OMP decoding of quasi-cyclic (QC) LDPC codes. We propose a partly parallel OMP decoder architecture and implement it using FPGA. For any QC LDPC code, our OMP decoder achieves the maximum throughput gain and HUE due to overlapping, hence has higher throughput and HUE than previously proposed OMP decoders while maintaining the same hardware requirements. We also show that the maximum throughput gain and HUE achieved by our OMP decoder are ultimately determined by the given code. Thus, we propose a coset-based construction method, which results in QC LDPC codes that allow our optimal OMP decoder to achieve higher throughput and HUE.     

多码率多边类型LDPC码译码器的设计与实现

提出了一种固定码长的多码率多边LDPC码译码器,该译码器采用对校验比特信息进行间隔删余的算法实现其多码率译码,并设计了一种适合多码率多边LDPC码的部分并行译码结构。基于该结构在FPGA平台上实现了码长为640 bit,码率为0.5～0.8的多边LDPC码译码器。