A fully monolithic 260-/spl mu/W, 1-GHz subthreshold low noise amplifier

A micro-power complementary metal oxide semiconductor (CMOS) low-noise amplifier (LNA) is presented based on subthreshold MOS operation in the GHz range. The LNA is fabricated in an 0.18-/spl mu/m CMOS process and has a gain of 13.6 dB at 1 GHz while drawing 260 /spl mu/A from a 1-V supply. An unrestrained bias technique, that automatically increases bias currents at high input power levels, is used to raise the input P1dB to -0.2 dBm. The LNA has a measured noise figure of 4.6 dB and an IIP3 of 7.2 dBm.     

A power efficient differential 20-GHz low noise amplifier with 5.3-GHz 3-dB bandwidth

A 20-GHz differential two-stage low-noise amplifier (LNA) is demonstrated in a foundry digital 130-nm CMOS technology with 8-metal layers. This LNA has 20-dB voltage gain and /spl sim/5.5-dB noise figure at 20GHz with 24-mW power consumption. The measured IP/sub 1 dB/ and IIP/sub 3/ are -11 dBm and -4dBm. Compared to the previously published bulk CMOS LNAs operating above 20GHz, this LNA has exceptionally low power and current consumption especially considering its differential topology and wide bandwidth.     

Packaged single-ended CMOS low noise amplifier with 2.3 dB noise figure and 64 dBm IIP/sub 2/

A single-ended low noise amplifier (LNA) implemented in a foundry 0.18 /spl mu/m CMOS process is tested on a PC board using the chip-on-board technique. The measured S/sub 11/ and S/sub 22/ are less than -10 dB over 5.15-5.35 GHz, which is the lower subband of UNII and HIPERLAN/2 band. The measured noise figure is 2.0 dB and power gain is 15.5 dB at 5.15 GHz, while drawing 5.8 mA of current from a 1.8 V supply. The measured IIP/sub 2/ is greater than 64 dBm. This extremely high IP/sub 2/ is due to the tuned response of the LNA. The LNA is suitable for WLAN applications in the lower UNII and HIPERLAN/2 subband.     

A 20-GHz low-noise amplifier with active balun in a 0.25-/spl mu/m SiGe BICMOS technology

A 20-GHz low-noise amplifier (LNA) with an active balun fabricated in a 0.25-/spl mu/m SiGe BICMOS (f/sub t/=47 GHz) technology was presented by the authors in 2004. The LNA achieves close to 7 dB of gain and a noise figure of 4.9 dB with all ports simultaneously matched to 50 /spl Omega/ with better than -16 dB of return loss. The amplifier is highly linear with an IP/sub 1dB/ of 0 dBm and IIP/sub 3/ of 9 dBm, while consuming 14 mA of quiescent current from a 3.3-V rail, with temperature-compensated biasing. To the authors' knowledge, the LNA delivers the lowest reported noise figure and highest linearity for a silicon implementation of a combined active balun and LNA at 20 GHz, and is the first implementation of an active balun with an LC degenerated emitter-coupled pair. Here we expand on that work, with an analysis of the balun operation and noise optimization of the design.     

0.18 /spl mu/m 3-6 GHz CMOS broadband LNA for UWB radio

A 3-6 GHz CMOS broadband low noise amplifier (LNA) for ultra-wideband (UWB) radio is presented. The LNA is fabricated with the 0.18 /spl mu/m 1P6M standard CMOS process. Measurement of the CMOS LNA is performed using an FR-4 PCB test fixture. From 3 to 6 GHz, the broadband LNA exhibits a noise figure of 4.7-6.7 dB, a gain of 13-16 dB, and an input/output return loss higher than 12/10 dB, respectively. The input P/sub 1 dB/ and input IP3 (IIP3) at 4.5 GHz are about -14 and -5 dBm, respectively. The DC supply is 1.8 V.     

A matrix amplifier in 0.18-/spl mu/m SOI CMOS

A fully integrated matrix amplifier with two rows and four columns (2-by-4) fabricated in a three-layer metal 0.18-/spl mu/m silicon-on-insulator (SOI) CMOS process is presented. It exhibits an average pass-band gain of 15 dB and a unity-gain bandwidth of 12.5 GHz. The input and output ports are matched to 50 /spl Omega/ using m-derived half sections; the measured S/sub 11/ and S/sub 22/ values exceed -7 and -12 dB, respectively. Integrated in 2.0/spl times/2.9mm/sup 2/, it dissipates 233.4 mW total from 2.4- and 1.8-V power supplies.     

A novel CMOS low-noise amplifier design for 3.1- to 10.6-GHz ultra-wide-band wireless receivers

An ultra-wideband (UWB) 3.1- to 10.6-GHz low-noise amplifier (LNA) employing a common-gate stage for wideband input matching is presented in this paper. Designed in a commercial 0.18-/spl mu/m 1.8-V standard RFCMOS technology, the proposed UWB LNA achieves fully on-chip circuit implementation, contributing to the realization of a single-chip CMOS UWB receiver. The proposed UWB LNA achieves 16.7/spl plusmn/0.8 dB power gain with a good input match (S11<-9 dB) over the 7500-MHz bandwidth (from 3.1 GHz to 10.6 GHz), and an average noise figure of 4.0 dB, while drawing 18.4-mA dc biasing current from the 1.8-V power supply. A gain control mechanism is also introduced for the first time in the proposed design by varying the biasing current of the gain stage without influencing the other figures of merit of the circuit so as to accommodate the UWB LNA in various UWB wireless transmission systems with different link budgets.     

SiGe bipolar transceiver circuits operating at 60 GHz

A low-noise amplifier, direct-conversion quadrature mixer, power amplifier, and voltage-controlled oscillators have been implemented in a 0.12-/spl mu/m, 200-GHz f/sub T/290-GHz f/sub MAX/ SiGe bipolar technology for operation at 60 GHz. At 61.5 GHz, the two-stage LNA achieves 4.5-dB NF, 15-dB gain, consuming 6 mA from 1.8 V. This is the first known demonstration of a silicon LNA at V-band. The downconverter consists of a preamplifier, I/Q double-balanced mixers, a frequency tripler, and a quadrature generator, and is again the first known demonstration of silicon active mixers at V-band. At 60 GHz, the downconverter gain is 18.6 dB and the NF is 13.3 dB, and the circuit consumes 55 mA from 2.7 V, while the output buffers consume an additional 52 mA. The balanced class-AB PA provides 10.8-dB gain, +11.2-dBm 1-dB compression point, 4.3% maximum PAE, and 16-dBm saturated output power. Finally, fully differential Colpitts VCOs have been implemented at 22 and 67 GHz. The 67-GHz VCO has a phase noise better than -98 dBc/Hz at 1-MHz offset, and provides a 3.1% tuning range for 8-mA current consumption from a 3-V supply.     

A 24-GHz CMOS front-end

This paper reports the first 24-GHz CMOS front-end in a 0.18-/spl mu/m process. It consists of a low-noise amplifier (LNA) and a mixer and downconverts an RF input at 24 GHz to an IF of 5 GHz. It has a power gain of 27.5 dB and an overall noise figure of 7.7 dB with an input return loss, S/sub 11/ of -21 dB consuming 20 mA from a 1.5-V supply. The LNA achieves a power gain of 15 dB and a noise figure of 6 dB on 16 mA of dc current. The LNA's input stage utilizes a common-gate with resistive feedthrough topology. The performance analysis of this topology predicts the experimental results with good accuracy.     

2.4 GHz、增益可控的CMOS低噪声放大器

介绍了一种基于 0 35 μmCMOS工艺、2 4GHz增益可控的低噪声放大器。从噪声优化、阻抗匹配及增益的角度详细分析了电路的设计方法 ,讨论了寄生效应对低噪声放大器性能的影响。仿真结果表明在考虑了高频寄生参数的情况下 ,低噪声放大器依然具有良好的性能指标 :在 2 4GHz工作频率下 ,3dB带宽为 6 6 0MHz,噪声系数NF为 1 5 8dB ,增益S2 1为 14dB ,匹配参数S11约为 - 13 2dB。     

220-GHz metamorphic HEMT amplifier MMICs for high-resolution imaging applications

In this paper, the development of 220-GHz low-noise amplifier (LNA) MMICs for use in high-resolution active and passive millimeter-wave imaging systems is presented. The amplifier circuits have been realized using a well-proven 0.1-/spl mu/m gate length and an advanced 0.05-/spl mu/m gate length InAlAs/InGaAs based depletion-type metamorphic high electron mobility transistor technology. Furthermore, coplanar circuit topology in combination with cascode transistors was applied, leading to a compact chip size and an excellent gain performance at high millimeter-wave frequencies. A realized single-stage 0.05-/spl mu/m cascode LNA exhibited a small-signal gain of 10 dB at 222 GHz, while a 0.1-/spl mu/m four-stage amplifier circuit achieved a linear gain of 20 dB at the frequency of operation and more than 10 dB over the bandwidth from 180 to 225 GHz.     

A cavity-backed rectangular aperture antenna with application to a tilted fan beam array antenna

A rectangular aperture of A/sub x//spl times/A/sub y/, cut in the top conducting plate of a triplate transmission line and backed by a cavity, radiates a tilted beam off the direction normal to the aperture. The mechanism of the radiation is explained using the Poynting vector distribution above the aperture and the phase distribution of the electric field over the aperture. The tilt angle is calculated as a function of side length A/sub x/ for a representative value of A/sub y/=18 mm=0.747/spl lambda//sub 12.45/, where /spl lambda//sub 12.45/ is the wavelength at a test frequency of 12.45 GHz. A tilted beam of approximately 27/spl deg/ is realized at A/sub x//A/sub y/=8/9 with a gain of approximately 8 dB. Using this value of A/sub x//A/sub y/, an array antenna composed of rectangular cavity-backed aperture elements is investigated. The array forms a tilted fan beam without phase shifters. The frequency responses of the gain and input impedance are discussed.     

Low-power W-band CPWG InAs/AlSb HEMT low-noise amplifier

We present the development of a low-power W-band low-noise amplifier (LNA) designed in a 200-nm InAs/AlSb high electron mobility transistor (HEMT) technology fabricated on a 50-/spl mu/m GaAs substrate. A single-stage coplanar waveguide with ground (CPWG) LNA is described. The LNA exhibits a noise figure of 2.5 dB and an associated gain of 5.6 dB at 90 GHz while consuming 2.0 mW of total dc power. This is, to the best of our knowledge, the lowest reported noise figure for an InAs/AlSb HEMT LNA at 90 GHz. Biased for maximum gain, the single-stage amplifier presents 6.7-dB gain and an output 1-dB gain compression point (P1dB) of -6.7dBm at 90 GHz. The amplifier provides broad-band gain, greater than 5dB over the entire W-band.     

Post-linearization of cascode CMOS low noise amplifier using folded PMOS IMD sinker

A post-linearization technique for the cascode complementary metal oxide semiconductor (CMOS) low noise amplifier (LNA) is presented. The proposed method uses an additional folded cascode positive-channel metal oxide semiconductor field-effect transistor for sinking the third-order intermodulation distortion (IMD3) current generated by the common source stage, while minimizing the degradation of gain and noise figure. This technique is applied to enhance the linearity of CMOS LNA using 0.18-/spl mu/m technology. The LNA achieved +13.3-dBm IIP3 with 12.8-dB gain, 1.4dB NF at 2GHz consuming 8mA from a 1.8-V supply.     

Prediction of Wide-Band Power Performance of MESFET Distributed Amplifiers Using the Volterra Series Representation

The power performance of a four-section MESFET distributed amplifier is predicted over the frequency range 2-8 GHz. The nonlinear model of the MESFET used has three nonlinear elements: g/sub d/, and C/sub gs/, which are represented by power series up to the third order. The analysis employs the Volterra series representation up to the third order. Experimental verification is first made on a 0.5x400-µm medium-power MESFET device to confirm the validity of the nonlinear model used in the analysis. The agreement between predicted and measured output power at 1-dB gain compression is within +-0.5 dBm across the 2-16 GHz band. A four-section distributed amplifier was then built with four 0.5x400-µm MESFET's. The agreement between predicted and measured output power at 1-dB gain compression of this amplifier is within +-0.7 dBm across the 2-8-GHz band. The measured output power at 1-dB gain compression is (22+-1) dBm across the 2-8-GHz band.     

Two-stage broadband high-gain W-band amplifier using 0.1-/spl mu/m metamorphic HEMT technology

We report broadband high-gain W-band monolithic microwave integrated circuit amplifiers based on 0.1-/spl mu/m InGaAs-InAlAs-GaAs metamorphic high electron mobility transistor (MHEMT) technology. The amplifiers show excellent S/sub 21/ gains greater than 10 dB in a very broad W-band frequency range of 75-100 GHz, thereby exhibiting a S/sub 21/ gain of 10.1 dB, a S/sub 11/ of -5.1 dB and a S/sub 22/ of -5.2 dB at 100 GHz, respectively. The high gain of the amplifier is mainly attributed to the performance of the MHEMTs exhibiting a maximum transconductance of 691 mS/mm, a current gain cutoff frequency of 189 GHz, and a maximum oscillation frequency of 334 GHz.     

增益可调宽带CMOS低噪声放大器设计

设计了一种应用于超宽带系统中的可变增益宽带低噪声放大器。电路中采用了二阶巴特沃斯滤波器作为输入和输出匹配电路;采用了两级共源共栅结构实现电路的放大,并通过控制第二级的电流,实现了在宽频带范围内增益连续可调;采用了多栅管(MGTR),提高了电路的线性度;设计基于SMIC 0.18μm CMOS工艺。仿真结果显示,在频带3~5 GHz的范围内最高增益17 dB,增益波动小于1.8 dB,输入和输出端口反射系数分别小于-10 dB和-14 dB,噪声系数nf小于3.5 dB,当控制电压Vctrl=1.4 V时,IIP3约为2 dBm,电路功耗为16 mW。     

A 5.7-GHz 0.18-/spl mu/m CMOS gain-controlled differential LNA with current reuse for WLAN receiver

This letter presents a 5.7 GHz 0.18 /spl mu/m CMOS gain-controlled differential LNA for an IEEE 802.11a WLAN application. The differential LNA, fabricated with the 0.18 /spl mu/m 1P6M standard CMOS process, uses a current-reuse technology to increase linear gain and save power consumption. The circuit measurement is performed using an FR-4 PCB test fixture. The LNA exhibits a noise figure of 3.7 dB, linear gain of 12.5 dB, P/sub 1dB/ of -11 dBm, and gain tuning range of 6.9 dB. The power consumption is 14.4 mW at V/sub DD/=1.8 V.     

An ultra-wideband CMOS low noise amplifier for 3-5-GHz UWB system

An ultra-wideband (UWB) CMOS low noise amplifier (LNA) topology that combines a narrowband LNA with a resistive shunt-feedback is proposed. The resistive shunt-feedback provides wideband input matching with small noise figure (NF) degradation by reducing the Q-factor of the narrowband LNA input and flattens the passband gain. The proposed UWB amplifier is implemented in 0.18-/spl mu/m CMOS technology for a 3.1-5-GHz UWB system. Measurements show a -3-dB gain bandwidth of 2-4.6GHz, a minimum NF of 2.3 dB, a power gain of 9.8 dB, better than -9 dB of input matching, and an input IP3 of -7dBm, while consuming only 12.6 mW of power.     

A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless LAN in 0.18-/spl mu/m CMOS

A low-noise amplifier (LNA) uses low-loss monolithic transformer feedback to neutralize the gate-drain overlap capacitance of a field-effect transistor (FET). A differential implementation in 0.18-/spl mu/m CMOS technology, designed for 5-GHz wireless local-area networks (LANs), achieves a measured power gain of 14.2 dB, noise figure (NF, 50 /spl Omega/) of 0.9 dB, and third-order input intercept point (IIP3) of +0.9 dBm at 5.75 GHz, while consuming 16 mW from a 1-V supply. The feedback design is benchmarked to a 5.75-GHz cascode LNA fabricated in the same technology that realizes 14.1-dB gain, 1.8-dB NF, and IIP3 of +4.2 dBm, while dissipating 21.6 mW at 1.8 V.