Low-power CMOS distributed amplifier using new cascade gain cell for high and low gain modes

A CMOS distributed amplifier (DA) with low-power and flat and high power gain (S₂₁) is presented. In order to decrease noise figure (NF) an RL terminating network used for the gate transmission line instead of single resistance. Besides, a flat and high S₂₁ is achieved by using the proposed cascade gain cell consist of a cascode-stage with bandwidth extension capacitor. In the high-gain mode, under operation condition of V _dd  = 1.2 V and the overall current consumption of 7.8 mA, simulation result shown that the DA consumed 9.4 mW and achieved a flat and high S₂₁ of 20.5 ± 0.5 dB with an average NF of 6.5 dB over the 11 GHz band of interest, one of the best reported flat gain performances for a CMOS UWB DA. In the low-gain mode, the DA achieved average S₂₁ of 15.5 ± 0.25 dB and an average NF of 6.6 dB with low power consumption (P_DC) of 3.6 mW, the lowest P_DC ever reported for a CMOS DA or LNA with an average gain better than 10 dB.     

增益可调宽带CMOS低噪声放大器设计

设计了一种应用于超宽带系统中的可变增益宽带低噪声放大器。电路中采用了二阶巴特沃斯滤波器作为输入和输出匹配电路;采用了两级共源共栅结构实现电路的放大,并通过控制第二级的电流,实现了在宽频带范围内增益连续可调;采用了多栅管(MGTR),提高了电路的线性度;设计基于SMIC 0.18μm CMOS工艺。仿真结果显示,在频带3~5 GHz的范围内最高增益17 dB,增益波动小于1.8 dB,输入和输出端口反射系数分别小于-10 dB和-14 dB,噪声系数nf小于3.5 dB,当控制电压Vctrl=1.4 V时,IIP3约为2 dBm,电路功耗为16 mW。     

A CMOS variable gain LNA for UWB receivers

A CMOS variable gain low noise amplifier(LNA) is presented for 4.2-4.8 GHz ultra-wideband application in accordance with Chinese standard.The design method for the wideband input matching is presented and the low noise performance of the LNA is illustrated.A three-bit digital programmable gain control circuit is exploited to achieve variable gain.The design was implemented in 0.13-μm RF CMOS process,and the die occupies an area of 0.9 mm~2 with ESD pads.Totally the circuit draws 18 mA DC current from 1.2 V DC supply,the LNA exhibits minimum noise figure of 2.3 dB,S(1,1) less than -9 dB and S(2,2) less than -10 dB.The maximum and the minimum power gains are 28.5 dB and 16 dB respectively.The tuning step of the gain is about 4 dB with four steps in all.Also the input 1 dB compression point is -10 dBm and input third order intercept point(IIP3) is -2 dBm.     

一种用于超宽带接收机的CMOS可变增益低噪声放大器

本文介绍一种符合中国超宽带应用标准的工作频率范围为4.2-4.8 GHz的CMOS可变增益低噪声放大器(LNA)。文章主要描述了LNA宽带输入匹配的设计方法和低噪声性能的实现方式,提出一种3位可编程增益控制电路实现可变增益控制。该设计采用0.13-μm RF CMOS工艺流片,带有ESD引脚的芯片总面积为0.9平方毫米。使用1.2 V直流供电,芯片共消耗18 mA电流。测试结果表明,LNA最小噪声系数为2.3 dB,S(1,1)小于-9 dB,S(2,2)小于-10 dB。最大和最小功率增益分别为28.5 dB和16 dB,共设有4档可变增益,每档幅度为4 dB。同时,输入1 dB压缩点是-10 dBm,输入三阶交调为-2 dBm。     

Low-voltage CMOS programmable gain amplifier for UHF applications

A CMOS programmable gain amplifier suitable for low-voltage operation over the very high frequency range is presented. The scheme is based on a very simple common-mode feedforward pseudo-differential pair with resistive loads. Post-layout results for a 1.8 V-0.18 mum CMOS design show a linear-in-dB programmable gain from 0 to 12 dB with a -3 dB bandwidth above 1.4 GHz and power consumption below 17 mW over all the gain range.     

Low-power digitally-controlled variable gain attenuator and LNA with high gain dynamic range for sub-GHz ISM bands

A low-power Digitally-controlled Variable Gain Attenuator and Low Noise Amplifier are implemented in a 40-GHz f_T 0.25-??m BiCMOS process. They cover the sub-GHz ISM bands for automotive applications such as Remote Keyless Entry. The LNA achieves wideband input matching independent of the variable gain, as well as high reverse isolation, thanks to a partial feedback technique. Its variable gain is based on a resistor-chain gain-control technique, leading to fine gain steps and constant output impedance. This LNA is designed with 15 gain steps of 1?dB. The simulated results for the maximum gain show a Transducer Power Gain of 16.5?dB, a Noise Figure of 2.4?dB and respective input and output IP₃ of ?12.1 and +4.5?dBm, while only drawing 1.45?mA from a 2.7?V power supply. The measurement results are slightly degraded because of wire-bonding couplings in the package. This LNA is preceded by a five coarse steps (about 11?dB each) digitally-programmable attenuator based on a hybrid T and R-2R network. Together with the LNA, more than 50?dB of gain dynamic range is achieved. For high attenuation steps, input IP₃ of more than +18?dBm is reached.     

一种带有混合平均式分布采样电路的低功耗CMOS全折叠型模数转换器

This paper describes an 8-bit 125 MHz low-power CMOS fully-folding analog-to-digital converter （ADC） A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5μm CMOS technology and occupies a die area of 2 × 1.5 mm^2. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply.     

Low-power CMOS fully-folding ADC with a mixed-averaging distributed T/H circuit

This paper describes an 8-bit 125 Mhzlow-powerCMOS fully-foldinganalog-to-digital converter(ADC).A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5μm CMOS technology and occupies a die area of 2 × 1.5 mm~2. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply.     

基于模拟总线接收端的CMOS增益可编程LNA

面向模拟总线接收器应用,设计实现了一款CMOS增益可编程低噪声放大器(LNA)。内置高/中/低增益3个信号放大通路,以满足不同信号幅度情况下的模拟总线接收时的噪声、线性度与输入阻抗等性能需求。提出电容补偿漏电流方法提高高增益信号通路放大器的输入阻抗,同时采用带宽拓展负载方法降低信号相移,解决放大器相移造成电流补偿能力降低的问题。中/低增益信号通路放大器采用差分多门控晶体管(DMGTR)和负反馈技术提高放大器线性度。放大器基于0.18 μm CMOS工艺设计,在1~33 MHz频段,增益范围为-14.3~25 dB,输入阻抗大于2.4 kΩ,输入三阶交调点(IIP3)为-1.6 dBm(最大为20.7 dBm),在25 dB增益下等效输入噪声为1.79 nV·Hz-1/2@1 MHz-0.87 nV·Hz-1/2@33 MHz,1.8 V电源电压下工作电流为6.5 mA。     

Low-power CMOS current conveyor

A novel second-generation CMOS current conveyor based on a new adaptive biasing technique is proposed. It is shown that the use of this circuit offers an excellent performance and leads to a significant reduction in the standby power dissipation. PSPICE simulation results, assuming 0.5 μm CMOS process, are also given     

Low-power CMOS digital design

Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption     

可编程信号处理器的低功耗设计

可编程信号处理器已获得广泛应用，随着VLSI技术的发展，现在已可利用信号处理器实现SOC功能，实现SOC功能还必须降低处理器的功耗。本文首先叙述可编程信号处理器降低功耗的各种途径，然后介绍低功耗可编程处理器的结构设计，最后对最新的TMS320C55X的低功耗性能进行分析。     

Low-power CMOS threshold-logic gate

A new implementation of a threshold gate based on a latch-type comparator that does not consume static power is presented. Simulation results indicate high operation speed and low power consumption, which make it very attractive when used as a basic building block in digital design     

Low-power CMOS continuous-time filters

A design technique for low-power continuous-time filters using digital CMOS technology is presented. The basic building block is a fully-balanced integrator with its unity-gain frequency determined by a small-signal transconductance and MOSFET gate capacitance. Integrator excess phase shift is reduced using balanced signal paths, and open-loop gain is increased using low-voltage cascode amplifiers. Two-pole bandpass and five-pole lowpass ladder filters have been implemented in a 1.2 μm n-well CMOS process. The lowpass prototypes provided 300 kHz-1000 kHz bias-current-tunable -3 dB bandwidth, 67 dB dynamic range with 1% total harmonic distortion (THD), and 30 μW/pole (300 kHz bandwidth) power dissipation with a 1.5 V supply; the bandpass prototypes had a tunable center frequency of 300 kHz-1000 kHz, Q of 8.5, and power dissipation of 75 μW/pole (525 kHz center frequency) from a 1.5 V supply. The active filter area was 0.1 mm²/pole for both designs     

A 110-MHz 84-dB CMOS programmable gain amplifier with integrated RSSI function

This paper describes a CMOS programmable gain amplifier (PGA) that maintains a 3-dB bandwidth greater than 110 MHz and can provide an 84-dB gain control range with 1-dB step resolution. The PGA can also be operated in a low-power mode with 3-dB bandwidth greater than 71 MHz. Integrated with this PGA is a CMOS successive logarithmic detecting amplifier with a /spl plusmn/0.7-dB logarithmic accuracy over an 80-dB dynamic range. It achieves -83-dBm sensitivity and consumes 13 mA from a single 3-V supply in the normal power mode. The chip area, including pads, occupies 1.5/spl times/1.5 mm/sup 2/.     

一种可切换的双频段CMOS低噪声放大器

基于0.18μm RF CMOS工艺,设计了一种可切换的双频段CMOS低噪声放大器,其输入输出均匹配到50Ω。加入封装、ESD电路和PAD模型,采用Cadence Spectre RF进行仿真。结果显示,在1.8 V工作电压下,1.575 GHz输入时,LNA的噪声系数、功率增益和偏置电流分别为0.9 dB、18.2 dB和5.7 mA;1.2 GHz输入时,LNA的噪声系数、功率增益和偏置电流分别为0.8dB、16.8 dB和5.3 mA。     

一个基于65 nm CMOS工艺具有17.3 dB增益的47-67 GHz宽带低噪声放大器

报道了一个基于65 nm CMOS工艺具有17.3 dB增益的47-67 GHz宽带低噪声放大器（LNA）。文中首先阐述了毫米波电路的特征,并讨论了其设计方法。LNA的宽带输入匹配通过源极电感退化获得,这种结构在低GHz频段为窄带匹配,但由于栅漏电容Cgd的存在,在毫米波频段其进化为宽带匹配。为了使噪声系数（NF）最小化,LNA在第一级使用了共源（CS）结构而不是cascode结构,同时文中也探讨了噪声匹配的原理。LNA的后两级使用cascode结构以提高功率增益。对共栅（CG）晶体管中栅极电感的增益提升效应进行了分析。级间T形匹配网络用来提升电路带宽。所有片上电感和传输线都在3维电磁仿真工具中建模和仿真以确保成功的设计。测试结果显示LNA在60 GHz处取得最高的 17.3 dB增益,同时3-dB带宽为20 GHz（47-67 GHz）,涵盖所需要的59-64 GHz频段,并在62 GHz取得最低的4.9 dB噪声系数。整个LNA从1.2 V电源处吸收19 mA电流,芯片包括焊盘占用面积为900×550 μm2。     

利用Cadence设计COMS低噪声放大器

结合一个2.4 GHz CMOS低噪声放大器(LNA)电路,介绍如何利用Cadence软件系列中的IC 5.1.41完成CMOS低噪声放大器设计.首先给出CMOS低噪声放大器设计的电路参数计算方法,然后结合计算结果,利用Cadence软件进行电路的原理图仿真,并完成了电路版图设计以及后仿真.仿真结果表明,电路的输入/输出均得到较好的匹配.由于寄生参数,使得电路的噪声性能有约3 dB的降低.对利用Cadence软件完成CMOS射频集成电路设计,特别是低噪声放大器设计有较好的参考价值.     

CMOS 射频低噪声放大器的设计

讨论了CMOS射频低噪声放大器的相关设计问题,对影响其增益、噪声系数、线性度等性能指标的因素进行了分析,并综述了几种提高其综合性能指标的方法。在此基础上,采用SMIC0．25μm CMOS工艺库,给出了3．8GHz CMOSLNA的设计方案。HSPICE仿真结果表明：电路的功率增益为13．48dB,输入、输出匹配良好,噪声系数为2．9dB,功耗为46．41mw。