大亚湾中微子实验波形数据获取软件设计

介绍了大亚湾中微子实验波形数据读出和数据压缩算法的数据获取软件设计。该软件是以大亚湾中微子实验数据获取系统为基础,在不影响现有电子学系统正常取数的前提下,针对一号实验厅新增的一套前端电子学系统实现波形数据的网络读出、检查、组装、压缩和存盘等功能的软件系统。文中详细说明了波形数据的读出流程以及不同数据压缩方法的实现,并给出了软件的长期稳定性测试结果。     

瞬发γ射线谱数据在线采集系统研制

介绍了爆炸物监测数据在线采集系统的研制情况。设计了NIM标准的前端电子学系统,使用基于PCI总线标准的高速数据采集卡,通过编写控制程序实现了多路与γ信号的相关谱测量。并介绍了几种典型的应用。     

A Prototype of the Read-out Subsystem of the BESIII DAQ Based on PowerPC

1 Overview of the data acquisi-tion system for BES IIIAfter having run successfully for more than tenyears, the BEPC e+ e- collider will be upgradedfor higher luminosity, which will be increased to1033 cm-2 ·sec-1 [1]. Therefore, its detector BESII willbe upgraded to BESIII in order to take advantage ofthis increased luminosity, named BESIII.Trigger rate and event size define the performance re-quirements for the data acquisition (DAQ) system. Forpeak luminosity, we expect a L1 t…     

应用于气体电子倍增器的电子学板研制

气体电子倍增器（GEM）电子学板（GEB）在大面积GEM探测器系统中起重要作用。为满足大面积GEM探测器系统中高速电子学信号的传输、实现电磁屏蔽及为前端电子学提供电源等需求,本文设计了8层结构的GEB,并对该GEB原型进行了电气性能、机械兼容性、信号传输和噪声测试。测试结果显示,本文所设计的GEB在320 Mb/s信号传输速度下的误码率小于10^-13,在保证信号高速性和完整性的基础上能成功传输前端电子学信号;通过采用叠层对称式设计克服了大面积GEB生产时弯曲程度高的困难,生产的GEB原型弯曲高度降低了2/3,平均弯曲高度为1 mm,增强了前端电子学在探测器系统中的运行稳定性。     

Electronics for the CMS Muon Drift Tube Chambers: The Read-Out Minicrate

On the Compact Muon Solenoid (CMS) experiment for large hadron collider (LHC) at CERN laboratory, the drift tube chambers are responsible for muon detection and precise momentum measurement. In this paper the first level of the read out electronics for these drift tube chambers is described. These drift tube chambers will be located inside the muon barrel detector in the so-called minicrates (MCs), attached to the chambers. The read out boards (ROBs) are the main component of this first level data acquisition system, and they are responsible for the time digitalization related to Level 1 Accept (L1A) trigger of the incoming signals from the front-end electronics, followed by a consequent data merging to the next stages of the data acquisition system. ROBs' architecture and functionality have been exhaustively tested, as well as their capability of operation beyond the expected environmental conditions inside the CMS detector. Due to the satisfactory results obtained, final production of ROBs and their assembly in the MCs has already started. A total amount of 250 MCs and approximately 1500 ROBs are being produced and tested thoroughly at CIEMAT (Spain). One set of tests, the burn-in tests, will guarantee ten years of limited maintenance operation. An overview of the system and a summary of the different results of the tests performed on ROBs and MCs will be presented. They include acceptance tests for the production chain as well as several validation tests that insure proper operation of the ROBs beyond the CMS detector conditions.     

大面积GEM中子探测器高计数率读出电子学系统研制

研制并测试了GEM中子探测器的512通道高计数读出电子学系统,以满足中国散裂中子源高效率、高分辨、高通量二维位置灵敏中子探测器的需求。系统以Kintex-7 FPGA作为系统控制和数据分析的核心,使用8块AS20Board前端芯片对灵敏面积为200 mm×200 mm的探测器的两个维度的信号进行读出,读出通道为256×256。读出数据经FPGA分析后通过千兆以太网传输至计算机显示。计算机可通过千兆以太网发送配置指令对前端采样电路和FPGA算法进行配置。系统与探测器组装后在中子束流实验中测得系统最高瞬时计数率为（1.2±0.1）×106 s^-1,系统运行稳定,受噪声干扰小。     

PandaX-nT暗物质探测实验读出电子学预研系统的研制

PandaX-nT升级对电子学系统提出了诸多新的挑战,如更多的通道数、高速高精度的波形数字化、灵活的触发算法和更高的数据带宽要求等。本文介绍一种为未来PandaX-nT暗物质直接探测升级实验预研的读出电子学系统。该电子学系统主要由前置放大电路模块、波形数字化模块（FDM）、数据获取模块（DAQ）和时钟分发模块等组成。FDM集成8路14 bit@ 1 GS/s ADC,具有较高集成度,可实现对探测器信号波形数字化,并通过光纤与DAQ通信。DAQ可汇总多块FDM数据,实现全数字化的触发算法,并通过基于TCP协议的千兆以太网与计算机通信,保证了数据传输的可靠与稳定。目前已完成了整个读出电子学系统设计,并对整个电子学系统进行了功能验证,以及与探测器进行了初步的联合测试。整个电子学系统具有较高的可扩展性,并能实现更复杂的触发算法,能满足下一代升级的需求。     

Chooz 中微子探测器电子学系统的设计

介绍了Ｃｈｏｏｚ中微子探测器中的电子学系系统,简述ＥＭＩ９３５６ＫＢＡ Ｂ５３型光电倍增管的性能和组成该电子学系统的信号扇入／扇出、信号多级触发、时间数字转换、波形数字化以及数据获取等各系统的设计原理。     

Upgrade of the TRIUMF on-line isotope separator, TISOL

The operational TISOL thick target, on-line isotope separator at the TRIUMF, 500 MeV proton cyclotron facility has been upgraded to be a production facility with an active experimental program. A new experimental area is now available and modifications are under design to handle remotely the expected radioactively “hot” targets. Two ion source systems are now available, a heated surface of normal design and a new ECR (electron cyclotron resonance) source resulting in ion beams from a wide range of elements. Details of the new upgraded facility will be presented along with its experimental program and plans for the future. The status of the previously proposed accelerated radioactive beams facility, ISAC, for which TISOL is a prototype front-end system, will also be mentioned.     

The data-acquisition system for the CMS tracker beam tests

This paper describes the conception and the development of a real-time data-acquisition system for prototype detectors of the Tracker being designed for the compact muon solenoid (CMS) experiment at the Large Hadron Collider of CERN, European Laboratory for Particle Physics, Geneva, Switzerland. The rationale for the development of a dedicated data-acquisition system was the need to perform two fundamental beam tests (the “Milestone Barrel 1” and “Milestone Forward 1”), with large-scale prototypes of the detectors planned as the baseline design. The number of readout channels, the complexity of the readout electronics, and the stringent requirements of the milestone tests mandated that a thorough understanding of the issues related to the physics of the detectors themselves be coupled with the application of leading-edge electronic and software engineering technologies. The implementation described in this paper is based on a distributed architecture. An event builder CPU handles the two main tasks of synchronizing a variable number of front-end processors and formatting the data in preparation for the transfer to a dedicated high-performance storage system, while the front-end processors handle the hardware and the real-time readout. Additional workstations are used to decouple the actual task of transferring the data files and monitoring the detector performance on-line from the readout farm. The system has been successfully operated during the two aforementioned Milestone tests, allowing the CMS Tracker collaboration to pass them, with the simultaneous readout of up to 40000 detector channels. The results of the two Milestones have led to the compilation of the “Tracker Technical Design Report”. Subsequently, the same readout system has been used for a number of other beam tests, and it has formed the basis for the development of further, more advanced data-acquisition systems for the new readout electronic of the CMS Tracker     

硅多条阵列探测器多路电荷灵敏前置放大器研制

本文简要介绍了应用于阵列探测器特别是硅多条阵列探测器的高密度多路前置放大器和前端电子学的发展现状、工作原理、设计要求和设计思路.同时,介绍了一套新开发的用于硅多条探测器中的48路电荷灵敏前置放大器的电路设计和实际测量结果,它具有低成本、高密度、好于1%的能量分辨和良好的长期稳定性.     

The trigger system of the first CMS tracker beam tests

The trigger for the first compact muon solenoid (CMS) tracking beam tests is a dedicated system for analog multiplexed front-end electronics. With this first generation of electronics dedicated to CMS tracker detectors, some new specific development was necessary to read it with a multicrate distributed data acquisition (DAQ) system. The goal of this development was to reach a high scalability of experiment subsystems and a good robustness for test beams. Each subsystem had to be independent from the others, both from the hardware and software point of view. Remote control software for this system as well as further monitoring facilities were the required functions of the trigger system     

基于APV25芯片的GEM探测器读出电子学系统的测试与改进

气体电子倍增器(GEM)是目前最具发展前景的位置灵敏气体探测器。其新一代读出电子学系统包括APV25前端卡、多用途数字转换器（MPD)、VME控制器及基于Linux的采集软件DAQ。本工作完成了读出系统的调试,获得了系统在40 MHz和20 MHz工作频率下的理想数据。在长时间测试中,系统运行稳定。通过对软件配置的优化和对硬件的改进,降低了噪声水平,提高了信噪比。     

Modular software for MAST multi-technology data acquisition system

The MAST (Mega-Amp Spherical Tokamak) data acquisition system is being radically upgraded. New hardware with completely different control interface and logic has been installed on all system levels from front-end devices to plant control. MAST plant control has been moved from VMS to a Windows-based OPC system. Old CAMAC and VME units are being replaced by cPCI and PXI units. A number of CAMAC crates have been upgraded with new Ethernet controllers supporting useful front-end devices.The upgrade is being performed without disturbing operations; the data acquisition units are being replaced gradually. Such an upgrade is possible due to the structure of the MAST data acquisition system which is build as a set of autonomous units, each one controlled by a computer. Modern computers are capable of controlling several units, and this has been the major opportunity and challenge because it radically changes the unit control logic. As a result practically all system components had to be redesigned.The new unit software is a step in system evolution towards greater flexibility and universality. Each unit can now manage multiple data files, possibly with different formats, and many units can be hosted on the same computer. This feature is provided by a message proxy server. Each unit is controlled independently and transparently, exactly like a stand-alone unit. A message interface has been modified for consistent handling of new functions. The unit software supports event-triggered and real-time data acquisition at the system level. New software has been developed for a number of new hardware devices, and the device modules for all usable old devices have been rewritten to operate with the new control interface.The new software allows units to be upgraded even during operations. The system structure and logic provide easy extension. The system as a whole or system design elements could also be used on other fusion facilities.     

基于APV25读出电子学系统的GEM探测器的位置分辨与X射线成像研究

采用3层GEM膜制作了有效面积为10 cm×10 cm的GEM探测器,该探测器采用二维条读出方式,条间距为400 μm,每个维度有256个读出通道。探测器的读出采用APV25读出电子学系统,根据GEM探测器的需要,设计并改进了电子学系统使用的背板连接器。实验测得GEM探测器空间分辨为76 μm。进行了X射线二维成像研究,获得了清晰的二维图像,探测器与电子学运行稳定可靠。     

Digital Architecture and Interface of the New ATLAS Pixel Front-End IC for Upgraded LHC Luminosity

A new pixel front-end integrated circuit is being developed in a 130 nm technology for use in the foreseen b-layer upgrade of the ATLAS pixel detector. Development of this chip is considered as an intermediate step towards super-LHC upgrade, and also allows having a smaller radius insertable pixel layer. The higher luminosity for which this chip is tuned implies a complete redefinition of the digital architecture logic with respect to the current ATLAS pixel front-end. The new digital architecture logic is not based on a transfer of all pixel hits to the periphery of the chip, but on local pixel logic, local pixel data storage, and a new mechanism to drain triggered hits from the double-column. An overview of the new chip will be given with particular emphasis on the new digital logic architecture and possible variations. The new interface needed to configure and operate the chip will also be described.     

ECH system developments including the design of an intelligent fault processor on the DIII-D tokamak

A new generation fault processor is in development which is intended to increase fault handling flexibility and reduce the number of incomplete DIII-D shots due to gyrotron faults. The processor, which is based upon a field programmable gate array device, will analyze signals for aberrant operation and ramp down high voltage to try to avoid hard faults. The processor will then attempt to ramp back up to an attainable operating point. The new generation fault processor will be developed during an expansion of the electron cyclotron heating (ECH) areas that will include the installation of a depressed collector gyrotron and associated equipment. Existing systems will also be upgraded. Testing of real-time control of the ECH launcher poloidal drives by the DIII-D plasma control system will be completed. The ECH control system software will be upgraded for increased scalability and to increase operator productivity. Resources permitting, all systems will receive an extra layer of interlocks for the filament and magnet power supplies, added shielding for the tank electronics, programmable filament boost shape for long pulses, and electronics upgrades for the installation of the advanced fault processor.     

Test Suite for the LHCb Muon Chambers Quality Control

This paper describes the apparatus and the procedures implemented to test the front-end (FE) electronics of the LHCb muon detector multi wire proportional chambers (MWPC). Aim of the test procedure is to diagnose every FE channel of a given chamber by performing an analysis of the noise rate versus threshold and of the performances at the operational thresholds. Measurements of the key noise parameters, obtained while performing quality tests on the MWPC chambers before the installation on the experiment, are presented. The test suite proved to be an automatic, fast and user-friendly system for mass production tests of chambers. It provided the electronic identification of every chamber and FE board, and the storage and bookkeeping of test results that will be made available to the experiment control system during data taking.     

Distributed Low-Voltage System for the Front End of the HADES Timing RPC Wall

The power supply system for the front-end electronics of the HADES resistive plate chamber (RPC) detector, installed at GSI (Darmstadt, Germany), is described. The system has a distributed architecture that includes custom low-voltage boards using isolated DC-DC switching converters. These converters are compact and operate at high efficiency. The converters are fitted with input and output electromagnetic interference filters, resulting in very low output noise. Operational tests of the RPC detector demonstrate that the performance of the detector when powered by this system is comparable to that achieved when powered by laboratory bench supplies, proving its suitability for large-scale applications requiring time resolutions better than 100 ps.