一种高频单片GaN DC-DC降压转换器设计

基于全耗尽型(D-mode) 0.25 μm 硅基氮化镓(GaN-on-Si)工艺,设计了一款高频单片GaN DC-DC降压转换器芯片。该芯片集成了驱动电路和半桥功率级电路,驱动电路中电平放大功能通过有源上拉结构实现,在100~200 MHz频率范围内,单片GaN DC-DC降压转换器可直接被0.7 V的高速脉冲信号控制,无需片外模块,其峰值功率级效率达到92.2%,峰值总效率达到84.24%,峰值功率为7.7 W。相较于前期工作,芯片工作范围从100 MHz提升至200 MHz,在保证芯片效率性能的情况下,实现了对工作频率的大幅提升。     

一种新的应用于降压式DC-DC变换器电流采样电路的设计

在分析了传统的应用于大负载电流降压式DC-DC变换器电流采样电路主要缺点的基础上,提出一种新的应用于降压式DC-DC变换器的电流采样电路。该方法通过一个电阻电容网络来消除电感寄生电阻的影响,并利用开关电容积分器来实现降压式DC-DC变换器的电流采样,在Chartered 0.35μm CMOS工艺下实现该电路并流片验证。最终的测试结果显示,提出的电流采样电路实现了对降压式DC-DC变换器精确的电流采样。     

集成于电流模降压型DC-DC变换器的电流采样电路

针对电流模降压型DC-DC变换器,提出了一种新颖的CMOS片上电流采样电路.该电路结构简单,易于集成,功率损耗小,且通过MOSFET的匹配使采样比例几乎不受温度、模型以及电源电压变化影响.并通过进一步的优化设计,使得响应速度更快,工作电压进一步降低.提出的采样电路在一款基于0.5μm CMOS工艺没计的单片电流模降压型DC-DC变换器中进行了验证.在2.5～5.5V的电压范围,0～2A的负载范围内芯片工作稳定,瞬态响应良好,且效率高达96%.     

集成于电流模降压型DC-DC变换器的电流采样电路

针对电流模降压型DC-DC变换器,提出了一种新颖的CMOS片上电流采样电路.该电路结构简单,易于集成,功率损耗小,且通过MOSFET的匹配使采样比例几乎不受温度、模型以及电源电压变化影响.并通过进一步的优化设计,使得响应速度更快,工作电压进一步降低.提出的采样电路在一款基于0.5μm CMOS工艺没计的单片电流模降压型DC-DC变换器中进行了验证.在2.5～5.5V的电压范围,0～2A的负载范围内芯片工作稳定,瞬态响应良好,且效率高达96%.     

基于滑模控制的DC-DC降压变换器实验平台

为了实现DC-DC降压变换器的高精度控制,设计了一种基于滑模控制的输出电压调节器。首先根据DC-DC降压变换器的工作原理建立了系统的动态模型;接着利用转换后的受扰动态模型设计了滑模控制器,同时基于李雅普诺夫函数证明了闭环系统的稳定性;最后使用Matlab/Simulink软件和DC-DC降压变换器硬件电路搭建了实验测试平台。测试结果表明与传统的PID控制方法相比,DC-DC降压变换器系统在所设计的滑模控制器的作用下可以获得更快的动态性能与更强的扰动抑制能力。该实验平台不仅有利于大学生理解和掌握滑模控制理论,还可以提高大学生的工程应用能力。     

一种宽电压输入范围降压稳压电路的设计

为了解决高压恒流源芯片内部低压模块供电问题,通过集成降压预调整电路、前置基准源和线性稳压器3个模块,设计了一种宽电压输入范围的降压稳压电路.采用0.6μm BCD工艺模型进行仿真验证.结果显示,降压预调整电路低压跟随时压差在50mV内.输入在6～40V范围内变化时,偏置和基准的变化分别为1.13mV和0.3mV幅度.线性稳压器直流下PSRR可达-85dB,在1MHz工作频率下,输入电压为6V和40V时,模拟电源变化幅度分别不超过24mV和46mV,数字电源变化幅度分别不超过0.3V和0.8V.该降压稳压电路已成功应用于高压LED恒流源中.     

基于DC-DC的白光LED驱动电路的研究与设计

LED由于环保、寿命长、低耗电量等特性,近年来在各行业得以快速应用及发展,LED驱动电路的研究与设计也成了关注热点。通过设计升压式DC-DC转换芯片,采用PWM控制方式和电流控制模式,对外接串联的LED进行驱动。然后用Spectre软件完成了总体电路的模拟和仿真,通过对其结果分析,表明系统能够稳定工作,并且达到设计指标要求。     

PWM型降压式DC-DC变换器中分岔与混沌的研究

对连续工作模式下的PWM型Buck变换器进行了研究。通过仿真和实验，证实了DC-DC变换器是一个强非线性系统，随着输入电压Vi的变化，会出现倍周期分岔和混沌现象。     

一种具有快速电压跟随和宽输出电压范围的电压模式DC-DC降压型变换器

A high switching frequency voltage-mode buck converter with fast voltage-tracking speed and wide output voltage range has been proposed. A novel error amplifier （EA） is presented to achieve a high DC gain and get high phase margin, including a resistor and capacitor net, a unit gain block and a high gain block. The investigated converter has been fabricated with GF 0.35 μm CMOS process and can operate at 6 MHz with the output voltage range from 0.6 to 3.4 V. The experimental results show that the voltage-tracking speed can achieve 8.8 μs/V for up-tracking and 6 μs/V for down-tracking. Besides, the recovery time is less than 8 μs while the load current suddenly changes 400 mA.     

一种新型的3kw推挽DC-DC变换器

摘要：针对推挽DC/DC变换器,功率超过1kw时,随输出功率增加,开关管关断时次级漏感引起MOSFET尖峰增加,同时MOSFET开通损耗加大。提出一种双变压器LC串联谐振软开关电路,两个变压器采用初级绕组并联,次级绕组串联,实现LC串联谐振软开关,实现MOSFET在零电压下开通或零电流下关断,从而降低开关管开通与关断漏感引起的尖峰。给出了电路结构图和软开关原理,并分析电路工作过程,根据原理,电路采用两个EE65B高频磁芯变压器,制作48V输入、380V直流输出的3kw的DC/DC LC串联谐振变换器。实验证明,通过对比MOSFET的漏源极电压实验数据,串联谐振电路可以大幅度减小MOSFET开通损耗与关闭时漏感引起的尖峰值。     

Tapped-inductor buck converter for high-step-down DC-DC conversion

The narrow duty cycle in the buck converter limits its application for high-step-down dc-dc conversion. With a simple structure, the tapped-inductor buck converter shows promise for extending the duty cycle. However, the leakage inductance causes a huge turn-off voltage spike across the top switch. Also, the gate drive for the top switch is not simple due to its floating source connection. This paper solves all these problems by modifying the tapped-inductor structure. A simple lossless clamp circuit can effectively clamp the switch turn-off voltage spike and totally recover the leakage energy. Experimental results for 12V-to-1.5V and 48V-to-6V dc-dc conversions show significant improvements in efficiency.     

同步降压式DC-DC转换器的稳定性设计

DC-DC转换器因其相比于传统的线性稳压器具有较高的电源转换效率,而被广泛地应用到各种现代电子设备中。同时随着电源整流技术的不断进步,DC-DC转换器也正在从以肖特基二极管作为续流二极管的异步整流模式向同步整流模式转变。同步整流式DC-DC转换器具有极高的电源转换效率(可超过95%),是各种手持设备电源设计的首选。本文从分析同步降压式DC-DC转换器的闭环增益和相位曲线入手,研究了多种条件下如何实现同步降压式DC-DC转换器的稳定性设计。     

On-chip CMOS current-sensing circuit for DC-DC buck converter

An on-chip CMOS current-sensing circuit for a DC-DC buck converter is presented. The circuit can measure the inductor current through sensing the voltage of the switch node during the converter on-state. By matching the MOSFETs, the achieved sense ratio is almost independent of temperature, model and supply voltage. The proposed circuit is suitable for low power DC-DC applications with high load current.     

A novel winding-coupled buck converter for high-frequency, high-step-down DC-DC conversion

This paper analyzes the fundamental limitations of the buck converter for high-frequency, high-step-down dc-dc conversion. Further modification with additional coupled windings in the buck converter yields a novel topology, which significantly improves the efficiency without compromising the transient response. An integrated magnetic structure is proposed for these windings so that the same magnetic cores used in the buck converter can be used here as well. Furthermore, it is easy to implement a lossless clamp circuit to limit the device voltage stress and to recover inductor leakage energy. This new topology is applied for a 12V-to-1.5V/25A voltage regulator module (VRM) design. At a switching frequency of 2MHz, over 80% full-load efficiency is achieved, which is 8% higher than that of the conventional buck converter.     

DC-DC降压变换器的滑模控制研究

为更快获得比较理想的直流输出电压,优化Buck变换器的动态性能,本文分析了一种滑模控制器控制的直流-直流降压变换器,推导了描述降压变换器的动态方程,并设计了滑模控制器。通过MATLAB/Simulink进行仿真,仿真结果表明,基于滑模控制的降压转换器对负载变化和输入电压变化的有效性和鲁棒性。     

Wireless PWM control of a parallel DC-DC buck converter

We demonstrate a new concept for wireless pulse-width modulation (PWM) control of a parallel dc-dc buck converter. It eliminates the need for multiple physical connections of gating/PWM signals among the distributed converter modules. The new scheme relies on radio-frequency (RF) based communication of the PWM control signals from a master to the slave modules. We analyze the system stability and demonstrate the experimental effectiveness of the wireless control scheme for a two-module parallel buck converter for 10-kHz and 20-kHz switching frequencies and for channel lengths of 1.5 and 15ft, respectively. The proposed control concept may lead to easier distributed control implementation of parallel dc-dc converters and distributed power systems, and may lead to redundancy that is achievable using droop method. It may also be used as a backup for wire-based control of parallel converters to provide fault tolerance.     

Automotive DC-DC bidirectional converter made with many interleaved buck stages

Interleaving technique is used in some applications due to its advantages regarding filter reduction, dynamic response, and power management. In dual battery system vehicles, the bidirectional dc-dc converter takes advantage of this technique using three-to-five paralleled buck stages. In this paper, we propose the use of a much higher number of phases in parallel together with digital control. It will be shown that this approach opens new possibilities since changes in the technology are possible. Thus, two 1000-W prototypes have been designed using surface mount technology devices (SO-8 transistors). An additional important feature is that due to the accuracy of the digital device [field-programmable gate array (FPGA)], current loops have been eliminated, greatly simplifying the implementation of the control stage.     

A buck converter with adaptive on-time PFM control and adjustable output voltage

This letter proposes a new adaptive on-time pulse-frequency modulation (PFM) circuit that operates at a wide range of supply voltage levels and that can generate various output voltage levels compared to conventional circuits. The circuit’s peak inductor current is well-controlled; the magnitude of the output ripple voltage is constant, even when the supply and output voltage levels are significantly different. Since the ripple voltage is a noise component, constant ripple voltage is important for predictable noise of a power management system.     

A high-efficiency DC-DC buck converter for sub-2×VDD power supply

This paper presents a DC-DC step-down converter, which can accommodate the range of power supply voltage from VDD to sub-2×VDD. By utilizing stacked power MOSFETs, a voltage level converter, a detector and a controller, the proposed design is realized by a typical 1P6M CMOS process without using any high voltage process to resolve gate-oxide reliability and leakage current problems. The core area of the proposed design is less than 0.184 mm², while the power supply range is up to 5 V. Since the internal reference voltage is 1.0 V, it can increase the output regulation range. The proposed design attains very high conversion efficiency to prolong the life time of battery-based power supply. Therefore, it can be integrated in a SOC (system-on-chip) to provide multiple supply voltage sources.     

A wide dynamic range continuously adjustable CMOS current mirror

A novel circuit realization of a CMOS current mirror with wide input dynamic range and continuously adjustable gain is presented. The proposed current mirror is linear with respect to signal current in the strong inversion as well as in the subthreshold region of MOSFET operation. The gain is controlled by the same control signal in both regions. The circuit is analyzed using a numerical unified MOSFET model which covers both operating regions. The implemented current mirror is adjustable over more than eight decades of signal current