An 18-ns 1-Mbit CMOS SRAM

A 1-Mb (256 K×4 b) CMOS static random-access memory with a high-resistivity load cell was developed with 0.7-μm CMOS process technology. This SRAM achieved a high-speed access of 18 ns. The SRAM uses a three-phase back-bias generator, a bus level-equalizing circuit and a four-stage sense amplifier. A small 4.8×8.5-μm² cell was realized by the use of a triple-polysilicon structure. The grounded second-polysilicon layer increases cell capacitance and suppresses α-particle-induced soft errors. The chip size measures 7.5×12 mm²     

A 46-ns 1-Mbit CMOS SRAM

A 1-Mb (128 K×8-bit) CMOS static RAM (SRAM) with high-resistivity load cell has been developed with 0.8-μm CMOS process technology. Standby power is 25 μW, active power 80 mW at 1-MHz WRITE operation, and access time 46 ns. The SRAM uses a PMOS bit-line DC load to reduce power dissipation in the WRITE cycle, and has a four-block access mode to reduce the testing time. A small 4.8×8.5-μm² cell has been realized by triple-polysilicon layers. The grounded second polysilicon layer increases cell capacitance and suppresses α-particle-induced soft errors. The chip size is 7.6×12.4 mm²     

A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM

An ultrahigh-speed 4.5-Mb CMOS SRAM with 1.8-ns clock-access time, 1.8-ns cycle time, and 9.84-μm² memory cells has been developed using 0.25-μm CMOS technology. Three key circuit techniques for achieving this high speed are a decoder using source-coupled-logic (SCL) circuits combined with reset circuits, a sense amplifier with nMOS source followers, and a sense-amplifier activation-pulse generator that uses a duplicate memory-cell array. The proposed decoder can reduce the delay time between the address input and the word-line signal of the 4.5-Mb SRAM to 68% of that of an SRAM with conventional circuits. The sense amplifier with nMOS source followers can reduce not only the delay time of the sense amplifier but also the power dissipation. In the SRAM, the sense-amplifier activation pulse must be input into the sense amplifier after the signal from the memory cell is input into the sense amplifier. A large timing margin required between these signals results in a large access time in the conventional SRAM. The sense-amplifier activation pulse generator that uses a duplicate memory-cell array can reduce the required timing margin to less than half of the conventional margin. These three techniques are especially useful for realizing ultrahigh-speed SRAM's, which will be used as on-chip or off-chip cache memories in processor systems     

A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layoutsense amplifiers

A 16-Mb CMOS SRAM using 0.4-μm CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm² is fabricated and an address access time of 12.5 ns has been achieved     

A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current senseamplifiers

A 4-Mb CMOS SRAM with 3.84 μm² TFT load cells is fabricated using 0.25-μm CMOS technology and achieves an address access time of 6 ns at a supply voltage of 2.7 V. The use of a current sense amplifier that is insensitive to its offset voltage enables the fast access time. A boosted cell array architecture allows low voltage operation of fast SRAM's using TFT load cells     

A 9-ns 16-Mb CMOS SRAM with offset-compensated current senseamplifier

A 9-ns 16-Mb CMOS SRAM has been developed using a 0.35-μm CMOS process, The current-mode fully nonequalized data path has been realized in a CMOS SRAM for the first time by using a stabilized feedback current-sense amplifier (SFCA) that provides a small input resistance and an offset compensation effect. To reduce the test time, a bit-line wired-OR parallel test circuit has been implemented     

An experimental 1-Mbit CMOS SRAM with configurable organization andoperation

A 1-Mb SRAM (static random-access memory) configurable as a 128-kb×8, 256-kb×4, or 1-Mb×1 memory featuring asynchronous operation with static-column and chip-enable-access speedup modes or synchronous operation with a fast-page (toggle) or static-column mode is described. It has been fabricated in a double-metal, double-polysilicon CMOS process with 0.7-μm geometry and special SRAM structures. The measured synchronous access of 29 ns with a fast-page mode access of 22 ns. Measured asynchronous access is 34 ns with a static-column access of 33 ns and a chip-select speedup access of 29 ns. The SRAMs six-transistor CMOS memory cell is 58.24 μm²     

A 23-ns 4-Mb CMOS SRAM with 0.2-μA standby current

A 4-Mb CMOS SRAM having 0.2-μA standby current at a supply voltage of 3 V has been developed. Current-mirror/PMOS cross-coupled cascade sense-amplifier circuits have achieved the fast address access time of 23 ns. A new noise-immune data-latch circuit has attained power-reduction characteristics at a low operating cycle time without access delay. A 0.5-μm CMOS, four-level poly, two-level metal technology with a polysilicon PMOS load memory cell, yielded a small cell area of 17 μm² and the very small standby current. A quadruple-array, word-decoder architecture allowed a small chip area of 122 mm²     

A 7.5-ns 32 K×8 CMOS SRAM

A 256 K (32 K×8) CMOS static RAM (SRAM) which achieves an access time of 7.5 ns and 50-mA active current at 50-MHz operation is described. A 32-block architecture is used to achieve high-speed access and low power dissipation. To achieve faster access time, a double-activated-pulse circuit which generates the word-line-enable pulse and the sense-amplifier-enable pulse has been developed. The data-output reset circuit reduces the transition time and the noise generated by the output buffer. A self-aligned contact technology reduces the diffused region capacitance. This RAM has been fabricated in a twin-tub CMOS 0.8-μm technology with double-level polysilicon (the first level is polycide) and double-level metal. The memory cell size is 6.0×11.0 μm² and the chip size is 4.38×9.47 mm ²     

A 16-Mb CMOS SRAM with a 2.3-μm2 single-bit-linememory cell

A novel architecture that enables fast write/read in poly-PMOS load or high-resistance polyload single-bit-line cells is developed. The architecture for write uses alternate twin word activation (ATWA) with bit-line pulsing. A dummy cell is used to obtain a reference voltage for reading. An excellent balance between a normal cell signal line and a dummy cell signal line is attained using balanced common data-line architecture. A newly developed self-bias-control (SBC) sense amplifier provides excellent stability and fast sensing performance for input voltages close to V_CC at a low power supply of 2.5 V. The single-bit-line architecture is incorporated in a 16-Mb SRAM, which was fabricated using 0.25-μm CMOS technology. The proposed single-bit-line architecture reduces the cell area to 2.3-μm² , which is two-thirds of a conventional two-bit-line cell with the same processes. The 16-Mb SRAM, a test chip for a 64-Mb SRAM, shows a 15-ns address access time and a 20-ns cycle time     

A 14-ns 1-Mbit CMOS SRAM with variable bit organization

The authors describe a 14-ns 1-Mb CMOS SRAM (static random-access memory) with both 1M word×1-b and 256 K word×4-b organizations. The desired organization is selected by forcing the state of an external pin. The fast access time is achieved by the use of a shorter divided-word-line (DWL) structure, a highly sensitive sense amplifier, a gate-controlled data-bus driver, and a dual-level precharging technique. The 0.7-μm double-aluminum and triple-polysilicon process technology with trench isolation offers a memory cell size of 41.6 μm² and a chip size of 86.6 mm ². The variable bit-organization function reduces the testing time while keeping the measurement accuracy of the access times     

An ultrahigh-density high-speed loadless four-transistor SRAM macrowith twisted bitline architecture and triple-well shield

We have developed two schemes for improving access speed and reliability of a loadless four-transistor (LL4T) SRAM cell: a dual-layered twisted bitline scheme, which reduces coupling capacitance between adjacent bitlines in order to achieve highspeed READ/WRITE operations, and a triple-well shield, which protects the memory cell from substrate noise and alpha particles. We incorporated these schemes in a high-performance 0.18-μm-generation CMOS technology and fabricated a 16-Mb SRAM macro with a 2.18-μm² memory cell. The macro size of the LL4T-SRAM is 56 mm², which is 30% to 40% smaller than a conventional six-transistor SRAM when compared with the same access speed. The developed macro functions at 500 MHz and has an access time of 2.0 ns. The standby current has been reduced to 25 μA/Mb with a low-leakage nMOSFET in the memory cell     

A 25-ns low-power full-CMOS 1-Mbit (128 K×8) SRAM

A 5-V full-CMOS 1-Mb SRAM (static random-access memory) is described. The access time is 25 ns with 30-pF load, and power dissipation is 75 mW at 10 MHz and less than 1 μW in standby mode. The chip is made in a 0.7-μm twin-tub, single-poly, double-metal technology on p/p⁺ epi substrate. Cascoding of NMOS devices and special timing techniques are used to suppress hot-electron degradation. The authors describe circuit techniques that obtain low active power dissipation and high speed for a byte-wide part     

A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM

An ultrahigh-speed 1-Mb emitter-coupled logic (ECL)-CMOS SRAM with 550-ps clock-access time, 900-MHz operating frequency, and 12-μm² memory cells has been developed using 0.2-μm BiCMOS technology. Three key techniques for achieving the ultrahigh speed are a BiCMOS word decoder/driver with an nMOS level-shift circuit, a sense amplifier with a voltage-clamp circuit, and a BiCMOS write circuit with a variable-impedance bitline load. The proposed word decoder/driver and sense amplifier can reduce the delay times of the circuits to 54% and 53% of those of conventional circuits. The BiCMOS write circuit can reduce the power dissipation of the circuit by 74% without sacrificing writing speed. These techniques are especially useful for realizing ultrahigh-spaced high-density SRAMs, which will be used as cache and control memories in mainframe computers     

A 29-ns 64-Mb DRAM with hierarchical array architecture

A 29-ns (RAS access time), 64-Mb DRAM with hierarchical array architecture has been developed. For consistent high yields and high speed, a CMOS segment driver circuit is used as a hierarchical word line scheme. To achieve high speed, precharge signal (PC) drivers for equalizing the bit lines pairs, and shared sense amplifier signal (SHR) drivers are distributed in the array. To enhance sense amplifiers speed in low array voltage, an over driven sense amplifier is adopted. A hierarchical I/O scheme with semidirect sensing switch is introduced for high speed data transfer in the I/O paths. By combining these proposed circuit techniques and 0.25-μm CMOS process technologies with phase-shift optical lithography, an experimental 64-Mb DRAM has been designed and fabricated. The memory cell size is 0.71×1.20 μm ², and the chip size is 15.91×9.06 mm². A typical access time under 3.3 V power supply voltage is 29 ns     

An 18-Mb, 12.3-GB/s CMOS pipeline-burst cache SRAM with 1.54Gb/s/pin

An 18-Mbit CMOS pipeline-burst cache SRAM achieves a 12.3-Gbyte/s data transfer rate with 1.54-Gbit/s/pin I/O's. The SRAM is fabricated on a 0.18-μm CMOS technology. The 14.3×14.6-mm² SRAM chip uses a 5.59-μm², six-transistor cell. Circuit techniques used for achieving high bandwidth include fully self-timed array architecture, segmented hierarchical sensing with separated global read/write bitlines in different metal layers, a high-speed data-capture technique, a reduced-swing output buffer, and a high-sensitivity, high-bandwidth input buffer     

A 50-MHz 8-Mbit video RAM with a column direction drive senseamplifier

An 8-Mb (1-Mwords×8-b) dynamic RAM which utilizes a column direction drive sense amplifier to obtain low peak current is described. The power supply peak current is about one fourth of that for conventional circuits. The chip operates at 50-MHz and is fabricated with a 0.7-μm n-well CMOS, double-level polysilicon, single-polycide, and double-level metal technology. The memory cell is a surrounding hi-capacitance cell structure. The cell size is 1.8×3.0 μm², and the chip area is 12.7×16.91 mm²     

A 6-ns 1-Mb CMOS SRAM with latched sense amplifier

A 1-Mb (256 K×4) CMOS SRAM with 6-ns access time is described. The SRAM, having a cell size of 3.8 μm×7.2 μm and a die size of 6.09 mm×12.94 mm, is fabricated by using 0.5-μm triple-polysilicon and double-metal process technology. The fast access time and low power dissipation of 52 mA at 100-MHz operation are achieved by using a new NMOS source-controlled latched sense amplifier and a data-output prereset circuit. In addition, an equalizing technique at the end of the write operation is used to avoid lengthening of access time in a read cycle following a write cycle     

A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-linearchitecture

A 16-Mb dynamic RAM has been designed and fabricated using 0.5-μm CMOS technology with double-level metallization. It uses a novel trench-type surrounding high-capacitance cell (SCC) that measures only 3.3-μm² in cell size with a 63-fF storage capacitance. A novel relaxed sense-amplifier-pitch (RSAP) open-bit-line architecture used on the DRAM achieves a high-density memory cell array, while maintaining a large enough layout pitch for the sense amplifier. These concepts allow the small chip that measures 5.4×17.38 (93.85) mm² to be mounted in a 300-mil dual-in-line package with 65-ns RAS access time and 35-ns column address access time     

A step-down boosted-wordline scheme for 1-V battery-operated fastSRAM's

Fast and low-power circuit techniques for battery-operated low-voltage SRAM's are described. To shorten the read access time with low power dissipation, the step-down boosted-wordline scheme, which is combined with current-sense amplifiers, is proposed. Boosting a selected-wordline voltage shortens the bitline delay before the stored data are sensed. The power dissipation while selecting a wordline is suppressed by stepping down the selected-wordline potential. Moreover, to reduce the standby power, a switched-capacitor-type boosted-pulse generator, which is controlled by an address transition detection (ATD) signal, is used. A 61 kword×16-bit organization SRAM test chip was fabricated using the 0.5-μm multithreshold-voltage CMOS (MTCMOS) process. The power dissipation in the memory array is reduced to 57% (1 mW) at 10 kHz operation in comparison with the conventional boosted-wordline scheme