MCM—C倒装焊工艺技术研究

简要介绍了主要倒装焊技术，重点研究了实用性强、可行性好的超声热压倒装焊、导电环氧粘接倒装、ACA粘接倒装以及MCM—C基板上的芯片倒装焊区制作、倒装后芯片的下填充等工艺技术，总结了芯片倒装互连质量的主要检验要求。     

微波倒装焊互连技术及特性分析

随着应用频率的提高,微波芯片与基板间的互连更多地采用了倒装焊。文中用HFSS（高频结构仿真器）有限元软件对凸点变换及倒装互连结构进行建模、仿真和优化,提取了凸点变换的等效集总电路模型,介绍了凸点制作工艺和倒装焊结构互连的微组装过程,并完成了试验样品的测试。最后,对微波倒装焊的前景进行了展望。     

不同I/O端数金凸点倒装焊的预倒装工艺研究

金凸点热压超声倒装焊中涉及的主要工艺参数,如压力和超声功率,会随着I/O端数的改变产生较大差异。对具有不同数量I/O端的金凸点倒装焊工艺参数进行研究和优化,有助于透析产生差异的根源,指导实际生产。通过对I/O端数分别为121、225、361的金凸点倒装焊工艺参数进行研究,发现随着I/O端数量的增加,单位凸点上的最大平均剪切力依次减小,达到最大平均剪切力时所需单位凸点上的平均超声功率和平均压力依次减小。工艺窗口依次缩窄的主要原因是热压超声过程中传递的能量不均匀。在倒装焊工艺中,使用预倒装的方法可使各凸点在倒装焊中的能量分布更均匀,使用此方法对具有361个I/O端的芯片进行倒装焊,单位凸点上的平均剪切力达到了0.54 N,比未使用此方法时的平均剪切力（0.5 N）提高了8%。     

倒装焊后清洗工艺及其对底部填充的影响

倒装焊封装是通过将整个芯片有源面进行管脚阵列排布并预制焊料凸点,通过倒装焊工艺进行互连,与传统引线键合技术相比具有更高的组装密度及信号传输速率,是实现电子产品小型化、轻量化、多功能化的关键技术之一.对于小尺寸微节距的倒装焊芯片来说,焊后清洗的难度相对更大,因此清洗技术也是影响倒装焊工艺的重要因素.针对不同清洗方式及参数...     

金凸点超声热压倒装焊工艺参数优化研究

通过正交试验设计方法研究了不同工艺因素对金凸点超声热压倒装焊的影响效果。结果表明,超声功率与压力的交互作用对倒装焊后的剪切力没有显著影响,且不同因素对倒装焊后剪切力的影响效果的排序为:压力>超声功率>温度>超声时间,结合凸点形变量以及不同因素显著性的讨论得出最优条件组合,且通过试验验证达到了预测的估计值。     

用于倒装芯片的晶片凸点制作工艺研究

倒装芯片在电子封装互连中占有越来越多的份额,是一种必然的发展趋势,所以对倒装芯片技术的研究变得非常重要。倒装芯片凸点的形成是其工艺过程的关键。现有的凸点制作方法主要有蒸镀焊料凸点、电镀凸点、微球装配方法、焊料转送、在没有UBM的铅焊盘上做金球凸点、使用金做晶片上的凸点、使用镍一金做晶片的凸点等。每种方法都各有其优缺点,适用于不同的工艺要求。介绍了芯片倒装焊基本的焊球类型、制作方法及各自的特点,总结了凸点制作应注意的问题。     

热压超声倒装焊工艺研究

本文重点介绍在倒装焊工艺加工过程中,采用金丝球焊机制作金球凸点和热压超声工艺进行倒装焊的加工工艺方法。     

C4技术中多层金属化可靠性研究

本文对C4倒装焊技术所涉及凸点下多层薄膜金属(UBM)的选择、基板金属化(TSM)的选择、焊料凸点制作、焊接及影响C4倒装焊的可靠性因素进行了分析，并通过电镜扫描和电子能谱对凸点下多层薄膜金属进行了定量分析，论述了C4倒装焊技术金属化选择对可靠性的影响。     

倒装焊陶瓷封装失效模式分析及失效机理研究

随着封装技术的发展,倒装焊技术得到广泛的应用,倒装焊的研究也越来越广泛深入。文章阐述了倒装焊封装的失效模式,主要有焊点疲劳失效、填充胶分层开裂失效、电迁移失效、腐蚀失效、机械应力失效等。并分析了陶瓷基板倒装焊温度循环试验后的失效模式,陶瓷倒装焊封装失效的机理主要是倒装芯片焊点与UBM界面金属间化合物应力开裂失效。根据失效机理分析,进行陶瓷倒装焊工艺优化改进,试验达到了JESD22-A104C标准规定的温度循环:-65℃～+150℃、500次循环、3只样品无失效的要求。     

倒装焊器件的密封技术

倒装焊的底部填充属非气密性封装,并且受倒装焊凸点焊料熔点、底部填充有机材料耐温限制,使得倒装焊器件的密封结构设计和工艺设计受限。文章结合气密性器件使用要求,设计了两种不改变现行倒装焊器件制造工艺、器件总体结构[3]的密封技术,经过分析论证以及工艺实验,确认其是可行的。密封的器件能够满足MIL-883G中有关气密性、内部水汽含量、耐腐蚀(盐雾)、耐湿以及机械试验等[6~7],密封结构、密封工艺均是在现有封装工艺条件基础上进行,具有非常强的可行性。     

Low cost bumping by stencil printing: process qualification for 200 μm pitch

Area array packages (flip chip, CSP (Chip scale packages) and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment and/or are limited by the throughput, minimal pitch and yield, the industry is currently searching for new and lower cost bumping approaches. The experimental work of stencil printing to create solder bumps for flip chip devices is described in detail in this article. In the first part of this article, a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented, and the limits concerning pitch, stencil design, reproducibility and bump height will be discussed in detail. In the second part, a comparison of measured standard deviations of bump heights as well as the quality demands for ultrafine pitch flip chip assembly are shown.     

倒装芯片凸点制作方法

倒装芯片技术正得到广泛应用，凸点形成是其工艺过程的关键。介绍了现有的凸点制作方法，包括蒸发沉积、印刷、电镀、微球法、黏点转移法、SB2－Jet法、金属液滴喷射法等。每种方法都各有其优缺点，适用于不同的工艺要求。可以看到要使倒装芯片技术得到更广泛的应用，选择合适的凸点制作方法是极为重要的。     

Bump formation for flip chip and CSP by solder paste printing

Area array packages (flip chip, CSP and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment or are limited by the throughput, minimal pitch and yield the industry is currently searching for new and lower cost bumping approaches. In this paper the experimental work of stencil printing to create solder bumps for flip chip and wafer level CSP (CSP-WL) is described in detail.This paper is divided into two parts. In the first part of the paper a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless Nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented and the limits concerning pitch, reproducibility and bump height will be discussed in detail. The second part of the paper is focused on solder paste printing for wafer-level CSPs. In order to achieve large bumps an optimized printing method will be presented. Additionally advanced stencil design will be shown and the achieved results will be compared with conventional methods.     

采用热压焊工艺实现金凸点芯片的倒装焊接

金凸点芯片的倒装焊接是一种先进的封装技术.叙述了钉头金凸点硅芯片在高密度薄膜陶瓷基板上的热压倒装焊接工艺方法,通过设定焊接参数达到所期望的最大剪切力,分析研究互连焊点的电性能和焊接缺陷,实现了热压倒装焊工艺的优化.同时,还简要介绍了芯片钉头金凸点的制作工艺.     

Numerical analysis of thermo-mechanical and mobility effects for 28 nm node and beyond: Comparison and design consequences over bumping technologies

Thanks to finite elements simulation and dedicated post-processing routines, this paper explores stress induced mobility changes over three major bumping processes. A numerical comparative analysis over the assembly generations is carried out. In order to do so, models are built for solder flip chip, copper pillar flip chip and micro-copper pillar bumping. Design recommendations for MOSFET placement to include in conception tools are provided, which allow to ensure adherence to product specifications while technologies advance.     

焊球植球凸块工艺的可靠性研究

焊球植球是一种最具潜力的低成本倒装芯片凸块制作工艺.采用焊球植球工艺制作的晶圆级芯片尺寸封装芯片的凸块与芯片表面连接的可靠性问题是此类封装技术研究的重点.为此,参考JEDEC关于电子封装相关标准,建立了检验由焊球植球工艺生产的晶圆级芯片尺寸封装芯片凸块与芯片连接及凸块本身是否可靠的可靠性测试方法与判断标准.由焊球植球工艺生产的晶圆级芯片尺寸封装芯片,分别采用高温存储、热循环和多次回流进行试验,然后利用扫描电子显微镜检查芯片上凸块剖面的凸块下金属层分布和测试凸块推力大小来验证凸块的可靠性.试验数据表明焊球植球工艺生产的晶圆级芯片尺寸封装芯片具有高的封装连接可靠性.     

Novel Bumping Material for Solder‐on‐Pad Technology

A novel bumping material, which is composed of a resin and Sn3Ag0.5Cu (SAC305) solder power, has been developed for the maskless solder‐on‐pad technology of the fine‐pitch flip‐chip bonding. The functions of the resin are carrying solder powder and deoxidizing the oxide layer on the solder power for the bumping on the pad on the substrate. At the same time, it was designed to have minimal chemical reactions within the resin so that the cleaning process after the bumping on the pad can be achieved. With this material, the solder bump array was successfully formed with pitch of 150 µm in one direction.     

红外探测器倒装互连技术进展

随着红外焦平面技术的发展,红外探测器探测波段已由单波段变为双色及四色波段,半导体元件的封装数量由最初的数十个发展到数百万个,I/O输出密度不断增大,传统微互联技术如引线键合技术、载带自动焊技术等已根本无法满足器件要求。倒装焊技术以其封装尺寸小、互联密度高、生产成本低的特点越来越受到人们的亲睐。倒装互连工艺主要包括:UBM 制备、铟膜沉积、回流成球、倒压焊、填充背底胶。介绍了各工艺步骤的发展状况,并对铟膜沉积、铟柱增高工艺进行详细阐述。     

HV‐SoP Technology for Maskless Fine‐Pitch Bumping Process

Recently, we have witnessed the gradual miniaturization of electronic devices. In miniaturized devices, flip‐chip bonding has become a necessity over other bonding methods. For the electrical connections in miniaturized devices, fine‐pitch solder bumping has been widely studied. In this study, high‐volume solder‐on‐pad (HV‐SoP) technology was developed using a novel maskless printing method. For the new SoP process, we used a special material called a solder bump maker (SBM). Using an SBM, which consists of resin and solder powder, uniform bumps can easily be made without a mask. To optimize the height of solder bumps, various conditions such as the mask design, oxygen concentration, and processing method are controlled. In this study, a double printing method, which is a modification of a general single printing method, is suggested. The average, maximum, and minimum obtained heights of solder bumps are 28.3 μm, 31.7 μm, and 26.3 μm, respectively. It is expected that the HV‐SoP process will reduce the costs for solder bumping and will be used for electrical interconnections in fine‐pitch flip‐chip bonding.     

Using GA-SVM for defect inspection of flip chips based on vibration signals

Flip chip technology has been widely used in IC packaging, and the combination of flip chip technology and solder joint interconnection technology has been utilized in the manufacturing of electronic devices universally. As the development of flip chip towards high density and ultra-fine pitch, the inspection of flip chips is confronted with great challenges. In this paper, we developed an intelligent system used for the detection of flip chips based on vibration. Thirty-four features including 18 time domain features and 16 frequency domain features were extracted from the raw vibration data. The support vector machine was employed to implement the recognition and classification of flip chips. In order to improve the classification accuracy of SVM, cross validation (CV) and genetic algorithm (GA) were utilized to optimize the parameters of SVM respectively. SVM, CV-SVM and GA-SVM were applied to classification separately and the results were obtained. By comparison, GA-SVM can recognize and classify the flip chips rapidly with high accuracy. Thus, GA-SVM is effective for the defect inspection of flip chips.