Recess dependent breakdown behavior of GaAs-HFETs

GaAs based HEMT devices were fabricated with a constant recess towards the source, whereas the recess width towards the drain was varied. While the off-state breakdown voltage has been improved by the use of a wide recess towards the drain, no dependence of the on-state breakdown on the recess configuration was observed. The constant breakdown voltage in the on-state is analysed by the feedback parameters obtained from an extraction of the small signal equivalent circuit. Although the extrinsic gate drain capacitance could be reduced by the use of a wider recess configuration, it is assumed that the intrinsic drift region is independent of the recess configuration     

On-state breakdown in power HEMTs: measurements and modeling

We have carried out a systematic study of on-state breakdown in a sample set of InAlAs/InGaAs HEMT's using a new gate current extraction technique in conjunction with sidegate and temperature-dependent measurements. We find that as the device is turned on, the breakdown voltage limiting mechanism changes from a TFE-dominated process to a multiplication-dominated process. This physical understanding allows the creation of a phenomenological physical model for breakdown which agrees well with all our experimental results, and explains the relationship between BV_on and the sheet carrier concentration. Our results suggest that depending on device design, either on-state or off-state breakdown can limit maximum power     

50-nm Metamorphic High-Electron-Mobility Transistors With High Gain and High Breakdown Voltages

We report the design, fabrication, and characterization of ultrahigh-gain metamorphic high-electron-mobility transistors (MHEMTs) with significantly enhanced breakdown performance. In this letter, an asymmetrically recessed 50-nm $Gamma$-gate process has been successfully applied to epitaxial designs with double-sided-doped InAs-layer-inserted channels grown on GaAs substrates. The critical gate recess width has been optimized for device performance, including transconductance, breakdown voltage, and gain. The employment of a device passivation process greatly minimizes the adverse impacts that the aggressive vertical and lateral scaling would have introduced for pursuing enhanced performance. As a result, we have achieved 1.9-S/mm transconductance and 800-mA/mm maximum drain current at a drain bias of 1 V, 9-V off-state breakdown voltage, approximately 3.5-V on-state breakdown voltage, and 14.2-dB maximum stable gain at 110 GHz. To our knowledge, this is a record combination of gain and breakdown performance reported for microwave and millimeter-wave HEMTs, making these devices excellent candidates for ultrahigh-frequency power applications.      

用于智能功率集成电路的PTG-LDMOST

提出一种用于智能功率集成电路的基于绝缘体上硅(SOI)的部分槽栅横向双扩散MOS晶体管(PTG-LDMOST)。PTG-LDMOST由传统的平面沟道变为垂直沟道,提高了器件击穿电压与导通电阻之间的折衷。垂直沟道将开态电流由器件的表面引向体内降低了导通电阻,而且关态的时候耗尽的JFET区参与耐压,提高单位漂移区长度击穿电压。仿真结果表明:对于相同的10微米漂移区长度,新结构的击穿电压从常规结构的111V增大到192V,增长率为73%。     

A polycrystalline silicon thin-film transistor with a thinamorphous buffer

We have developed a novel, low off-state leakage current polycrystalline silicon (poly-Si) thin-film transistor (TFT) by introducing a very thin hydrogenated amorphous silicon (a-Si:H) buffer on the poly-Si active layer. The a-Si:H buffer is formed on the whole poly-Si and thus no additional mask step is needed. With an a-Si:H buffer on poly-Si, the off-state leakage current of a coplanar TFT is remarkably reduced, while the reduction of the on-state current is relatively small. The poly-Si TFT with an a-Si:H buffer exhibited a field effect mobility of 12 cm²/Vs and an off-state leakage current of 3 fA/μm at the drain voltage of 1 V and the gate voltage of -5 V     

Voltage-splitting technique for reliability evaluation of off-state mode of MOSFETs in ultrathin gate oxides

A simple and practical new methodology is proposed for reliability evaluation of off-state mode in ultrathin oxides. By applying a negative voltage on the gate while the drain region is biased at the operating voltage; the so-called voltage-splitting technique (VST), we successfully resolve the difficulty associated with the unrealistic high drain-bias stress otherwise required, which leads to the excessive damage to oxide integrity in the overlap region. In comparison with a high drain-bias stress, the time-dependent dielectric breakdown measurements using VST show the well-behaved breakdown distribution and correlate with the measured device characteristics. In addition, this methodology may provide a possible method to extrapolate stress data to operational voltage for realistic off-state reliability projection.     

Decrease in on-state gate current of AlGaN/GaN HEMTs by recombination-enhanced defect reaction of generated hot carriers investigated by TCAD simulation

Changes in the on-state gate current of AlGaN/GaN high-electron-mobility transistors (HEMTs) under various electrical and thermal stress conditions have been analyzed by technology computer-aided design (TCAD) simulation. A larger gate current is observed under on-state bias condition than that under off-state bias condition. The TCAD simulation indicates that on-state gate current flows from the heated gate electrode to the AlGaN layer by tunneling or hopping through the gate depletion layer when we apply some deep-donor-type traps under the gate in the AlGaN barrier layer. The gate current is caused by electrons that flow and is pulled away by the applied gate-to-drain voltage under a high channel temperature condition. The deep traps benefit both the on- and off-state gate current behavior. We found that the on-state gate current is effectively decreased by electrical stress under the on-state condition. Electroluminescence measurement indicates that a large number of hot carriers are generated under this condition. The results suggest that the process-induced crystal defects are annealed out by non-radiative recombination of the generated hot carriers by a recombination-enhanced defect reaction mechanism. The change in the on-state gate current in the TCAD simulation can be successfully explained by the decrease in the donor traps.     

Planar Power MOSFETs for Smart Power CMOS Switches

Planar power MOSFETs with an octagonal gate are designed, fabricated, and tested. The implantation dose of the pinch-resistor region is optimized for off-state breakdown voltage times on-state resistance by computer simulation.     

Leakage current variation during two different modes of electrical stressing in undoped hydrogenated n-channel polysilicon thin film transistors (TFTs)

Leakage current evolution during two different modes of electrical stressing in hydrogenated-undoped n-channel polysilicon thin film transistors (TFTs) is studied in this work. On-state bias stress (high drain bias and positive gate bias) and off-state bias stress (high drain bias and negative gate bias) were performed in order to study the degradation of the leakage current. It is found that during off-state bias stress the gate oxide is more severely damaged than the SiO₂-polySi interface. In contrast, during on-state bias stress, two different degradation mechanisms were detected which are analyzed.     

Determination and assessment of the floating-body voltage of SOICMOS devices

A self-consistent method to extract the off-state floating-body (FB) voltage of SOI CMOS devices is presented. The technique is simple and is based on CV and S-parameter measurements of a single standard SOI MOSFET device; no special test structure design is needed. The bias dependent S-parameter measurements of the FB SOI device and its equivalent circuit, along with the CV measurements between the drain and source of the same device, are used to determine the FB voltage. The technique provides reasonable insight on device off-state and leakage performances that are important for digital applications. Additionally, it proposes a method for the extraction of the parasitic source, drain, and gate resistances. Using the technique, FB voltage in excess of 0.4 V is measured in a partially depleted (PD) NMOS device at drain voltage of 2.5 V and zero gate voltage, demonstrating the importance of understanding FB effects on device off-state and junction leakage performances     

SJ/RESURF LDMOST

A monolithic lateral double diffused MOSFET (LDMOST) based on the super junction (SJ) concept is proposed to significantly improve the device's on-state and off-state characteristics. The device structure features a split drift region made of two parts: 1) an SJ structure that extends over most of the drift region and 2) a terminating reduced surface field (RESURF) region occupying a portion of the drift region adjacent to the n/sup +/ drain. This structure suppresses substrate-assisted depletion effects and ensures complete depletion and near uniform electric field distribution over the entire drift region. In the on-state, the high conductivity of the SJ drift region results in a significant improvement in the specific on-resistance for a given breakdown voltage (BV) and, hence, a reduction in the on-state, switching, and gate-drive losses. In the off-state, the RESURF region, located near the n/sup +/ drain, effectively neutralizes the substrate-assisted depletion effects and results in high BV.     

Study of the leakage current suppression for hybrid-Schottky/ohmic drain AlGaN/GaN HEMT

The leakage current suppression mechanism in AlGaN/GaN High Electron Mobility Transistors (HEMTs) is investigated. It is known that leakage current can cause severe reliability problems for HEMT devices and conventional AlGaN/GaN HEMT devices suffer from detrimental off-state drain leakage current issues, especially under high off-state drain bias. Therefore, a leakage current suppression technique featuring hybrid-Schottky/ohmic-drain contact is discussed. Through the 2-zones leakage current suppression mechanism by the hybrid-Schottky/drain metal including the shielding effect of the rough ohmic-drain metal morphology and the drain side electric field modulation, AlGaN/GaN HEMT featuring this novel technique can significantly enhance the leakage current suppression capability and improve the breakdown voltage. An analytical method using loop-voltage-scanning is proposed to illustrate the optimization procedure of the hybrid-Schottky/ohmic drain metallization on leakage current suppression. Through the comparison of the loop leakage current hysteresis of conventional ohmic drain HEMT and hybrid-Schottky/ohmic drain, the leakage current suppression mechanism is verified through the leakage current considering surface acceptor-like trap charging/discharging model. Device featuring the hybrid-Schottky/ohmic drain technique shows an improvement in breakdown voltage from 450 V (with no Schottky drain metal) to 855 V with a total drift region length of 9 μm, indicating enhanced off-state reliability characteristics for the AlGaN/GaN HEMT devices.     

Electroluminescence analysis of HFET's breakdown

In this letter, we correlate different breakdown mechanisms occurring near pinch-off and in off-state conditions in power AlGaAs/GaAs heterojunction FETs (HFETs), operated in “three terminals” (on-state) and “two-terminals” (off-state) modes, to electroluminescence emission due to high energy carriers, electrons, and holes. In particular we will use spectral analysis and spatially resolved emission analysis in order to identify regions of the device where hot and cold carriers emit light. We will show how under “three-terminals” breakdown conditions high energy carriers emit light at the drain side of the gate while cold carriers recombine mostly at the source side of the gate     

Effects of drift region parameters on the static properties of power LDMOST

The effects of the drift region geometry and the physical parameters on the thin layer (resurfed) lateral DMOS transistor operation have been studied for both the static on-state and the off-state. The variations of breakdown voltage with drift region parameters were investigated using numerical modeling and compared to the experimental results. The operation of the LDMOST in the on-channel condition was modeled semi-empirically. The analytical and experimental results show that the operation of the device depends strongly on the geometry and the physical parameters of the drift region, particularly at high gate voltages and low drain voltages. Design guidelines for the lateral DMOS transistor for switching applications are discussed.     

Off-state breakdown in power pHEMTs: the impact of the source

Conventional wisdom suggests that in pseudomorphic high electron mobility transistors (pHEMTs), the field between the drain and the gate determines off-state breakdown, and that the drain to gate voltage therefore sets the breakdown voltage of the device. Thus, the two terminal breakdown voltage is a widely used figure of merit, and most models for breakdown focus on the depletion region in the gate-drain gap, while altogether ignoring the source. We present extensive new measurements and simulations that demonstrate that for power pHEMTs, the electrostatic interaction of the source seriously degrades the device's gate-drain breakdown. We identify the key aspect ratio that controls the effect, L_G:x_D where L_G is the gate length and x_D is the depletion region length on the drain. This work establishes that the design of the source must be taken into consideration in the engineering of high-power pHEMT's     

A p-channel poly-Si/Si1-xGex/Si sandwichedconductivity modulated thin-film transistor

A p-channel poly-Si/Si_1-xGe_x/Si sandwiched conductivity modulated thin-film transistor (CMTFT) is proposed and demonstrated in this paper for the first time. This structure uses a poly-Si/Si_1-xGe_x/Si sandwiched structure as the active layer to avoid the poor interface between the gate oxide and the poly-Si_1-xGe_x material. Also an offset region placed between the channel and the drain is used to reduce the leakage current. Furthermore, the concept of conductivity modulation in the offset region is used to provide high on-state current. Results show that this structure provides high on-state current as well as low leakage current as compared to that of conventional offset drain TFTs. The on-state current of the structure is 1.3-3 orders of magnitude higher than that of a conventional offset drain TFT at a gate voltage of -24 V and drain voltage ranging from -15 to -5 V while maintaining comparable leakage current     

On-state and off-state stress-induced degradation in unhydrogenated solid phase crystallized polysilicon thin film transistors

The effects of DC bias gate and drain on-state and off-state stresses on unhydrogenated solid phase crystallized polysilicon thin film transistors were investigated. The observed, under gate bias stress, threshold voltage turnaround from an initial negative shift due to hole trapping to positive shift with logarithmic time dependence attributed to electron trapping was suppressed when a drain bias was added for a combined gate–drain on-state stress; this suppression was more effective for larger gate bias. The subthreshold swing, the midgap trap state density and the transconductance exhibited logarithmic degradation, in line with the positive V_th shift. The stressing time needed for V_th turnaround decreased, indicating increase of electron trapping, and the midgap trap state density increased in correlation with increasing stressing current I_DS as stressing V_DS increased, for a given on-state stressing V_GS. Off-state gate–drain stressing resulted in logarithmic positive V_th shift, after a small initial negative shift, and in reduction of the leakage current due to stress-induced shielding of the gate field. An applied inverse stress resulted in less severe V_th degradation due to stress-induced effects being more concentrated near the source rather than the drain in that case.     

High-breakdown characteristics of the InP-based heterostructurefield-effect transistor withIn0.34Al0.66As0.85Sb0.15Schottky layer

We report improved breakdown characteristics of InP-based heterostructure field-effect transistors (HFET's) utilizing In_0.34 Al_0.66As_0.85Sb_0.15 Schottky layer grown by low-pressure metalorganic chemical vapor deposition. Due to high energy bandgap and high Schottky barrier height (>0.73 eV) of the In_0.34Al_0.66As_0.85Sb_0.15 Schottky layer, high two-terminal gate-to-drain breakdown voltage of 40 V, three-terminal off-state breakdown voltage of 40 V three-terminal threshold-state breakdown voltage of 31 V, and three-terminal on-state breakdown voltage of 18 V at 300 K for In_0.75Ga_0.25As channel, are achieved. Moreover, the temperature dependence of two-terminal reverse leakage current is also investigated. The two-terminal gate-to-drain breakdown voltage is up to 36 V at 420 K. A maximum extrinsic transconductance of 216 mS/mm is obtained with a gate length of 1.5 μm     

A Conductivity Modulated Polysilicon Thin-Film Transistor

This paper reports a novel high voltage Conductivity Modulated Thin-Film Transistor (CMTFT) fabricated using polycrystalline silicon. The transistor uses the idea of conductivity modulation in the offset region to obtain a significant reduction in on-state resistance. Experimental on-state and off-state current-voltage characteristics of the CMTFT have been compared with those of the conventional offset drain device. Results show that the CMTFT has six times to more than three orders of magnitude higher on-state current handling capability for operating at drain voltages ranging from 15 V to 5 V while still maintaining low leakage current and providing even faster switching speed. The CMTFT devices can be fabricated using a low temperature process (620°C) which is highly desirable for large area electronic applications