Switched-capacitor discrete Fourier analyser with window function circuit

An analogue window function circuit is realized by using switched-capacitor techniques. In order to verify the effect of this window, a novel switched-capacitor analogue discrete Fourier analyser is proposed. The window function circuit is included in this analyser as the ratios of capacitances. This switched-capacitor discrete Fourier analyser is very simple in construction, namely, only two elemental circuits based on the integral feedback capacitance circuit are connected in series. Agreement between the experimental and the theoretical values is confirmed.     

Switched-capacitor DAC with analogue mismatch correction

A background calibration method for enhancing the accuracy and linearity of a switched-capacitor digital-to-analogue converter is described. The method can be used alone or in combination with mismatch shaping to achieve very high accuracy and linearity combined with high speed     

Switched-capacitor integrators with low finite-gain sensitivity

Compensated SC integrator stages are analysed and compared with respect to their sensitivities to finite amplifier gain effects. Simple single-stage amplifiers may be used in such circuits even in highly selective filtering applications. This may allow an extension of the present frequency range of SC circuits.     

Switched-capacitor resonator structure with improved performance

A novel switched-capacitor resonator circuit is proposed. Its centre frequency is insensitive to the finite bandwidth and gain of the opamps used     

A high-speed current-multiplexed sample-and-hold amplifier with lowhold step

A monolithic high-speed sample-and-hold amplifier is described. It minimizes the hold step via a new circuit architecture. This design takes advantage of the speed of open-loop sample-and-hold circuits during the sample mode and cancellation of charge injection by duplicating and feeding it through a second amplifier during the hold mode. The unique feature of the design is an acquisition time of 150 ns to 0.01% of a 10-V step including the time required for all internal nodes to settle after the hold command is given. Aperture uncertainty is less than 20 ps and linearity is 0.003%. The device has 10-pF on-chip hold and dummy capacitors and the die size is 8.548 mm² on a junction-field-effect-transistor (JFET) plus complementary bipolar process     

A modified generalized discrete transform

A modified version of the generalized discrete transform described earlier is now developed. The transform matrix of this modified version has a number of zeros as its elements, and consequently its matrix factors are more sparse. This results in fewer arithmetic operations and corresponding savings in computer time, when information is processed.     

Switched-capacitor bandpass filter with quasi-continuous digitalQ-factor tunability

A second-order switched-capacitor (SC) bandpass filter with very wide Q-factor programmability range, is presented. Although the Q-factor is controlled by digitally varying the effective sampling frequency of an SC branch, quasi-continuous programmability is provided. Experimental results from a 0.8 μm CMOS integrated prototype demonstrate the versatility of the proposed technique     

Switched-capacitor integrator with reduced sensitivity to amplifier gain

A new switched-capacitor integrator with low sensitivity to finite amplifier gain is described. The circuit is simple, requiring very little extra chip area as compared to the uncompensated integrator. It is compared with previously proposed finite gain compensated switched-capacitor integrators.     

Switched-capacitor biquad with low influence of finite gains

The letter describes a switched-capacitor (SC) biquad which exhibits less effect of the finite gains on the Q-factor and centre frequency than other known biquads of this type. The properties of the circuit have been established by extensive simulation studies using a symbolic analysis program.     

A switched-ca pari tor delay line with self-equalizing sample-and-hold

A simple SC delay line using a three-phase clock is described. The new circuit uses a reduced number of operational amplifiers and includes a circuit for correcting the amplitude deviation arising from the sample-and-hold effect Unlike previous circuits this circuit does not affect the group-delay of the delay line. An example for a 10μS delay line in the frequency range 0-250 kHz is given.     

Switched-capacitor filters driven with very low voltage clock signals

It is well known that the switches of a very low voltage (1.5V) switched-capacitor filter in a standard CMOS process must be driven with a clock signal higher than the power supply, often generated on-chip. The authors present, however, a technique to implement very low voltage switched-capacitor filters with switches driven at the same very low voltages.<>     

A precision FET-less sample-and-hold with high charge-to-droop current ratio

A monolithic sample-and-hold amplifier designed without field-effect transistors is described. Various sample-and-hold configurations are compared and their merits are discussed. Unique features of the design include a diode-bridge switch and a current booster with 50 mA of drive capability to charge the hold capacitor during large signal acquisition. The output amplifier's operating conditions are changed under logic control; it functions as a fast follower in the sample mode, and as a low input current amplifier in the hold mode. Performance characteristics include: 3.5-/spl mu/s acquisition time to 0.1 percent with a 5000-pF hold capacitor, 50 pA of droop current from 0 to 70/spl deg/C, 10/SUP 9/ charge-to-droop current ratio, and 0.3 mV of zero-scale error.     

Microprocessor-based modified discrete integral variable-structurecontrol for UPS

This paper presents a digital signal processor microprocessor-based high-performance uninterruptible power system (UPS). It also modifies the integral variable-structure control (IVSC) approach to be more suitable for the UPS, which is tracking a sinusoidal AC voltage with specified frequency and amplitude. Since the implementation of the control laws has tended to the digital microprocessor, the paper extends the modified IVSC to the discrete time domain. Procedures are developed for determining the control function, the switching plane and the integral control gain, so that the system has desired properties. Simulation and experimental results show that the proposed scheme can supply a high-quality voltage power source in the presence of load disturbance and parameter variation     

Switched-capacitor track-and-hold amplifier with low sensitivity to op-amp imperfections

This paper describes a high-precision switched-capacitor (SC) track-and-hold amplifier (THA) stage. It uses a novel continuous-time correlated double sampling (CDS) scheme to desensitize the operation to amplifier imperfections. Unlike earlier predictive-CDS THAs, the circuit does not need a sample-and-held input signal for its operation. During the tracking period, an auxiliary continuous-time signal path is established, which predicts the output voltage during the holding period. This allows accurate operation even for low amplifier gains and large offsets over a wide input frequency range. Extensive simulations were performed to compare the performance of the proposed THA with earlier circuits utilizing CDS. The results verify that its operation is far more robust than that of any previously described THA.     

Switched-capacitor DC/DC converters with resonant gate drive

In this paper, we examine how switched-capacitor (SC) converters can be used in low-voltage low-power DC/DC applications with power management. Analysis of losses is presented to facilitate SC converter design and optimization. A resonant gate drive is proposed to reduce switching losses and simplify control of switches in SC converters. A closed-loop controller is designed to enable and disable oscillations of the resonant gate drive so that the output DC voltage is well regulated down to zero load and so that high efficiency is maintained for a very wide range of loads. Results are experimentally verified on two low-power (0.2 and 5 W) five-one step-down converters with regulated 3 Vdc output and efficiency greater than 80% in a 100-1 load range     

Current memory based differentiator with protection of storage node

A time-domain differentiator based on current memory is presented. To ensure processing accuracy, an MOS charge divider is used to reduce the effect of charge injection and a well (n or p type) is used to protect the storage device from minority carrier diffusion in the substrate. The circuit operates at low current levels. A single-poly CMOS technology can be used for circuit implementation     

Integrator and differentiator with time constant multiplicationusing current feedback amplifier

A set comprising an active RC integrator and differentiator with time constant multiplication is presented. The proposed integrator and the differentiator can be used for low-frequency signal processing applications. Moreover, no extremely large-valued passive components are needed. In the integrator, the unlimited multiplication of time constants is allowed. Both have been implemented using commercially available current feedback amplifiers. Experimental results demonstrate the theoretical predictions     

A modified discrete control law for UPS applications

This paper presents a model reference controller with a repetitive control action for uninterruptible power supply (UPS) applications. The model reference controller modifies the structure of the plant so that the closed-loop transfer function is equal to a chosen reference model transfer function, whereas the repetitive control action minimizes periodic distortions caused by unknown periodic disturbances. Design procedure and stability analysis of the control scheme are discussed. Simulation and experimental results for a single-phase PWM inverter (110 V/sub RMS/, 1 kVA) controlled by a low cost microcontroller are presented to verify the performance of the proposed control approach under different load conditions.     

Analysis and recovery of sample-and-hold and linearly interpolatedsignals with irregular samples

A modular method is suggested to recover a bandlimited signal from the sample-and-hold and linearly interpolated (or, in general, an n th-order hold) version of the irregular samples. The approach is an extension of work for the sample-and-hold signals with uniform samples. A coordinate transform technique is applied to show a practical way of finding an approximate inverse coordinate mapping. As a byproduct, some sufficient conditions on the nonuniform samples for the modular technique to the valid are derived