Efficient Realization of Large Size Two’s Complement Multipliers Using Embedded Blocks in FPGAs

This paper presents an optimized design approach for two’s complement large size multipliers using smaller size embedded multiplier blocks available as resources in field programmable gate arrays (FPGAs). The realization is based on the Baugh–Wooley algorithm, which segments the multiplication into unsigned and signed components. To achieve efficient implementation results, a set of optimized schemes for the realization of the additions required for the unsigned multipliers and for combining the unsigned and signed components is proposed. The implementations of the multipliers have been carried out for operands with sizes ranging from 20 to 128 bits. The designs are synthesized and implemented on Xilinx’s Spartan-3 in the ISE 8.1 design platform and compared with three other realizations using the following approaches: (1) conventional sign-extension approach, (2) Xilinx’s IP-Core generator, and (3) sign-and-magnitude-based approach. The experimental results indicate that our proposed method outperforms the other techniques.     

STUDY ON THE RELATION BETWEEN STRUCTURE AND HOT CARRIER EFFECT IMMUNITY FOR DEEP SUB-MICRON GROOVED GATE NMOSFET’s

Grooved gate structure Metal-Oxide-Semiconductor(MOS) device is considered as the most promising candidate used in deep and super-deep sub-micron region,for it can suppress hot carrier effect and short channel effect deeply.Based on the hydrodynamic energy transoprt model,using two-dimensional device simulator Medici,the relation between structure parameters and hot carrier effect immunity for deep-sub-micron N-channel Mosfet‘s is studied and compared with that of counterpart conventional planar device in this paper.The examined structure parameters include negative junction depth,conventinal planar device in this paper.The examined structure parameters include negative junction depth,concave corner and effective channel length.Simulation results show that grooved gate device can suppress hot carrier effect is strongly influenced by the concave corner and channel length for grooved gate device.With the increase of concave corner,the hot carrier effect in groovd gate MOSFET decreases sharply,and with the reducing of effective channel length,the hot carrier effect becomes large.     

Minimum Path Exposure and Detection Interval Setting for Target Detection Using Wireless Sensor Network

Sensor network generally detects target at a fixed frequency. Detection interval means time spacing between two adjacent detection attempts. While designing a sensor network for detection of target intrusion in a specific region, the interval should be carefully set with trade-off between power consumption and detection performance. This is because redundant power may be consumed if it is too short and the target may be missed if too long. In this paper, we study the determination of the maximum detection interval (MDI) with specified detection performance. Path exposure is adopted as a performance metric. For detection-oriented application, a novel method to evaluate the minimum path exposure (MPE) is developed. Then the MDI problem is formulated and its solution is presented. The factors influencing the MDI are extensively simulated.

Separate/joint optimization of error feedback and realization for roundoff noise minimization in a class of 2-D state-space digital filters

Techniques for the separate/joint optimization of error-feedback and realization are developed to minimize the roundoff noise subject to l ₂-norm dynamic-range scaling constraints for a class of 2-D state-space digital filters. In the joint optimization, the problem at hand is converted into an unconstrained optimization problem by using linear-algebraic techniques. The unconstrained problem obtained is then solved by applying an efficient quasi-Newton algorithm. A numerical example is presented to illustrate the utility of the proposed techniques.