A CMOS analog front-end IC for portable EEG/ECG monitoring applications

A new digital programmable CMOS analog front-end (AFE) IC for measuring electroencephalograph or electrocardiogram signals in a portable instrumentation design approach is presented. This includes a new high-performance rail-to-rail instrumentation amplifier (IA) dedicated to the low-power AFE IC. The measurement results have shown that the proposed biomedical AFE IC, with a die size of 4.81 mm/sup 2/, achieves a maximum stable ac gain of 10 000 V/V, input-referred noise of 0.86 /spl mu/ V/sub rms/ (0.3 Hz-150 Hz), common-mode rejection ratio of at least 115 dB (0-1 kHz), input-referred dc offset of less than 60 /spl mu/V, input common mode range from -1.5 V to 1.3 V, and current drain of 485 /spl mu/A (excluding the power dissipation of external clock oscillator) at a /spl plusmn/1.5-V supply using a standard 0.5-/spl mu/m CMOS process technology.     

A 1.1-V 270-/spl mu/A mixed-signal hearing aid chip

This paper presents a single-chip mixed-signal IC for a hearing aid system. The IC consumes 270 /spl mu/A of supply current at a 1.1-V battery voltage. The presented circuit and architectural design techniques reduce the total IC power to 297 /spl mu/W, a level where up to 70 days of lifetime is achieved at 10 h/day for a small zinc-air battery. The measured input referred noise for the entire channel is 2.8 /spl mu/Vrms and the average THD in the nominal operating region is 0.02%. The jitter for the on-board ring oscillator is 147 ps rms. The chip area is 12 mm/sup 2/ in a 0.6-/spl mu/m 3.3-V mixed-signal CMOS process.     

A 402-output TFT-LCD driver IC with power control based on the number of colors selected

A 402-output thin-film-transistor liquid crystal display (TFT-LCD) driver integrated circuit (IC) with power control based on the number of colors to be displayed is described. To achieve this type of power control, reference voltage buffers are turned on and off according to the selected number of colors. In this architecture, the reference voltage buffers must drive 1-402 capacitive loads, corresponding to a capacitance of 30-12000 pF. Phase compensation using a zero formed with capacitive loads is proposed for the reference voltage buffers. The introduced zero has a fixed zero frequency for 1-402 loads. An operational amplifier with slew-rate enhancement is also proposed for the buffers. An experimental 402-output TFT-LCD driver IC was fabricated using a 0.6-/spl mu/m CMOS technology. The chip size was 2.35 mm /spl times/ 18.1 mm. The quiescent current dissipation of the analog section including decoders was 529 /spl mu/A for 262144 colors, 182 /spl mu/A for 4096 colors, and 112 /spl mu/A for 512 colors for a 5-V supply.     

Analysis, design, and performance of micropower circuits for a capacitive pressure sensor IC

An integrated circuit has been designed, built, and testing as part of a capacitive pressure transducer. High-accuracy compact micropower circuits utilizing a standard bipolar IC process without any special components or trimming are used. The key circuits for achieving this performance are a Schmitt trigger oscillator and a bandgap voltage reference. The sensor circuits consume 200 /spl mu/W at 3.5 V, can resolve capacitance changes of 300 p.p.m., measure temperature to /spl plusmn/0.1/spl deg/C over a limited temperature range, and presently occupy 4 mm/SUP 2/ on a 2 mm/spl times/6 mm implantable monolithic silicon pressure sensor. Further scaling of the sensor is discussed showing that a reduction of area by a factor of 4 is achievable.     

A 10-Gb/s CDR/DEMUX with LC delay line VCO in 0.18-/spl mu/m CMOS

A monolithic 10-Gb/s clock/data recovery and 1:2 demultiplexer are implemented in 0.18-/spl mu/m CMOS. The quadrature LC delay line oscillator has a tuning range of 125 MHz and a 60-MHz/V sensitivity to power supply pulling. The circuit meets SONET OC-192 jitter specifications with a measured jitter of 8 ps p-p when performing error-free recovery of PRBS 2/sup 31/-1 data. Clock and data recovery (CDR) is achieved at 10 Gb/s, demonstrating the feasibility of a half-rate early/late PD (with tri-state) based CDR on 0.18-/spl mu/m CMOS. The 1.9/spl times/1.5 mm/sup 2/ IC (not including output buffers) consumes 285 mW from a 1.8-V supply.     

A 3.3-mW /spl Sigma//spl Delta/ modulator for UMTS in 0.18-/spl mu/m CMOS with 70-dB dynamic range in 2-MHz bandwidth

A quadrature fourth-order, continuous-time, /spl Sigma//spl Delta/ modulator with 1.5-b quantizer and feedback digital-to-analog converter (DAC) for a universal mobile telecommunication system (UMTS) receiver chain is presented. It achieves a dynamic range of 70 dB in a 2-MHz bandwidth and the total harmonic distortion is -74 dB at full-scale input. When used in an integrated receiver for UMTS, the dynamic range of the modulator substantially reduces the need for analog automatic gain control and its tolerance of large out-of-band interference also permits the use of only first-order prefiltering. An IC including an I and Q /spl Sigma//spl Delta/ modulator, phase-locked loop, oscillator, and bandgap dissipates 11.5 mW at 1.8 V. The active area is 0.41 mm/sup 2/ in a 0.18-/spl mu/m 1-poly 5-metal CMOS technology.     

A low-voltage BiMOS op amp

Describes the development of a threshold implanted BiMOS amplifier IC optimized for 2-5 V operation at a supply current of 300 /spl mu/A. A nonlinear operational transconductance amplifier (OTA) buffer having on-chip feedback provides a low-impedance rail-to-rail output, and a bulk-modulated PMOS input pair extends the common-mode range. Protective-network bootstrapping makes possible subpicoampere input-bias currents below 85/spl deg/C, and improved offset stability is achieved by the choice of threshold-level stage currents. Amplifier design is straightforward and readily applied from `micropower' to `broad-band' operating ranges. The combination of these features has produced a unique high-performance integrated circuit.     

A low-power integrated tuner for cable telephony applications

This paper describes an integrated tuner for cable telephony in a 0.35 /spl mu/m, 27 GHz SOI BiCMOS technology. The IC integrates a complete dual-conversion signal path including upconverter, downconverter, variable-gain amplifier, LO synthesizers with fully integrated voltage-controlled oscillators, gain control circuitry, as well as digital calibration and interface circuits. It accepts signals in the 200-880 MHz band and produces a 44 MHz IF. Drawing 168 mA from a 3 V supply, the tuner system has a worst case noise factor of 7.3 dB, system phase noise below -78 dBc/Hz at a 10 kHz offset, spurs below -42 dBc for 137 5 dBmV input channels, a gain of 60 dB, and gain control range of 68 dB. The 13 mm/sup 2/ IC meets specifications across an outdoor temperature range of -40/spl deg/C to 100/spl deg/C in production lots.     

Highly integrated direct conversion receiver for GSM/GPRS/EDGE with on-chip 84-dB dynamic range continuous-time /spl Sigma//spl Delta/ ADC

This paper describes a highly digitized direct conversion receiver of a single-chip quadruple-band RF transceiver that meets GSM/GPRS and EDGE requirements. The chip uses an advanced 0.25-/spl mu/m BiCMOS technology. The I and Q on-chip fifth-order single-bit continuous-time sigma-delta (/spl Sigma//spl Delta/) ADC has 84-dB dynamic range over a total bandwidth of /spl plusmn/135 kHz for an active area of 0.4 mm/sup 2/. Hence, most of the channel filtering is realized in a CMOS IC where digital processing is achieved at a lower cost. The systematic analysis of dc offset at each stage of the design enables to perform the dc offset cancellation loop in the digital domain as well. The receiver operates at 2.7 V with a current consumption of 75 mA. A first-order substrate coupling analysis enables to optimize the floor plan strategy. As a result, the receiver has an area of 1.8 mm/sup 2/.     

A quad-band GSM-GPRS transmitter with digital auto-calibration

A low-power low-voltage fully integrated fast-locking quad-band (850/900/1800/1900-MHz) GSM-GPRS transmitter is described. It exploits closed-loop phase-locked loop (PLL) upconversion using a modulated fractional-N frequency synthesizer with digital auto-calibration. It uses a type-I PLL in a mostly digital IC with no external components and achieves a lock time of 43 /spl mu/s, a tuning range of 500 MHz, receive-band phase noise of -158dBc/Hz and -165 dBc/Hz for the high and low bands, respectively, and reference feed through of -93.9 dBc. It is implemented in 2.1 mm/sup 2/ using a 0.13-/spl mu/m CMOS process and meets all quad-band GSM transmitter specifications with a current consumption of only 28 mA from a single 1.5-V power supply.     

A 4-/spl mu/a quiescent-current dual-mode digitally controlled buck converter IC for cellular phone applications

This paper describes a dual-mode digitally controlled buck converter IC for cellular phone applications. An architecture employing internal power management is introduced to ensure voltage compatibility between a single-cell lithium-ion battery voltage and a low-voltage integrated circuit technology. Special purpose analog and digital interface elements are developed. These include a ring-oscillator-based A/D converter (ring-ADC), which is nearly entirely synthesizable, is robust against switching noise, and has flexible resolution control, and a very low power ring-oscillator-multiplexer-based digital pulse-width modulation (PWM) generation module (ring-MUX DPWM). The chip, which includes an output power stage rated for 400 mA, occupies an active area 2 mm/sup 2/ in 0.25-/spl mu/m CMOS. Very high efficiencies are achieved over a load range of 0.1-400 mA. Measured quiescent current in PFM mode is 4 /spl mu/A.     

A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC

A 1.8-V 15-bit 40-MSample/s CMOS pipelined analog-to-digital converter with 90-dB spurious-free dynamic range (SFDR) and 72-dB peak signal-to-noise ratio (SNR) over the full Nyquist band is presented. Its differential and integral nonlinearities are 0.25 LSB and 1.5 LSB, respectively, and its power consumption is 400 mW. This performance is enabled by digital background calibration of internal digital-to-analog converter (DAC) noise and interstage gain errors. The calibration achieves improvements of better than 12 dB in signal-to-noise plus distortion ratio and 20 dB in SFDR relative to the case where calibration is disabled. Other enabling features of the prototype integrated circuit (IC) include a low-latency, segmented, dynamic element-matching DAC, distributed passive input signal sampling, and asymmetric clocking to maximize the time available for the first-stage residue amplifier to settle. The IC is realized in a 0.18-/spl mu/m mixed-signal CMOS process and has a die size of 4mm/spl times/5 mm.     

A two-terminal IC temperature transducer

A bipolar monolithic IC temperature transducer with an operating temperature range of -125/spl deg/C to +200/spl deg/C has been designed, fabricated, and tested. The two-terminal device, which is fabricated using laser trimmed thin-film-on-silicon technology, is a calibrated temperature dependent current source with an average output impedence of 10 M/spl Omega/ over the 3.5-V to 30-V range of input voltage. Overall absolute accuracies of /spl plusmn/0.5/spl deg/C from -75/spl deg/C to +150/spl deg/C have been achieved on a scale of 1 /spl mu/A/K under optimum operating conditions.     

Optical receiver IC for CD/DVD/blue-laser application

In this paper, an optoelectronic receiver IC for CD, DVD, and Blue-Laser optical data storage applications is presented. The IC was developed in a 0.5-/spl mu/m BiCMOS technology with integrated PIN photodiodes. It includes a new architecture of high-speed and low-noise variable gain transimpedance amplifiers witch current preamplifier input. The amplifier transimpedance gain is programmable over a gain range of 130 /spl Omega/ to 270 k/spl Omega/ by a serial interface. The amplifier small-signal bandwidth is 260 MHz for the highest gain, which gives a gain-bandwidth product of 70 THz/spl Omega/ and a sensitivity improvement by a factor of 2 compared to published OEICs. The amplifiers support a special write/clip mode which realizes a nonlinear gain reduction for high input signals. The output voltage buffers are 130-/spl Omega/ impedance matched for optimized data transmission over a flex cable. The impedance is generated by active-impedance synthesis to increase the output dynamic range.     

Single Ping-multiple measurements: sonar bearing angle estimation using spatiotemporal frequency filters

Presented is a mixed-signal full-custom VLSI chip designed to receive sonar return signals from an ultrasonic microphone array, and extract input bearing angles of the incoming signals. Processing utilizes simple low-power analog spatiotemporal bandpass filters to extract wavefront velocity across the array, which translates to input bearing angle. Processing uses phase information of array signals, not onset or offset of ultrasonic burst. With such synchronous processing, multiple angle readings from different returns of the same ultrasonic transmit burst are possible. Compatible microphone arrays are compact in size-test array has a total baseline of 26.5 mm. In a test with ultrasonic beacon 65 cm from a microphone array, angular precision of 1/spl deg/ was demonstrated in most instances in the range -60/spl deg/ to 60/spl deg/. Applications include sonar localization of remote objects, sonar imaging, and improved interference rejection between objects within the field of view of the sensor microphones. The chip was fabricated on a standard 3M2P CMOS process with a 0.5-/spl mu/m feature size.     

Remotely powered addressable UHF RFID integrated system

This paper presents a fully integrated remotely powered and addressable radio frequency identification (RFID) transponder working at 2.45 GHz. The achieved operating range at 4 W effective isotropically radiated power (EIRP) base-station transmit power is 12 m. The integrated circuit (IC) is implemented in a 0.5 /spl mu/m silicon-on-sapphire technology. A state-of-the-art rectifier design achieving 37% of global efficiency is embedded to supply energy to the transponder. The necessary input power to operate the transponder is about 2.7 /spl mu/W. Reader to transponder communication is obtained using on-off keying (OOK) modulation while transponder to reader communication is ensured using the amplitude shift keying (ASK) backscattering modulation technique. Inductive matching between the antenna and the transponder IC is used to further optimize the operating range.     

A 16 DIP, 64 kbit, static MOS-RAM

A 64K/spl times/1 bit fully static MOS-RAM has been fabricated. For the purpose of replacement of 64 kbit dynamic RAM, this static RAM has been designed to be assembled in a standard 300 mil 16 pin DIP. It is the first time address multiplexing has been in static RAMs. The device with multiple addressing and improved row decoder employs a double poly Si layer and a 1.5 /spl mu/m design rule which is achieved by advanced process technology. As a result, the RAM has a 11.0 /spl mu/m/spl times/26.5 /spl mu/m (291.5 /spl mu/m/SUP 2/) cell size and a 3.84 mm/spl times/7.40 mm (28.40 mm/SUP 2/) chip size. The address access time is less than 150 ns with an active power dissipation of 400 mW.     

Micropositioning device using impact force of piezoelectric flying wires

In this paper, a micropositioning device for precision positioning of miniaturized parts is proposed. This device uses piezoelectric flying wires to generate impact forces for actuating a target object to be positioned. The proposed device features two main characteristics: the impact force can actuate a half-tightened object with a high degree of precision, and the thin flying wire is suitable for the actuation of miniaturized object. Fundamental properties of the proposed device were examined experimentally and theoretically based on a basic positioning unit. Furthermore, for the practical application in assembly works, the control system for a three degrees-of-freedom micropositioning device with positioning range of (/spl plusmn/250 /spl mu/m, /spl plusmn/250 /spl mu/m, /spl plusmn/30 mrad) along the X-, Y-, and /spl Theta//sub z/-axes was implemented. The target object (16/spl times/24/spl times/6 mm) was successfully positioned with positioning accuracies of (/spl plusmn/1 /spl mu/m, /spl plusmn/1 /spl mu/m, /spl plusmn/0.2 mrad), based on a derived heuristic control model.     

Compact NMOS building blocks and a methodology for dedicated digital filter applications

Building blocks for digital filters are discussed. They require 0.7 mm/SUP 2/ or 3 mm/SUP 2/ per pole-zero for a dedicated and a partly programmable realization, respectively. They are realized in 6 /spl mu/m NMOS technology, with 16-bit words and working at bit rates up to 10 Mbit/s. With the exclusion of data conversion, scaling will make them competitive with switched capacitor realizations for 3 /spl mu/m technology, in terms of silicon area and speed. These compact results are achieved due to proper minimization in the design. The experience with the above designs is then generalized into a methodology for custom digital filters. An important concern is a hardware-minimization scheme over all design levels (algorithm, bit-serial architecture, and layout style) with efficient IC implementation and performance in mind. It leads to the possibility of an automated design. The design is supported by computer aided design tools for design verification on all levels, and for file management as well as layout. A formal design of a third-order elliptical wave digital filter demonstrates the concept. The resulting chip area is 1.8 mm/SUP 2/ in 6 /spl mu/m NMOS. The simulated maximum bit rate is 5 MHz (corresponding to 312 kHz sampling rate), with a power consumption of 18 mW.     

An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time

An all-digital phase-locked loop (PLL) circuit in which resolution in the phase detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time is presented. The pulse delay circuit is connected in a ring shape with 32 inverters (2/sup 5/ inverters). With the inverter gate-delay time as the time base, the pulse phase difference is detected simultaneously with the generation of the output clock. In this system, the phase detector and oscillator share a single ring-delay-line (RDL). This means the resolution is the same at all times, making a high-speed response possible. In a prototype integrated circuit (IC) using 0.65-/spl mu/m CMOS, the generation of a frequency multiplication clock was achieved with four reference clocks, and that of a phase-locked clock with seven reference clocks, for a high-speed response. The cell size was 1.08 /spl times/ 1.08 mm/sup 2/, and the output clock frequency had a wide range of 50 kHz/spl sim/60 MHz. The multiplication range of the clock frequency was also a very wide 4/spl sim/1022, and a high level of precision was achieved with a clock jitter standard deviation of 234 ps. This digital PLL can withstand a broad range of operating environments, from -30/spl deg/C/spl sim/140/spl deg/C, and is suitable for making a programmable clock generator on a chip.