In-line defect sampling methodology in yield management: anintegrated framework

In this paper we provide an integrated framework for designing the optimal defect sampling strategy for wafer inspection, which is crucial in yield management of state-of-the-art technologies. We present a comprehensive cost-based methodology which allows us to achieve the trade-off between the cost of inspection and the cost of yield impact of the undetected defects. We illustrate the effectiveness of our methodology using data from several leading fablines across the world. We demonstrate that this work has already caused a significant change in the sampling practices in these fablines especially in the area of defect data preprocessing (declustering), in-line defect based yield prediction, and optimization of wafer inspection equipment allocation     

Effects of defect propagation/growth on in-line defect-based yieldprediction

This paper presents the importance of understanding defect propagation/growth and its impact on in-line yield prediction. In order to improve the prediction accuracy, impact of defect propagation and growth phenomena needs to be modeled and incorporated into yield prediction system. We developed a new yield prediction model by taking into account defect carryover. The empirical results of interlayer and intralayer defect propagation analysis using actual fabline data are presented     

Correlation between predicted cause of SRAM failures and in-line defect data

A correlation has been made between the bitmap data from an SRAM and the in-line defect data as measured on a KLA2122 and Tencor7700. The SRAM was a dedicated design for yield enhancement in a 0.35 μm technology. Extra design features were added to encourage the change of having defect on particular places and discourage it on safe designed places. From the failure signature of a memory cell (0 or 1) and its failure extent (single cell, double cell, bitline, wordline (WL), …) one can predict the process-related cause of the failure. A special test program has been written which translates the electrical data from the failing cells into its process defect.The failing bits from the SRAM have been transferred into a KLA results file and added as an extra inspection to the defect database. With a defect source analysis it was possible to find out if the electrical failing bits were seen as a defect in the line and at which steps. With this analysis it is possible to find out if the predicted cause of the process defects from the test program is confirmed by the performed in-line inspections. With an intensive inspection plan about half of the electrical defects were seen in the line. For a large amount of these defects their predicted cause are indeed matching with the inspected layer. Moreover, quite some unknown failures can be explained by the in-line inspections. This correlation work makes it possible to prioritize in tackling the most killing defect sources.     

The impact of tolerance on kill ratio estimation for memory

Spatially correlating in-line inspection data and post process electrical test data is an effective approach for estimating the yield impact of different defect types and/or process steps. An estimator for the probability that a particular type of defect kills an electrically testable structure, the kill ratio, has been described in the literature. This estimator may be used to predict the yield impact immediately after inspection, providing a number of benefits. It may also be used to generate a yield loss pareto by defect type. This paper introduces a new estimator for the kill ratio, which takes into account the impact of tolerance, a parameter setting the maximum distance between a defect and structure under which they are considered spatially correlated. This estimator was developed for memory (bitmap) data, where the tolerance is very large relative to the size of the structure. The tolerance is often increased to accommodate for misalignment between inspection tool sets and the electrical data. The problem with increasing the tolerance is that the chance of coincidental correlation between failed bits and defects increases as the square of tolerance. Analytical and simulation results are presented to illustrate the danger of using the existing kill ratio estimator with too large a tolerance or overly sensitive inspection tool recipes. These same results illustrate the improved performance of the new estimator. Because the number of falsely attributed defects adds up over a number of inspections, a small error in the kill ratio estimator can have a major impact on the yield loss pareto.     

Cross-project software defect prediction based onmulti-source data sets

Cross-project defect prediction (CPDP) uses one or more source projects to build a defect prediction model and applies the model to the target project. There is usually a big difference between the data distribution of the source project and the target project, which makes it difficult to construct an effective defect prediction model. In order to alleviate the problem of negative migration between the source project and the target project in CPDP, this paper proposes an integrated transfer adaptive boosting (TrAdaBoost) algorithm based on multi-source data sets (MSITrA). The algorithm uses an existing two-stage data filtering algorithm to obtain source project data related to the target project from multiple source items, and then uses the integrated TrAdaBoost algorithm proposed in the paper to build a CPDP model. The experimental results of Promise's 15 public data sets show that: 1) The cross-project software defect prediction model proposed in this paper has better performance in all tested CPDP methods; 2) In the within-project software defect prediction (WPDP) experiment, the proposed CPDP method has achieved the better experimental results than the tested WPDP method.     

New tools for yield improvement in integrated circuit manufacturing: can they be applied to reliability?

This paper will start with a discussion of why probe yield (the number of good chips per silicon wafer) is so important to financial success in integrated circuit manufacturing. Actual data will be quoted and a numerical example shown. A simple model will be given to demonstrate the main factors influencing yield and the relationship between yield and reliability of the final product. In the last few years a range of new tools have been deployed in manufacturing, and these have accelerated the pace of yield improvement, thus increasing competitive pressures. These tools will be described, along with examples of their use. Topics will include in-line inspection and control, automatic defect classification and data mining techniques. A proposal is made to extend these tools to the improvement of reliability of products already in manufacturing by maintaining absolute chip identity throughout the entire wafer fabrication, packaging and final testing steps.     

Methods to Quantify the Detection Probability of Killing Defects

Two methods are presented to quantify the killing defect detection probability, or capture rate, of inline defect inspections. The first method uses yield impact and kill ratio of defects above a given size. By comparing the theoretical, critical-area based dependence between the yield impact and the kill ratio of defects above a given size, with the dependence as found from defect–yield correlation on product wafers, an estimate can be made of the fraction of yield impact explained by detected defects. The second method uses conventional defect–yield correlation. By plotting wafer level yield of clean die against the yield impact found by defect–yield correlation, it is possible to estimate the yield impact of undetected defects.     

Extraction of wafer-level defect density distributions to improveyield prediction

Defect density distributions play an important role in process control and yield prediction. To improve yield prediction we present a methodology to extract wafer-level defect density distributions better reflecting such chip-to-chip defect density variations that occur in reality. For that, imaginary wafermaps are generated for a variety of different chip areas to calculate a yield-to-area dependency. Based on these calculations a micro density distribution (MDD) will be determined for each wafer that reflects the degree of defect clustering. The single MDD's per wafer may be summarized to also provide a total defect density distribution per lot or any other sample size. Furthermore, the area needed for defect inspection may be reduced to just a fraction of each wafer which reduces time and costs of data collection and analysis     

An in-line process monitoring method using electron beam induced substrate current

In-line process monitoring technology plays a vital role in accelerating yield ramps and quickly identifying and resolving yield excursions in the system on a chip era. We have developed an in-line process monitoring method that uses electron beam induced substrate current. It is especially suitable for deep contacts and via holes. This method makes it possible to monitor non-destructive contacts and the via-hole formation process with a hole-bottom nm-order SiO₂ film thickness measurement and a hole-bottom diameter measurement. Moreover, it allows us to evaluate etching-process variation over an 8-inch wafer in less than 20 min. The results can be used for in-line device sorting as well as for decisions regarding the timing of etching machine maintenance.     

Efficient macromodeling of defect propagation/growth mechanisms inVLSI fabrication

Particulate contamination deposited on silicon wafers is typically the dominant reason for yield loss in VLSI manufacturing. The transformation of contaminating particles into defects and then electrical faults is a very complex process which depends on the defect location, size, material, and the underlying IC topography. An efficient defect macromodeling methodology based on the rigorous two-dimensional (2-D) topography simulator METROPOLE, has been developed to allow the prediction and correlation of the critical physical parameters (material, size, and location) of contamination in the manufacturing process to device defects. The results for a large number of defect samples simulated using the above approach were compared with the data gathered from the AMD-Sunnyvale fabline. A good match was obtained indicating the accuracy for our method of developing contamination to defect propagation/growth macromodels     

Defect Prediction in Android Binary Executables Using Deep Neural Network

Software defect prediction locates defective code to help developers improve the security of software. However, existing studies on software defect prediction are mostly limited to the source code. Defect prediction for Android binary executables (called apks) has never been explored in previous studies. In this paper, we propose an explorative study of defect prediction in Android apks. We first propose smali2vec, a new approach to generate features that capture the characteristics of smali (decompiled files of apks) files in apks. Smali2vec extracts both token and semantic features of the defective files in apks and such comprehensive features are needed for building accurate prediction models. Then we leverage deep neural network (DNN), which is one of the most common architecture of deep learning networks, to train and build the defect prediction model in order to achieve accuracy. We apply our defect prediction model to more than 90,000 smali files from 50 Android apks and the results show that our model could achieve an AUC (the area under the receiver operating characteristic curve) of 85.98% and it is capable of predicting defects in apks. Furthermore, the DNN is proved to have a better performance than the traditional shallow machine learning algorithms (e.g., support vector machine and naive bayes) used in previous studies. The model has been used in our practical work and helped locate many defective files in apks.     

Modeling of real defect outlines and parameter extraction using acheckerboard test structure to localize defects

For efficient yield prediction and inductive fault analysis, it is usually assumed that defects have the shape of circular discs or squares. Real defects, however, exhibit a great variety of different shapes. This paper presents a more accurate model. The defect outline is approximated by an ellipse, and an equivalent circular defect is determined that causes a fault with the same probability as the real defect. To utilize this model, only the maximum and the minimum extension of detected defects have to be determined. That can be done easily using a novel test structure design. The checkerboard test structure uses the boundary pad frame of standard chips and thus achieves a large defect sensitive area. This area is partitioned into many small regions that can be analyzed separately. Defects are localized by simple electrical measurements. This allows an efficient optical inspection that can provide detailed information about the detected defects     

二次电子显微镜的自动缺陷分类(SEM ADC)新应用-新产品设计转移

随着集成电路工业的快速成长,需在短时间内,引进愈小组件设计且导入量产的时间,愈来愈短.为了新产品能尽早导入量产,产品的缺陷的再检查(review)与分类是必要的,以期提供快速缺陷原因分析,改善良率与生产。在传统的做法中,建立新产品的二次电子显微镜的自动缺陷再检查?自动缺陷分类(SEMADR?ADC)最佳化程序,需时至少1个月,以收集足够的二次电子影像数据库,但是,这已经无法符合集成电路工业产品快速转换的需求,提出一种省时间的(模块程序概念)。这概念使不同产品的相似组成?结构层(layer),不需要额外的二次电子显微镜的自动缺陷再检查?自动缺陷分类(SEMADR?ADC)程序建立时间,利用此方法,台湾力晶半导体φ300mm晶圆厂利用0.15μm的缺陷数据库,成功地在2小时内建立新的0.13μm产品线上二次电子显微镜的自动缺陷再检查?自动缺陷分类(SEMADR?ADC)程序,加速缺陷原因分析与良率提升.     

Capture rate enhance method of 0.1-μm level defects bypattern-matching inspectors

In this paper, a method of enhancing the capture rate of 0.1-μm level defects by pattern-matching inspectors is studied from the viewpoint of image variances. By our method, defect inspection engineers can obtain quantitative information for enhancing the capture rate of 0.1-μm level defects on both actual devices and test element groups (TEGs). The inspection sensitivities were experimentally evaluated by using the detection rate of the defects on an actual device and on the TEG. The image noise and the defect signal of the captured charge-coupled device (CCD) images of the same defect were quantitatively analyzed. The observed image noise and the defect signal obey a normal distribution. The capture rate calculated by our model, based on normal distribution, almost agrees with the experimental data. Next, we propose a new criterion called the “practical rapture rate” by uniting the rapture rate and the false count. The threshold value optimized from the viewpoint of the practical capture rate agrees with empirical thresholds value set by our defect inspection engineers. Finally, as an example of capture rate enhancement, a unique TEG called TWICE (TEG with image contrast enhancing) for photoresist inspection is demonstrated     

Comparison of two wafer inspection methods for particle monitoringon semiconductor manufacturing

The two methods examined differ in the procedure used to select wafers for inspection. In the first, or fixed-policy, method, the same number of wafers is inspected regardless of defect density. In the second method a variable policy is used. It is found that in a superclean production environment these inspection methods are not equivalent in defect density estimation: estimates obtained by the variable policy may be biased, while those obtained with the fixed policy are always unbiased. Fundamental reasons for such a phenomenon are discussed and recommendations are made     

Equivalent circular defect model of real defect outlines in the ICmanufacturing process

For efficient yield prediction and inductive fault analysis of integrated circuits (IC's), it is usually assumed that defects related to photolithography have the shape of circular discs or squares. Real defects, however, exhibit a great variety of shapes. This paper presents an accurate model to characterize those real defects. The defect outline is used in this model to determine an equivalent circular defect such that the probability that the circular defect causes a fault is the same as the probability that the real defect causes a fault, so a norm is available which ran be used to determine the accuracy of a defect model, and thus estimate approximately the error that will be aroused in the prediction of fault probability of a pattern by using circular defect model. Finally, the new model is illustrated with the real defect outlines obtained by optical inspection     

Semi-supervised Software Defect Prediction Using Task-Driven Dictionary Learning

We present a semi-supervised approach for software defect prediction.The proposed method is designed to address the special problematic characteristics of software defect datasets,namely,lack of labeled samples and class-imbalanced data.To alleviate these problems,the proposed method features the following components.Being a semi-supervised approach,it exploits the wealth of unlabeled samples in software systems by evaluating the confidence probability of the predicted labels,for each unlabeled sample.And we propose to jointly optimize the classifier parameters and the dictionary by a task-driven formulation,to ensure that the learned features (sparse code) are optimal for the trained classifier.Finally,during the dictionary learning process we take the different misclassification costs into consideration to improve the prediction performance.Experimental results demonstrate that our method outperforms several representative stateof-the-art defect prediction methods.     

Yield modeling based on in-line scanner defect sizing and acircuit's critical area

Wafers containing a large number of defects on any layer should be discarded in order to avoid the cost associated with processing wafers that are unlikely to yield. Normally decisions about scrapping wafers are based on defect counts. However, including the size of defects can improve the accuracy of such dispositions. If the size of defects is taken into account, critical area provides an estimate of the kill ratio associated with defects of a given size, where the critical area of a layer of a circuit is computed from a circuit's layout. In this paper, the accuracy of the sizing of defects by in-line scanners is analyzed. Then, the impact of defect sizing inaccuracy on estimates of layer yield is discussed, and a methodology to more accurately compute layer yield and kill ratios is presented, which calibrates for inaccuracy in defect sizing by in-line scanners     

基于OMP的SRAM成品率分析的分组建模方法

静态随机存取存储器(SRAM)电路的失效是极小概率事件,并且不同电路条件下的失效区域边界可能相距很远。因此,为了更高效地获得更精准的SRAM成品率预测结果,提出一种基于正交匹配追踪(OMP)算法的SRAM性能分组建模方法,并应用于典型SRAM电路成品率的预测。此方法主要根据不同SRAM电路条件下失效区域边界距离的差异将仿真数据划分为多组,之后利用OMP算法对不同组的数据分别建立多项式模型,该模型可用于对SRAM电路的成品率进行快速分析预测。与标准蒙特卡洛统计算法及基于OMP的单一建模方法相比,基于OMP的分组建模方法不仅可以缩短建模时间,提高建模准确度,还能够获得更加精确的SRAM成品率预测结果。     

Thermomechanical Reliability Study of Flip Chip Solder Bumps: Using Laser Ultrasound Technique and Finite Element Method

Current techniques for nondestructive quality evaluation of solder bumps in electronic packages are either incapable of detecting solder bump cracks, or unsuitable for in-line inspection due to high cost and low throughput. As an alternative, a solder bump inspection system is being developed at Georgia Institute of Technology using laser ultrasound and interferometric techniques . This system uses a pulsed Nd:YAG laser to induce ultrasound in electronic packages in the thermoelastic regime; it then measures the transient out-of-plane displacement responses on the package surfaces using laser interferometric technique. The quality of solder bumps in electronic packages is evaluated by analyzing the transient responses. This paper presents a systematic study on thermomechanical reliability of flip chip solder bumps using laser ultrasound–interferometric inspection technique and finite element (FE) method. The correlation between the failure parameter extracted from FE simulation for evaluating solder bump reliability and quality degradation characterization of solder bumps through noncontact, nondestructive laser ultrasound testing has also been investigated.