平板显示器驱动芯片中NLDMOS寄生电容

功率器件寄生电容的大小直接关系到平板显示器驱动芯片的功耗及性能．本文利用器件的动态电流来分析NLDMOS寄生电容特性．在不影响NLDMOS直流特性的前提下,通过改变鸟嘴位置,得到具有低寄生电容的高性能器件．将该器件应用于平板显示器驱动芯片高低压转换电路,模拟结果证明该电路的自身功耗降低了34%,高压输出对低压控制信号的扰动减小了32%．     

平板显示器驱动芯片中NLDMOS寄生电容

功率器件寄生电容的大小直接关系到平板显示器驱动芯片的功耗及性能.本文利用器件的动态电流来分析NLDMOS寄生电容特性.在不影响NLDMOS直流特性的前提下,通过改变鸟嘴位置,得到具有低寄生电容的高性能器件.将该器件应用于平板显示器驱动芯片高低压转换电路,模拟结果证明该电路的自身功耗降低了34%,高压输出对低压控制信号的扰动减小了32%.     

航空用液晶显示器件环境条件试验报告

液晶显示器件(LCD)是一种新型的平板显示器件。由于它具有驱动电压低、功耗小、寿命长和能被CMOS电路直接驱动等特点,在使用电池作电源的小型数字仪器仪表、汽车仪表、信息终端显示、图象显示中获得了广泛的应用。     

一种MEMS开关驱动电路的设计

静电驱动MEMS开关可靠工作需要较高的驱动电压,大多数射频前端系统很难直接提供,因此需要一种实现电压转换和控制的专用芯片,以满足MEMS开关的实用化需要。本文基于200V SOI CMOS工艺设计的高升压倍数MEMS开关驱动电路,采用低击穿电压的Cockcroft-Walton电荷泵结构,结合特有的Trench工艺使电路的性能大大提高。仿真结果显示驱动电路在5V电源电压、0.2pF电容和1GΩ电阻并联负载下,输出电压达到82.7V,满足大多数MEMS开关对高驱动电压的需要。     

基于ASTLC5301A的TFTLCD栅驱动芯片研究

分析薄膜晶体管液晶显示(TFT-LCD)栅驱动芯片ASTLC5301A的原理,借助Pspice仿真工具进行驱动电路的设计,重点讨论芯片内部高低电平位移转换电路,提出改进型电平接口电路,完成高低压驱动管的尺寸和结构设计。     

基于ASTLC5301A的TFT LCD栅驱动芯片研究

分析薄膜晶体管液晶显示(TFT-LCD)栅驱动芯片ASTLC5301A的原理,借助Pspice仿真工具进行驱动电路的设计,重点讨论芯片内部高低电平位移转换电路,提出改进型电平接口电路,完成高低压驱动管的尺寸和结构设计.     

基于ASTLC5301A的TFT LCD栅驱动芯片研究

分析薄膜晶体管液晶显示（TFT-LCD）栅驱动芯片ASTLC5301A的原理，借助Pspice仿真工具进行驱动电路的设计，重点讨论芯片内部高低电平位移转换电路，提出改进型电平接口电路．完成高低压驱动管的尺寸和结构设计。     

适用于无源超高频RFID标签的高效率整流电路

基于动态阈值补偿技术,提出了一种适用于无源超高频RFID标签的高效率整流电路。该整流电路可以根据MOS管的工作状态对MOS管阈值电压进行动态补偿,使得MOS管同时具有低的导通电压和反向泄漏电流,从而实现高的功率转换效率。采用该整流电路的无源超高频RFID标签芯片在0.18 μm CMOS工艺下设计实现。测试结果表明,在驱动80 kΩ负载时,整流电路的功率转换效率最高可达53.7%。相比于传统整流电路,转换效率提高了约20％。     

一种与双极型模拟电路兼容的低/高压MOS器件

本文介绍一种与双极IC电路技术完全兼容的低压(CMOS)/高压(VDMOS)器件设计与制备工艺。VDMOS器件阈电压:1～2伏(根据注入剂量调节),漏击穿电压大于150伏。V_(GS)=5V时其跨导大于10m(?),导通电阻小于200Ω,最大输出电流约800mA。同时得到的NPN器件其β≥250,BV_(ceo)≥65V,BV_(CBO)≥90V。CMOS器件性能也合乎要求。利用这种工艺可制作任何低压和高压双极/MOS器件,这对于功率集成、高低压转换与驱动、等离子体显示等方面应用会有很多实用价值。     

高可靠、高效率的白光LED高压驱动芯片

根据白光LED(Light Emitting Diode)的特性及其对驱动电路的要求,提出了一种高可靠、高效率的LED高压驱动芯片,具有线性调光和数字调光两种调光功能。芯片采用简化的脉冲宽度调制(PWM,Pulse Width Modulation)峰值电流控制模式控制通过LED的电流,系统稳定性好,抗干扰能力强。振荡器中新型抖频电路模块的加入,提高了系统的电磁干扰(EMI,Electro Magnetic Interference)性能,使系统可靠性进一步增强。驱动芯片的输入电压范围为8.5 V~40V,输出的驱动电压达7.5V,可有效降低NMOS功率开关管的导通损耗。电路设计采用低静态电流、低反馈电压等低功耗设计技术,提高了系统的电能转换效率。芯片采用CSMC公司1μm 40V高压CMOS工艺模型设计,并完成流片。测试结果验证了抖频电路的作用,系统的最高转换效率达到了95.3%。     

Method of dissipating heat generated in high-voltage CMOS driver IC

A method of dissipating the heat generated in a high-voltage CMOS driver IC, which is designed for use with a flat panel display, is proposed. It utilises a charge pump circuit to reduce the voltage across the driver IC when its output stages change their status. It can reduce the power consumption and relieve the thermal problems of driver ICs.     

Low-power CMOS/BiCMOS drivers and receivers for on-chipinterconnects

Novel low-voltage swing CMOS and BiCMOS driver/receiver circuits for low-power VLSI applications are proposed. Interconnect wire drivers with low output signal swing are employed. Special receivers provide single and double level conversion while minimizing the total driver/receiver transmission delay. These level converters have no DC power dissipation. At 3.3 V power supply voltage, the proposed circuits consume less power without delay penalty. The power saving is observed to be as high as 30%. At lower supplies further power and delay improvements are observed     

电压倍增之像素设计

为了节省面板电路驱动芯片的功率损耗以及制作成本,本研究提出一种新的像素电路设计,而在设计中将会融合电荷泵电路。利用这种电路设计的像素可有效地将像素电极上的驱动电压提高到输入电压的2～3倍以上。此像素电路设计具有两个优势:第一,可以有效降低显示面板的像素功率损耗;第二,不需高电压的面板电路驱动芯片,因此可节省芯片的成本及功率损耗。由模拟结果可知,像素电极上的驱动电压确实可由此像素电路设计而提高到输入电压的2～3倍以上;而像素的功率损耗也可有效地降低,约为传统像素的1/2。     

An efficient driving method for a high-voltage CMOS driver IC

An efficient driving method for a high-voltage CMOS driver integrated circuit (IC) is proposed. It utilises an auxiliary circuit to reduce the voltage across the data driver IC when its output stages change their status. The auxiliary circuit can reduce the power consumption and relieve the thermal problems of the driver ICs. Moreover, it has load adaptive characteristics. Power consumption was reduced by 46% at one dot on/off image pattern.     

DB-driver: a low power CMOS bootstrapped differential cross-coupled driver

This paper for the first time reports the design of a high speed and low power differential cross-coupled bootstrapped CMOS driver circuit. The circuit design style, based on the proposed differential cross-coupled bootstrapped driver achieves high performance low core area, and fast full-swing operation, even in spite of the fact that the magnitude of the threshold voltage of the CMOS devices cannot be scaled down with the scaling of the power supply voltage. The proposed driver is implemented on 0.13?µm CMOS technology with a power supply of 1.2?V. It is 34% faster and provides 8% less core area when compared to a base-line circuit using an indirect bootstrap technique. In addition, the proposed driver reduces the power consumption by 35%. The superior performance of the proposed circuit over the other differential cross-coupled bootstrapped CMOS driver circuit, for the applications that require high performance, has been verified with post-layout simulation.     

低压CMOS带隙基准电压源设计

基准源是模拟集成电路中的基本单元之一,它在高精度ADC,DAC,SoC等电路中起着重要作用,基准源的精度直接控制着这些电路的精度。阐述一个基于带隙基准结构的Sub-1 V、低功耗、低温度系数、高电源抑制比的CMOS基准电压源。并基于CSMC 0.5μm Double Poly Mix Process对电路进行了仿真,得到理想的设计结果。     

一种低功耗的锂离子电池保护电路的设计

设计了一种适用于CMOS工艺的锂离子电池充放电保护电路,采用工作在亚阈值区的电路结构,使电路具有超低消耗电流驱动、高精度检测电压等特点。通过取样电路、基准电路和偏置电路设计的改进,保护电路功耗较低并且在较低电压下可以正常工作。模拟结果表明,该电路实现了基本的电池保护功能并在功耗方面达到了设计的目标。     

Abrupt power-off detector for mobile TFT-LCD driver IC using dual power supply

A circuit technique to detect unexpected power conditions such as battery separation is presented. Abrupt power-off owing to unexpected power conditions may cause an abnormal display in mobile TFT-LCDs because an adequate power-off sequence cannot be performed. The proposed abrupt power-off detector (APD) recognises decay of supply voltage and generates a signal to perform a proper power-off sequence. As mobile TFT-LCD driver ICs are usually operated with dual power supply, the APD detects abrupt power-off for both of the power supplies. To demonstrate the feasibility of the APD, a test chip was designed and fabricated in a 30 V/4 /spl mu/m 5 V/0.8 /spl mu/m 2.5 V/0.25 /spl mu/m triple-well CMOS process. Experimental results show that the proposed APD improves display quality by allowing a proper power-off sequence at all abrupt power-off conditions.     

一种低压CMOS LDO稳压电源电路

提出了一种低压CMOS LDO稳压电源电路。与常规CMOS LDO稳压电源电路相比,该电路有两个主要特点:引入了低压带隙基准电路;将带隙基准电路置于串联稳压管后端。通过上述设计,提出的稳压电源电路能在输出电压较低的情况下提供较稳定的输出,同时也能提供稳定的偏置电压及具有较高PSRR的基准输出。对电路进行了仿真,并给出了仿真结果。