基于集成节点的EPON与OBS网络互连的性能分析

以突发接入的模式将EPON接入到OBS网络存在的一系列问题,针对这些问题提出了一种新型边缘集成节点方案.该方案结合三级汇聚机制实现电域和光域的两种突发包的汇聚.通过OPNET仿真平台对直接互连和基于集成节点互连的方案分别进行建模仿真,分析和比较这两种方案的性能.     

基于集成节点的PON与OBS网络互连技术研究

无源光网络(PON)与光突发交换(OBS)网的互连是光分组传送网络发展的必然.文章分析了PON与OBS网互连存在的主要问题及已有的解决方案,提出一种聚合PON与OBS边缘节点功能的集成节点结构,研究基于集成节点的PON与0BS网络互连技术方案,提出基于业务流量的三级汇聚机制,分析结果表明三级汇聚机制可以保证业务等级,减少业务延时.     

基于双面TSV互连技术的超厚硅转接板制备

为了满足异质集成应用中对转接板机械性能方面的需求,提出了一种基于双面硅通孔(TSV)互连技术的超厚硅转接板的制备工艺方案。该方案采用Bosch工艺在转接板正面形成300μm深的TSV,通过结合保型性电镀工艺和底部填充电镀工艺进行TSV填充。在转接板背面工艺中首先通过光刻将双面TSV的重叠部分控制在一个理想的范围内,然后经深反应离子刻蚀(DRIE)工艺形成深度为20μm的TSV并完成绝缘层开窗,最后使用保型性电镀完成TSV互连。通过解决TSV刻蚀中侧壁形貌粗糙、TSV底部金属层过薄和光刻胶显影不洁等关键问题,最终得到了双面互连电阻约为20Ω、厚度约为323μm的硅转接板。     

处理机、微处理机、多机处理系统

0103118并行计算机 I/O 子系统结构分析[刊]/何江//计算机工程与科学.—2000,22(5).—56～60(D)本文分析了并行计算机 I/O 子系统逻辑模型,并从 I/O 子系统物理接口、I/O 子系统分布与互连以及I/O 结点内部结构三方面详细对比、分析了 I/O 子系统的物理实现。参3     

异构型网络互连技术研究

异构型网络互连是许多企事业单位普遍面临的问题。本文从OSI互连模型出发,讨论了网络互连的基本技术,说明了互连设备的特性及其使用方法。最后,提出了几种网络互连方案。     

基于半模基片集成波导的高速数据传输系统

提出了基于半模基片集成波导(HMSIW)互连的高速数据传输系统,并实现了单通道7.5Gbps 的高速数字信号传输。对传统SIW 互连传输系统进行了改进,设计加工了新型HMSIW 波导互连,替换传统SIW 波导互连,使得信道传输带宽和系统传输速率显著提高。在相同主模截止频率条件下,HMSIW 的工作带宽为SIW 的两倍,而其宽度尺寸仅为SIW 的一半。仿真与实测结果显示论文提出的HMSIW 互连传输系统与文献提出的传统SIW 互连传输系统相比,前者的最高传输速率是后者的1.5 倍。     

软件无线电中采样率转换技术的实现及在3G中的应用

目前移动通信标准繁多,且新旧体制混杂,很难做到统一.为了实现互连互通,目前比较可行的方法是采用软件无线电.采样率转换技术是实现互连互通的关键.文中针对第三代移动通信系统(3G)中不同通信体制的带宽、速率要求,根据分级变换的思想,对3G中的CDMA2000和TDSCDMA的采样率转换方案进行了设计,并对3G中的5种制式的采样率转换方案进行了分析比较.实验表明,这一方案可以在采样率变换的高效网络结构基础上进一步降低滤波运算量和存储量.     

基于偏振的大容量紧凑型全光互连系统

作为高可靠性、快速和灵活调制的通信手段 ,全光通信需要实现全光互连。由于自由空间方案充分利用了光学系统固有的二维优势而显得更有竞争力。文中提出一个基于偏振编码 ,适用于动态光互连的方案 ,并给出全连接系统的增长规律。所提出的方案大大降低了互连系统的价格和复杂性 ,具有现实可行性     

基于极化的大容量紧凑型全光互连系统

作为高可靠性、快速和灵活调制的通信手段,全光通信需要实现全光互连。自由空间方案由于充分利用了光学系统固有的二维优势而显得更有竞争力。提出一个基于极化编码,适用于动态光互连的方案,并给出全连接系统的增长规律。所提出的方案大大降低了互连系统的价格和复杂性,具有现实可行性     

硅通孔互连技术的可靠性研究

随着电子封装持续向小型化、高性能的方向发展,基于硅通孔的三维互连技术已经开始应用到闪存、图像传感器的制造中,硅通孔互连技术的可靠性问题越来越受到人们的关注。将硅通孔互连器件组装到PCB基板上,参照JEDEC电子封装可靠性试验的相关标准,通过温度循环试验、跌落试验和三个不同等级的湿度敏感性测试研究了硅通孔互连器件的可靠性。互连器件在温度循环试验和二、三级湿度敏感试验中表现出很好的可靠性,但部分样品在跌落试验和一级湿度敏感性测试中出现了失效。通过切片试验和扫描电子显微镜分析了器件失效机理并讨论了底部填充料对硅通孔互连器件可靠性的影响。     

Analysis and application of a novel model for estimating powerdissipation of optical interconnections as a function of transmissionbit error rate

This paper proposes a novel model for estimating power dissipation of optical/electrical interconnections as a function of transmission bit error rate. This model is applied to a simplified optoelectronic transmitter and receiver configuration in which a photodetector is directly connected to the decision circuit. It is analytically verified that this configuration can achieve error-free operation with low power under practical operating conditions. A comparison between optical and electrical interconnections based on this simplified configuration is performed. This result shows the interconnection length and bit rate at which optical interconnection is superior in terms of power dissipation to electrical interconnection, Only optical interconnections achieve error-free operation with 40 mW power dissipation at a transmission bit rate of 10 Gb/s and an interconnection length over 7 m     

Adaptive Control of Mechanical Systems Using Neural Networks

In this paper, we consider the decentralized adaptive control design problem for uncertain mechanical systems, where uncertainty may arise due to isolated subsystem and/or interconnections among subsystems. Radial basis function neural networks are used to approximate the nonlinear functions to include both dynamic and interconnection uncertainties in each subsystem. The stability of the thus designed control system can be guaranteed by a rigid proof. Finally, a simulation example is given to illustrate the effectiveness of the proposed algorithm.     

Block Diagram Reduction of the Interconnected Linear Time-Varying Systems in the Time-Frequency Domain

The problem of obtaining the time-frequency domain input-output model of a linear time-varying (LTV) system formed by linking the time-frequency domain blocks describing LTV subsystems is considered. Simultaneous input-output transformation of the constituent LTV subsystems modeled in terms of two-dimensional impulse responses into time-frequency domain is developed. It is shown that this transformation gives rise to the time-frequency domain subsystem representation which lends itself easily to: 1) deriving composition rules for obtaining the simplified overall interconnection model, and 2) revealing the constraints on individual subsystem modeling that need to be satisfied to admit such simplification. These composition rules are developed for the reduction of standard topologies including series, parallel, and feedback interconnections. The reduction of a more complicated topology using these rules is demonstrated.     

Application of MoSi/sub 2/ to the Double-Level Interconnections of I/sup 2/L Circuits

A new MoSi/sub 2/-CVD-Al double-level interconnection system is developed to obtain a high packing density in I/sup 2/L circuits. Taking advantage of MoSi/sub 2/, a fine pattern consisting of a Iinewidth of 2.5 /spl mu/m aid a spacing of 1 /spl mu/m is achieved for the first-level interconnections. This new system has a higher reliability than the normaf Al-CVD-Al structure because of the stability of the MoSi2 surface. The fundamental properties of 1/sup2/L gates with MoSi2 interconnections, namely, gain, propagation delay time, and toggle frequency of a T flip-flop, are measured. At practical injector currents, they show nearly the same values as with Al interconnectiorm The resistance effects of MoSi/sub 2/ interconnections are calculated with regard to the unbalance of the injector currents and increase of the propagation delay time. The calculations show that these effects can be ignored at an injector current of 1 /spl mu/A/gate. At higher injector currents, the MoSi/sub 2/ interconnection resistance must be taken into account in I/sup 2/L pattern layout.     

Integrated optical interconnections

The use of optical interconnections between processors, boards, chips, and gates in electronic digital systems to overcome the current performance limitations is described. The advantages of optical interconnections in relation to the interconnection distance, the data capacity, and the interconnection functions are presented. The devices which will support practical implementation of optical interconnections and the integration of optical interconnection devices are discussed. The development of future integrated optoelectronic materials, processing, and fabrication technologies to support integrated optical electronics is also discussed     

Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect

This paper introduces a new coding scheme that simultaneously tackles different design issues of interconnections such as noise, crosstalk and power consumption. The scheme is based on temporal skewing between data words on even and odd lines of an interconnection link, and its hardware implementation is simple and area-efficient. The proposed scheme permits to double the bandwidth of the interconnect while improving its noise tolerance. This is achieved through the simultaneous use of two error detecting techniques: temporal redundancy and parity. Improved noise tolerance property provided by our design enables to decrease the power supply voltage and hence to reduce power consumption of the interconnect.     

Analysis of Transmission Lines on Integrated-Circuit Chips

The availability of very fast semiconductor switching devices and the possibilities of large scale integration have increased the importance of the interconnection problem for the design of high-speed computers. The interconnection delay represents a fundamental boundary which limits the ultimate speed of logic circuits. The transmission-line behavior of interconnections on integrated-circuit chips, especially for subnanosecond applications, is the prime concern of this paper. A lumped circuit model is proposed and justified on physical and experimental grounds. It is shown that interconnections behave like RC transmission lines at low frequencies, with the effect of inductance showing up at midrange and high frequencies. Some simple formulas are included for design use.     

An investigation of solar cell interconnection schemes within CPV modules using a validated temperature‐dependent SPICE network model

In this paper, we present a temperature‐dependent network model of a concentrator photovoltaic (CPV) module. The ability of this network model to calculate different interconnection schemes within CPV modules is validated, and there is good agreement between the measured and calculated data. The model is used to quantify the influence of an inhomogeneous current and of a temperature distribution between the solar cells on the power output of a module. The different interconnection schemes that combine parallel and series connections are compared. The optimal interconnection scheme strongly depends on the variations in the short current densities and temperature differences between the solar cells as well as on the risk of ‘sudden death’ of individual solar cells. Optimal interconnection schemes for several scenarios are developed. A combination of parallel and series interconnections is found to be the most robust interconnection. Copyright © 2012 John Wiley & Sons, Ltd.     

A Three-Dimensional Stacked-Chip Star-Wiring Interconnection for a Digital Noise-Free and Low-Jitter I/O Clock Distribution Network

Cascaded repeaters are indispensable circuit elements in conventional on-chip clock distribution networks due to heavy loss characteristics of on-chip global interconnections. However, cascaded repeaters cause significant jitter and skew problems in clock distribution networks when they are affected by power supply switching noise generated by digital logic blocks located on the same die. In this letter, we present a new three-dimensional (3-D) stacked-chip star-wiring interconnection scheme to make a clock distribution network free from both on-chip and package-level power supply noise coupling. The proposed clock distribution scheme provides an extremely low-jitter and low-skew clock signal by replacing the cascaded repeaters with lossless star-wiring interconnections on a 3-D stacked-chip package. We have demonstrated a 500-MHz input/output (I/O) clock delivery with 34-ps peak-to-peak jitter and a skew of 11ps, while a conventional I/O clock scheme exhibited a 146-ps peak-to-peak jitter and a 177-ps skew in the same power supply noise environment     

商业化电视台的全台网系统建设与应用

本文结合香港潮声卫视全台网项目的整体项目管理,详细介绍了潮声卫视全台网项目的系统架构设计、项目实施概况、系统上线运维等情况,为商业化电视台全台网建设提供了崭新的思路。同时潮声卫视全台网项目的成功实施,在商业化电视台中形成了成熟的设计、实施以及技术运维方案。