Low-voltage operational amplifier with rail-to-rail input and output ranges

An operational amplifier is described which can perform precision signal operations in nearly the full supply voltage range, event when this range is as low as 1.5 V totally. The untrimmed input offset voltage is typically 0.3 mV in an input common-mode (CM) voltage range which extends beyond both supply voltages for about 200 mV. The output voltage can reach each supply rail within 150 mV. A nested-loop frequency-compensation scheme yields a stable unity-gain bandwidth of 0.6 MHz while the low-frequency open-loop voltage gain is 110 dB. The op amp is integrated in a standard low-cost bipolar process and the chip measures 1.5/spl times/1.7 mm/SUP 2/.     

1-V operational amplifier with rail-to-rail input and output ranges

A bipolar operational amplifier (OA) with rail-to-rail input and output ranges which can operate at supply voltages down to 1 V is presented. At this supply voltage, the input offset voltage is typically 1.0 mV in an input common-mode voltage range that extends beyond both supply rails for about 300 mV, with a common-mode rejection ratio (CMRR) between 38 and 100 dB, depending on conditions. The output voltage can reach both supply rails within 100 mV, the output current is limited to ±10 mA, the voltage gain is 100 dB, and the bandwidth is 450 kHz. The die is 2.5×5.5 mm². Qualities such as offset, input-bias current, and CMRR are improved when the supply voltage is increased and the dynamic level shift is autonomically turned off. The OA has been protected against unintentional reversal of the output signal when the inputs are substantially overdriven. The output stage of the circuit consists of two full complementary composite transistors, whose HF characteristics have been improved by internal Miller compensation and linearization of the transconductance     

轨到轨输入输出范围运算放大器的噪声分析和优化

这篇文章设计了一个轨到轨（Rail-to-Rail）输入输出范围的低噪声运算放大器,在输入级采用电流补偿的方法来稳定该运算放大器在整个输入共模范围内的跨导,在输出级使用了AB类的输出方法来提高运算放大器的输出范围,且详细分析了该运算放大器的噪声性能,在此基础上给出了改善该运算放大器噪声性能的方法,以此来提高该运算放大器的动态范围。     

一种高性能Folded-Cascode运算放大器的设计

介绍了一种高性能Foldcd-Cascode运放的电路结构,它具有先进的偏置电源结构以调节输出动态幅度、动态开关电容反馈电路用于控制运放输出端的稳定性、合理地关断电路以降低电路非工作时的功耗等特点.运用HSPICE对电路进行了模拟,并给出了结果.     

A high-performance all-enhancement NMOS operational amplifier

An NMOS operational amplifier has been designed and fabricated using only enhancement mode MOSFETs in a circuit that employs a novel feedforward compensation scheme. Specifications achieved include high open loop gain (2200), low-power (15 mW or less depending on the load), fast settling time (0.1 percent settling time in 3 /spl mu/s for a 4 V input step and a 10 pF load), and small area. While this amplifier uses only a small number of transistors, its performance is comparable to that of recent depletion load amplifiers. Fewer critical steps are needed to fabricate this amplifier, making it attractive for large analog/digital LSI circuits.     

A process-insensitive high-performance NMOS operational amplifier

A new high-performance NMOS operational amplifier is described which has been fabricated using a standard n-channel enhancement-depletion MOS process. A new input stage, employing common-mode feedback, is presented that reduces the circuit's sensitivity to process variations. The compensation of MOS cascade stages is examined and a simple improvement is shown to dramatically reduce the total compensation capacitance. It is shown that the high-performance of this design is maintained for a large variation in depletion device thresholds. Finally, an output stage is described with low quiescent power dissipation and improved driving capabilities.     

一款高性能共源共栅运算放大器设计

基于CSMC 0.5μm标准CMOS工艺,采用复用型折叠式共源共栅结构,设计一种折叠式共源共栅运算放大器。该电路在5V电源电压下驱动5pF负载电容,采用Cadence公司的模拟仿真工具Spectre对电路进行仿真。结果表明,电路开环增益达到了71.7dB,单位增益带宽为52.79MHz,开环相位裕度为60.45°。     

Design of a high-performance PJFET for the input stage of an integrated operational amplifier

With Shockley's approximate-channel theory and TCAD tools, a high-voltage, ultra-shallow junction PJFET for the input stage of an integrated operational amplifier (OPA) was realized. The high-performance PJFET device was developed in the Bi-FET process technology. The measured specifications are as follows. The top-gate junction depth is about 0.1 μm, the gate-leakage current is less than 5 pA, the breakdown voltage is more than 80 V, and the pinch-off voltage is optional between 0.8 and 2.0 V. The device and its Bi-FET process technology were used to design and process a high input-impedance integrated OPA. The measured results show that the OPA has a bias current of less than 50 pA, voltage noise of less than 50 nV/Hz~(1/2), and current noise of less than 0.05 pA/Hz~(1/2).     

一种集成运放输入级用高性能PJFET设计

通过使用肖克莱沟道近似理论和TCAD工具设计了一种可以应用于集成运放输入级的高压超浅结PJFET结构。采用Bi-FET兼容工艺,制作出了顶栅结深约0.1µm,栅漏电小于5pA,击穿电压大于80V,夹断电压在0.8～2.0V范围可调的PJFET。将该类器件及其兼容工艺用于某型号高输入阻抗JFET集成运放的设计与制造,获得了小于50PA的偏置电流,电压噪声小于50nV/Hz1/2,电流噪声小于0.05pA/Hz1/2。     

Current mode instrumentation amplifier with rail-to-rail input and output

This paper presents the results from an investigation on the implementation of Current Mode Instrumentation Amplifiers (CMIAs) with rail-to-rail operational amplifiers (op amp) with a gm control circuit. The objective of employing rail-to-rail op amps in the implementation of a CMIA is the improvement of the common-mode operation range. The enhancement of the input common mode range (ICMR) is obtained using op amps with a rail-to-rail input stage followed by a cascode-based output stage. A prototype of the CMIA was implemented in standard 0.6 μm XFAB CMOS technology. Test results showed that the CMIA common mode range was extended but with moderated CMRR. To minimize this issue the amplifier was re-designed and sent to fabrication. Simulations with the components variations included were performed and showed the enhancement of the CMRR can be expected.     

A rail-to-rail input/output CMOS power amplifier

A rail-to-rail amplifier that maintains a high common-mode rejection ratio (CMRR) over the whole common-mode range and has a low harmonic distortion despite the use of relatively small output devices is discussed. The circuit, which measures only 0.3 mm² in a 3-μm technology, has a quiescent current consumption of 600 μA and a CMRR larger than 55 dB. It handles up to 4 nF, and can, with a 5-V supply, drive 3.8 V_pp into 100 Ω (0.1% total harmonic distortion at 10 kHz)     

Open-loop output characteristics of a current feedback operational amplifier

The output characteristics of the basic current feedback operational amplifier (CFOA) in the linear region, on open-loop, would not appear to have been treated in the literature. This is possibly because it is not straightforward to determine, the problem being that the output saturates without the closed-loop connection. This paper considers a theoretical discussion that explains the results of simulation.     

The macromodel of an operational amplifier with current output

The results of development of the macromodel of an operational amplifier with current output, which is widely used in complex functional blocks of analog-to-digital and digital-to-analog converters, are presented. The main calculated characteristics are presented.     

一种输入输出轨到轨的电流模式仪表放大器设计

本文提出了一种基于标准CMOS工艺的电流模式仪表放大器.该放大器内部运放采用斩波调制技术去除低频1/f噪声和失调,并采用正、负电荷泵,使系统具有轨到轨的输入能力.芯片使用TSMC 0.25μm CMOS混合信号工艺模型设计并流片.测试结果表明,使用60kHz的斩波频率,系统增益为40dB时,具有100dB的共模抑制比和...     

低压工作的轨到轨输入／输出缓冲级放大器

本文提出了一种低压工作的轨到轨输入／输出缓冲级放大器。利用电阻产生的输入共模电平移动,该放大器可以在低于传统轨到轨输入级所限制的最小电压下工作,并在整个输入共模电压范围内获得恒定的输入跨导;它的输出级由电流镜驱动,实现了轨到轨电压输出,具有较强的负载驱动能力。该放大器在CSMCO．6-μmCMOS数模混合工艺下进行了HSPICE仿真和流片测试,结果表明：当供电电压为5V,偏置电流为60uA,负载电容为10pF时,开环增益为87．7dB,功耗为579uw,单位增益带宽为3．3MHz;当该放大器作为缓冲级时,输入3VPP10kHz正弦信号,总谐波失真THD为53．2dB。     

Rail-to-rail BiCMOS operational amplifier using input signal adapters with floating outputs

An operational amplifier with rail-to-rail input and output voltage range in 0.6 μm BiCMOS technology is presented. Two simple input signal adapters with floating outputs serving as pre-stages are introduced. They are followed by a differential amplifier. The adapters translate the input signals into a floating level within the operating region of the differential amplifier, enabling rail-to-rail operation. An inverter-based simple rail-to-rail class AB output stage has been used. With a single supply of 1.5 V, the proposed rail-to-rail operational amplifier achieves 72 dB DC open-loop gain, 2.54 MHz unity-gain frequency, 62° phase margin, 2.5 V/μs slew rate, and 147 μW power consumption.     

一种改进输入级结构的轨至轨运算放大器设计

基于0.18μm CMOS标准工艺设计了一种改进输入级结构的轨至轨运算放大器电路。该电路由输入级电路、共源共栅放大电路、共源输出电路及偏置电路组成。通过引入正反馈的MOS耦合对管将输入级电路改进为预放大电路,然后对其进行了详细分析,利用Cadence软件对电路进行仿真。仿真结果表明本文结构的低频直流开环增益可以达到80 dB,比相同参数下的普通结构高20 dB左右。相位裕度达到73o,共模输入电压范围满足全幅摆动,共模抑制比低频时可以达到107 dB。     

低功耗单端输入差分输出低噪声放大器

该文设计了应用于无线局域网2.4GHz低噪声放大器(LNA),采用了SMIC0.18μm CMOS工艺技术和单端输入差分输出的电路结构.电路同时采用了双支路的电流复用技术,实现了低功耗、低噪声和高增益的性能;通过在输出级增加一级共栅级放大电路,有效地增加了电路的对称性;共源支路串联电感,解决了差分信号相位偏差问题.仿真结果表明,设计的LNA的噪声系数为1.76dB,增益为20.9dB,在1.8V电源电压下,功耗为8.5mW.     

Measurement of EMI induced input offset voltage of an operational amplifier

An efficient measurement technique is introduced for determining the input referred offset voltage induced by electromagnetic interference (EMI) in operational amplifiers.     

Design criteria for multistage microwave amplifier with matchrequirements at input and output

An approach to the design of multistage microwave amplifiers in a prescribed frequency band with requirements about the transducer gain flatness and the maximum magnitude of the reflection coefficient at input and output is presented. The interstage equalizers are designed by imposing a suitable constraint on the maximum transducer gain, obtainable directly from the specifications; the input and output equalizer are obtained by imposing only the matching requirement. The method proposed allows a separate design of each network, which can be performed either through direct optimization or by means of a numerical synthesis