A gallium arsenide SDFL gate array with on-chip RAM

Describes a GaAs gate array with on-chip RAM based on the Schottky diode field-effect transistor logic (SDFL) technology. The array features 432 programmable SDFL cells, 32 programmable interface input-output (I/O) buffers, and four 4/spl times/4 bit static random access memories (RAM) on a 147 mil/spl times/185 mil chip. Each SDFL cell can be programmed as a NOR gate with as many as 8 inputs with a buffered or unbuffered output or as a dual OR-NAND gate with four inputs per side. The interface I/O buffer can be programmed for ECL, TTL, CMOS, and SDFL logic families. Each 4/spl times/4 bit RAM is fully decoded using SDFL circuits (depletion-mode MESFET). Preliminary results demonstrate the feasibility of GaAs SDFL for fast gate array and memory applications.     

一种软件化雷达定时器设计方法

以现场可编程门阵列为平台,提出一种通用定时设计架构,即软件化定时设计方法。它将定时程序划分为软件程序和硬件逻辑两部分,其中硬件逻辑采用定时产生子模块与合成模块实现通用化架构,软件程序为每个子定时配置位置与合成参数,从而实现复杂定时时序的产生。该方法可灵活、快捷调整定时时序,有效提升定时设计与调试效率。     

User-programmable logic-chasing the gate array

Integrated circuits (ICs) come in a wide range of technologies, and can implement a bewildering variety of functions. For the systems builder, however, there is one aspect of an IC that, irrespective of technology or function, is likely to be of overriding importance: whether it can be bought as a standard `off-the-shelf' component, or whether it must be implemented as some form of ASIC (application-specific IC). Here, the author shows that to a degree, the various forms of user-programmable logic, e.g. PLAs (programmable logic array) and PALs (programmable array logic), can offer the best of both worlds, as they are effectively standard parts that can be customised without recourse to a lengthy and expensive factory-based procedure. He shows that due to current advances in semiconductor processing and device architecture, integration levels for user-programmable logic are rising dramatically, attaining levels of functionality that rival low- to medium-complexity gate arrays     

A Full Coverage Test Method for Configurable Logic Blocks in FPGA

FPGA＇s conflgurability makes it difficult for FPGA＇s manufacturers to fully test it. In this paper, a full coverage test method for FPGA＇s Conflgurable logic blocks （CLBs） is proposed, through which all basic logics of FPGA＇s every CLB can be fully tested. Innovative test circuits are designed using FPGA＇s internal resources to build Iterative logic arrays （ILAs） for Look-up tables （LUTs）, distributed random access memories, configurable registers and other logics. The programmable interconnects needed to connect CLBs in these test circuits are also repeatable, making the configuration process much easier and the test speed much faster. The test method is transplantable and independent of FPGA＇s array size, so it can be applied to the test of different FPGAs. Xilinx＇s Virtex FPGA is taken as an example to explain our method, where only 19 test configurations are needed to achieve 100% coverage for all CLBs. To evaluate the test method reliably and guide the process of test vectors generation, a fault simulator- Turbofault is used to simulate FPGA＇s test coverage.     

Estimating Power for FPGAs Based on Signal Probability Theory

Power dissipation has become one of the key optimization conditions in logic design on field programmable gate arrays (FPGAs), thus the power estimation is necessary for logic design optimization. Nowadays, signal activity data created by logic simulation based on test vectors is essential to be used to determine the toggle rate of each signals and blocks in power estimation tools provided by field programmable gate array (FPGA) electronic design automation (EDA) tools. The accuracy of power estimation highly depends on the quality of test vectors, especially, pattern coverage. As probability distribution can describe the uncertainty signals, this work provides an algorithm which can estimate FPGAs power more effectively and accurately by using signal probability distribution rather than test vectors.     

DSP实时图像处理系统

阐述了高速图像目标测量系统的DSP实现,运用了高性能DSP(TMS320C6202)完成实时图像目标处理,研究了一种快速图像匹配的相关跟踪算法,并结合大规模可编程逻辑阵列CPLD进行逻辑控制和现场可编程门阵列FPGA对采集的视频图像做预处理.实验证明该系统性能可靠,跟踪效果较好,并有较高的实时性.     

A programmable image processing system using FPGAs

Real-time image processing usually requires an enormous throughput rate and a huge number of operations. Parallel processing, in the form of specialized hardware, or multiprocessing are therefore indispensable. This piper describes a flexible programmable image processing system using the field programmable gate array (FPGA). The logic cell nature of currently available FPGA is most suitable for performing real-time bit-level image processing operations using the bit-level systolic concept. Here, we propose a novel architecture, the programmable image processing system (PIPS), for the integration of these programmable hardware and digital signal processors (DSPs) to handle the bit-level as well as the arithmetic operations found in many image processing applications. The versatility of the system is demonstrated by the implementation of a 1-D median filter.     

一种高性能并行计算架构的FPGA实现

针对传统的现场可编程门阵列（Field Programmable Gate Array,FPGA）开发方法效率低、不能充分利用芯片逻辑资源等问题,提出了一种高性能并行计算架构。设计了统一的软件、硬件编程模型,并提供FPGA操作系统层级的支持,将部分可重构技术应用于硬件线程的开发,使该架构具备资源管理和复用的能力。同时还设计了软件、硬件协同开发的流程。在开发板ZC702上进行了设计验证,评估了架构的额外资源消耗情况,并以排序算法为例展示了该架构多线程设计的灵活性。     

FPGA在实时图像预处理中的应用

实时图像处理通常需要巨大的数据吞吐量和运算量。因此专用的硬件或者多重处理技术的并行处理很必要。描述了一个基于现场可编程门阵列(FPGA)的灵活的可编程图像处理系统。FPGA特有的逻辑结构单元对实现实时图像处理来说有着先天的优势。在此,我们提出一个通用的实时图像处理模型,并在FPGA上实现了中值滤波算法,从而对采集的实时图像作预处理。     

User-programmable gate arrays

A very flexible gate array that speeds the job of designing, updating, or varying the logic circuitry that turns standard microprocessor and memory ICs into computers and peripheral equipment is examined. The gates on this kind of IC are interconnected under software control, and downloaded into local memory cells from a program written by the user, which can alter it almost at will. The array is manufactured with a grid of interconnections consisting of metal segments and programmable switching points. The user's program defines which switching points are on and which are off, and in this way groups and interconnects the gates into useful functions. On conventional gate-array ICs, the interconnections are made once and for all by the manufacturer using photolithographic masks. Various types of arrays and methods for programming them are described. The approach to designing them is discussed, highlighting differences from the process for factory-configured gate arrays. Some example applications are presented     

基于量子元胞自动机的PLA故障分析和检测

量子元胞自动机(quantum-dot cellular automata,QCA)可编程逻辑阵列(programma-ble logic array,PLA)结构可用于实现大规模可编程逻辑电路。分析了4种故障类型发生在PLA单元的8个区域中的影响,得出了具体的影响效果。其中,直接或间接致使隐含线和与门发生逻辑错误的故障均会导致PLA中故障所在行整行失效,其他故障只会影响故障所在的PLA单元的逻辑功能和配置,而对PLA中的其他单元没有影响。此外,基于故障分析,提出了具体的PLA故障检测方法。     

Antifuse field programmable gate arrays

An antifuse is an electrically programmable two-terminal device with small area and low parasitic resistance and capacitance. Field-programmable gate arrays (FPGAs) using antifuses in a segmented channel routing architecture now offer the digital logic capabilities of an 8000-gate conventional gate array and system speeds of 40-60 MHz. A brief survey of antifuse technologies is provided. the antifuse technology, routing architecture, logic module, design automation, programming, testing and use of ACT antifuse FPGAs are described. Some inherent tradeoffs involving the antifuse characteristics, routing architecture and logic module are illustrated     

A radiation-hardened SOI-based FPGA

A radiation-hardened SRAM-based field programmable gate array VS 1000 is designed and fabricated with a 0.5 μm partial-depletion silicon-on-insulator logic process at the CETC 58th Institute.The new logic cell (LC),with a multi-mode based on 3-input look-up-table (LUT),increases logic density about 12％ compared to a traditional 4-input LUT.The logic block (LB),consisting of 2 LCs,can be used in two functional modes:LUT mode and distributed read access memory mode.The hierarchical routing channel block and switch block can significantly improve the flexibility and routability of the routing resource.The VS1000 uses a CQFP208 package and contains 392 reconfigurable LCs,112 reconfigurable user I/Os and IEEE 1149.1 compatible with boundaryscan logic for testing and programming.The function test results indicate that the hardware and software cooperate successfully and the VS 1000 works correctly.Moreover,the radiation test results indicate that the VS 1000 chip has total dose tolerance of 100 krad(Si),a dose rate survivability of 1.5 × 1011 rad(Si)/s and a neutron fluence immunity of 1 × 1014 n/cm2.     

基于Verilog HDL的ADS8322转换控制器设计

根据项目需求,采用Cyclone II系列EP2C8现场可编程逻辑门阵列（FPGA）作为控制核心,对16位高速模数转换芯片ADS8322进行控制,设计了一种基于Verilog硬件描述语言的ADS8322采样控制逻辑电路,该文详细阐明了ADS8322的特点和工作时序,采用有限状态机,实现了控制器电路的时序逻辑。同时给出采...     

Testing configurable LUT-based FPGA's

We present a new technique for testing field programmable gate arrays (FPGA's) based on look-up tables (LUT's). We consider a generalized structure for the basic FPGA logic element (cell); it includes devices such as LUT's, sequential elements (flip-flops), multiplexers and control circuitry. We use a hybrid fault model for these devices. The model is based on a physical as well as a behavioral characterization. This permits detection of all single faults (either stuck-at or functional) and some multiple faults using repeated FPGA reprogramming. We show that different arrangements of disjoint one-dimensional (l-D) cell arrays with cascaded horizontal connections and common vertical input lines provide a good logic testing regimen. The testing time is independent of the number of cells in the array (C-testability), We define new conditions for C-testability of programmable/reconfigurable arrays. These conditions do not suffer from limited I/O pins. Cell configuration affects the controllability/observability of the iterative array. We apply the approach to various Xilinx FPGA families and compare it to prior work     

Design and Implementation of Embedded Transmission Control Protocol/Internet Protocol Network Based on System-on-programmable Chip

A scheme of transmission control protocol/Internet protocol（TCP/IP） network system based on system-on-programmable chip（SOPC） is proposed for the embedded network communication. In this system, Nios processor, Ethernet controller and other peripheral logic circuits are all integrated on a Stratix Ⅱ field programmable gate array （FPGA） chip by using SOPC builder design software. And the network communication is realized by transplanting MicroC/OS Ⅱ （uC/OS Ⅱ ） operation system and light weight Internet protocol（LwIP）. The design idea, key points and the structures of both software and hardware of the system are presented and ran with a telecommunication example. The experiment shows that the embedded TCP/IP network system has high reliability and real-time performance.     

FPGA在航天遥感器中的应用

现场可编程门阵列（Field programmable gatearray,FPGA）是一种可编程逻辑器件,设计方便、便于修改、功能便于扩展,极大地提高了电子系统设计的灵活性和通用性,被广泛地应用在通信、航空航天和汽车电子等诸多领域。本文分析FPGA结构原理的同时,对FPGA在航天及空间电子系统中的应用进行了总结。指出了航天应用对FPGA的可靠性要求,对相关可靠性设计技术进行了总结,并对航天应用FPGA及其可靠性设计技术的发展进行了展望。     

New Non-Volatile Memory Structures for FPGA Architectures

A new set of programmable elements (PEs) using a new non-volatile device for use with routing switches and logical elements within a field-programmable gate array (FPGA) is described. The PEs have small area, can be combined with components that use low operational voltage on the same CMOS logic process, are non-volatile, enable the use of fast thin-oxide pass transistors, and are reprogrammable. A novel non-volatile flip-flop for use within the logical elements is presented as well. In combination, these methods enable programmable logic devices with improved area efficiency, the speed advantages of SRAM-based FPGAs, and a wide range of opportunities for power down strategies.     

Optimised bit serial modular multiplier for implementation on fieldprogrammable gate arrays

A high-speed architecture for bit serial modular multiplication is presented. The design of this array is highly regular, allowing the specific logic and routing resources available in field programmable gate arrays (FPGAs) to be exploited. Furthermore, an optimised array is presented which exploits the reprogrammability of the FPGA, such that a longer bit length can be implemented on the same FPGA