A new nonlinear time-domain op-amp macromodel using thresholdfunctions and digitally controlled network elements

A general-purpose nonlinear macromodel for the time-domain simulation of integrated circuit operational amplifiers (op amps), either bipolar or MOS, is presented. Three main differences exist between the macromodel and those previously reported in the literature for the time domain. First, all the op-amp nonlinearities are simulated using threshold elements and digital components, thus making them well suited for a mixed electrical/logical simulator. Secondly, the macromodel exhibits a superior performance in those cases where the op amp is driven by a large signal. Finally, the macromodel is advantageous in terms of CPU time. Several examples are included illustrating all of these advantages. The main application of this macromodel is for the accurate simulation of the analog part of a combined analog/digital integrated circuit     

A macromodel for integrated all-MOS operational amplifiers

A macromodel for integrated all-MOS operational amplifiers is developed with reference to circuits where the settling behavior of the op amps is of particular concern. Expressions for the values of the elements of the macromodel are obtained from typical measured characteristics. It is shown that the proposed macromodel can satisfactorily predict both small-signal and large-signal behavior of the op amps.     

A dual current feedback op amp in CMOS technology

A CMOS circuit configuration implementing a current feedback or transimpedance op amp (CFB op amp) is presented. The architecture of the circuit is derived from similar bipolar CFB op amps. The properties of the CMOS implementation are similar to those of its bipolar counterparts, i.e., a high slew rate and a bandwidth which is independent of the closed-loop gain when the op amp is used with current feedback. Further, it is shown how two CFB op amps can be connected to achieve a non-slew-rate-limited voltage-mode op amp.     

High-frequency active filter design using monolithic nullors

A monolithic building block suitable for high-frequency RC active filter implementation is described. The transconductance-type device is fabricated using standard bipolar technology, and its performance is shown to be superior to corresponding voltage operational amplifiers (op amps) at frequencies above 20 kHz. It is also shown that high quality simulated inductance and frequency dependent negative resistance elements can be implemented at higher frequencies than is possible using standard bipolar op amps.     

A multiplexed switched capacitor filter bank

A technique is introduced which allows several integrator capacitors to be multiplexed onto a single operational amplifier. As a result, the op amp can be shared by several switched capacitor filter channels, drastically reducing the number of op amps required for filter banks. Twenty second-order filters have been implemented in a circuit using only two op amps and 2.5 mm/SUP 2/. The design of this system is presented and its performance is discussed. Some loss of signal energy is shown to occur during the multiplexing operations, which reduces filter Q. Causes of this charge loss are described, and its effects on performance are modeled. The design of the op amp used is presented, which incorporates a new system of input stage biasing and differential to single-ended conversion, as well as other features.     

Changing technology-banish the 741! [op amp]

Pick up a current electronics text and you're likely to find the 741 op amp not only used, but also showcased. It's the op amp of choice for lab experiments, treatment of innards, etc. This is truly amazing when you consider that the 741 is nearly 30 years old! Of course op amps should be presented they can be used to implement a remarkable range of circuit functions. An inexpensive op amp can give near-ideal performance in certain practical applications. Getting something to work is infectious-the first op amps gave a whole generation the opportunity to build analog functions that really worked. But, like all technologies, op amp development never ceased; there have been some serious developments over the last 30 years!     

A high precision micropower operational amplifier

An operational amplifier configuration implemented as a true micropower high precision op amp is described. It includes a well controlled and predictable DC biasing network that is insensitive to variations in temperature, supply voltages, and process. Also, it permits single supply operation. Excellent DC precision characteristics, comparable to or better than the very best precision op amps currently available, are realized yet at micropower levels. By simply increasing the biasing currents, a version of this design operates in general purpose applications without any degradation in its high precision characteristics. Thus, the AC performance levels of general purpose op amps are attained at a fraction of supply current. This device is fabricated using a standard bipolar IC process; an ion-implanted JFET is added to simplify biasing.     

Design for testability of embedded integrated operationalamplifiers

The operational amplifier (op amp) is one of the most encountered analog building blocks. In this paper, the problem of testing an integrated op amp is treated. A new low-cost vectorless test solution, known as oscillation test, is investigated to test the op amp. During the test mode, the op amps are converted to a circuit that oscillates and the oscillation frequency is evaluated to monitor faults. The tolerance band of the oscillation frequency is determined using a Monte Carlo analysis taking into account the nominal tolerance of all important technology and design parameters. Faults in the op amps under test which cause the oscillation frequency to exit the tolerance band can therefore be detected. Some Design for Testability (DfT) rules to rearrange op amps to form oscillators are presented and the related practical problems and limitations are discussed. The oscillation frequency can be easily and precisely evaluated using pure digital circuitry. The simulation and practical implementation results confirm that the presented techniques ensure a high fault coverage with a low area overhead     

一种折叠共源共栅运算放大器的设计

折叠共源共栅运放结构的运算放大器可以使设计者优化二阶性能指标,这一点在传统的两级运算放大器中是不可能的。特别是共源共栅技术对提高增益、增加PSRR值和在输出端允许自补偿是有很用的。这种灵活性允许在CMOS工艺中发展高性能无缓冲运算放大器。目前,这样的放大器已被广泛用于无线电通信的集成电路中。介绍了一种折叠共源共栅的运算放大器,采用TSMC 0.18混合信号双阱CMOS工艺库,用HSpice W 2005.03进行设计仿真,最后与设计指标进行比较。     

A computer modeling approach for LSI digital structures

The paper presents a novel modeling approach to LSI MOST circuits performed at the gate level. A macromodel is analytically derived and provides a direct relationship between the input function and output response of the gate. This approach or macromodeling has been implemented for over 10 000 devices in LSI with only 32K of computer core and very fast computing time. The method employed relates directly the performance parameters (e.g., turn-on voltage, rise, and fall times, etc.) to the device parameters. An insight into the propagation delay of LSI structures is gained by statistically studying the transient performance of the system using Monte-Carlo techniques. Experimental results give ample evidence of good agreement with the computed results, for which various values of x0, oxide thickness, are used.     

Computer-Aided Analysis of RFI Effects in Operational Amplifiers

The modified Ebers-Moll model is used to predict RFI effects in the 741 operational amplifier (op amp)-a bipolar linear integrated circuit (IC). RFI susceptibility predictions for RF incident upon the op-amp input terminals are made using a complete model, a macromodel, and a voltage-offset model. Both the batch-mode computer program SPICE 2 and the commercial interactive computer program ISPICE are used. The three sets of calculated results are essentially identical and agree within 4 dB with experimental results measured at 220 MHz. A threshold cannot be given for the RF power level at which a 741 op amp is susceptible to RFI. The level depends upon the op-amp circuit application. For op-amp circuits designed to amplify input signals in the 0.1-to 1.0-V range, RF power levels as large as -15 to + 5 dBm may be required to cause RHI susceptibility problems. For op-amp circuits designed to amplify input signals in the 1-to 10-mV range, RF power levels as low as -55 to -35 dBm may cause RHI susceptibility problems.     

High performance op amps in a 40V BiCMOS process and their applications

This paper describes the design of three high-performance op amps in a 40V BiCMOS technology. The first circuit is a low-noise op amp with MOS inputs. A thermal noise level as low as with a 1/f noise corner frequency of 100 Hz is achieved. For applications that can tolerate a lower input impedance, a more economical bipolar input low-noise op amp has been designed, yielding an even better noise performance for source impedances up to 20 k. The third circuit is an internally compensated high-gain-bandwidth (GBW=15 MHz) op amp that can drive loads from 0 to 20 pF. A fourth-order low-pass switched-capacitor filter making use of the latter op amp is discussed next. Finally the applications of this 40V BiCMOS process are illustrated.     

A high-performance full-wave rectifier circuit

A new circuit that enables basic operational amplifiers (op amps) such as the LM741 to produce precise full-wave rectification for frequencies up to and exceeding 100 kHz without waveform distortion is presented. The circuit is based on a standard op amp precise rectifier that is modified by the inclusion of a current conveyor to improve the rectifying process.     

An integrated injection logic (I/SUP 2/L) macromodel including lateral and current redistribution effects

An integrated logic (I/SUP 2/L) macromodel for computer simulation of logical configurations of I/SUP 2/L gates is presented. The macromodel is synthesized from the familiar Ebers-Moll equivalent circuit which permits compatibility with numerous presently available circuit simulators. Measurement procedures are described for the complete and self-consistent set of electrical parameters required for macromodel definition. A five-stage ring oscillator is computer simulated to demonstrate the application of the macromodel. Lateral current transfer (LCT) between adjacent gates and injector current redistribution (ICR) effects are shown to reduce gate propagation delay times. When both effects are included, the macromodel produces an agreement between computer simulated and experimental results of better than 10 percent. A ring oscillator example illustrates the use of the macromodel to provide physical insight into the layout sensitivity of I/SUP 2/L.     

Compact High Gain CMOS Op Amp Design using Comparators

This paper discusses the design of high gain, general purpose op amps. The op amp is based on a novel cascaded design using comparators and with structural simplicity approaching that of digital circuits. Ideally, the design tool presented here can be used to optimize gain and CMRR independent of the other op amp performance parameters. The designed op amp has 140 dB open-loop gain and 43 MHz unity gain frequency (GBW) in Berkeley Spice3f Level-2 simulation. The circuit is implemented using a 2.0 m nwell CMOS process through MOSIS. The op amp is self-biased and requires only power supplies of ±2.5 V. It occupies an area of 113 m×474 m.     

A high-swing 2-V CMOS operational amplifier with replica-amp gainenhancement

A general gain-enhancement technique for operational amplifiers using a replica amplifier is described. Unlike conventional techniques such as cascoding, which increases the gain by increasing the output resistance, the replica-amp technique increase the gain by matching the main and the replica amps. Among the advantages of the replica-amp technique are low supply, high swing, and effectiveness with resistive loads. This technique has been demonstrated in a 1.2-μm CMOS two-stage op amp. Operating from ±1-V supplies, the op amp has an effective open-loop dc gain of greater than 10 000, while maintaining a high swing of 100 mV from either supply rails. The gain-enhancement circuit is shown to have only a small effect on the settling time experimentally, analytically, and in SPICE simulation     

Design, fabrication, and performance of scaled analog ICs

This paper concerns scaled MOS circuits for high-speed and high-density analog LSIs. The effect of scaling the devices employing three different scaling laws (constant electric field, constant voltage, and quasiconstant voltage laws) is examined using both the first-order approximation and two-dimensional device simulator. Versatile scaling relationships for analog circuits are then developed. They show that the bandwidth, transient response, and low-frequency gain are generally improved; however, the signal-to-noise ratio (S/N) is reduced by a scaling factor of k/SUP 0.5/ or k depending on which scaling law is used. To further investigate the scaling effects, scaled NMOS op amps are developed based mainly on the quasi-constant voltage law with k of approximately 2 and 3 compared to the conventional 8.5 /spl mu/m rule NMOS op amp. Improvements in slew rates and gain-bandwidth products are more than sixfold while keeping the low-frequency open-loop gain, power dissipation, and S/N almost unchanged.     

全集成精确连续时间六阶低通滤波器的谐波计算机分析

本文利用通用电路模拟程序SPICE-Ⅱ,分别在运放理想情况下和运放不理想情况下,对一个六阶切比雪夫滤波器MOSFET-C平衡结构进行了仿真分析,并与原分立元件构成的滤波器特性进行了比较。     

A convex macromodeling of dynamic comparator for analog circuit synthesis

Equation-based circuit optimization using geometric programming (GP) is a promising analog and mixed-signal design framework that is inherently capable of hierarchical design synthesis. By taking a dynamic comparator as a test vehicle, this paper presents a reduced-complexity cell-level macromodeling method compatible with equation-based circuit optimization using GP. A key contribution of this paper is the demonstration of the complexity-reduction method in creating a convex, empirical, and cell-level macromodel. The variable space reduction is guided by the 1st-order modeling obtained from fundamental understandings on the circuit behavior. The proposed modeling is ideally applicable to create a macromodel exhibiting nonlinear behaviors in time-domain, which are not readily captured in a traditional equation-based modeling approach. The numerical experiment using a dynamic comparator in 0.13 μm CMOS process as a test vehicle indicates that the modeling errors for major performance metrics are less than 5 %, while obtained Pareto-front tradeoff provides useful design guidelines on the architecture-level design exploration.     

Extending the bandwidth of an instrumentation amplifier

A new configuration for operational amplifier based instrumentation amplifier is presented. The analytical expressions are obtained and the performance of the proposed circuit is examined in relation to the conventional circuit. Simulation and experimental results are presented which establish the superiority of the proposed instrumentation amplifier topology over the conventional circuit. The effect of second pole of op amps on the circuit stability has also been investigated. Numerical results are given in support of theoretical conclusions.