Drastic reduction of gate leakage in InAlAs/InGaAs HEMT's using apseudomorphic InAlAs hole barrier layer

Impact ionization in the channel of InAlAs/InGaAs HEMT's was shown to be a reason for excess gate leakage current. Hot electrons in the high field region of the channel under the gate generate electron-hole pairs. The generated holes can reach the gate (gate leakage) as well as the source, the electrons flow to the drain (kink effect). The number of holes reaching the gate strongly depends on the valence band discontinuity. In order to increase this valence band discontinuity a thin pseudomorphic InAlAs layer with high Al-content was inserted in the spacer of an InAlAs/InGaAs HEMT. The efficiency of this hole barrier was measured by photocurrent and DC measurements, while its influence on transport characteristics was measured by Hall and RF measurements. A reduction of gate leakage by a factor of 200 is demonstrated     

Impact ionization in InAlAs/InGaAs/InAlAs HEMT's

The kink effect and excess gate current in InAlAs/InGaAs/InAlAs HEMT's have been linked to impact ionization in the high field region of the channel. In this letter, a relationship is established between experimentally measured excess gate current and the tunneling of holes from the quantum well formed in the channel. The channel hole current is then obtained as the quotient of the excess gate current to the gate-voltage-dependent transmission probability. This channel hole current follows the exponential dependence of the ionization constant on the inverse electric field     

Impact of recess-etching-assisting resist-openings on the shapes ofgate grooves for short gate length InAlAs/InGaAs heterojunction FET's

When resist openings are employed to monitor the drain current of InAlAs/InGaAs-heterojunction-based FET's during wet-chemical gate recess, etching rates for InGaAs and InAlAs can be significantly modified by the exposure of the surface metal on the nonalloyed ohmic electrodes to citric-acid-based etchants. Surface metal of Ni enhances the recess etching rate to a degree that is much higher than that in its absence. With nonselective citric acid-based etchant, the presence of Pt surface metal, however, leads to a preferential etching of InGaAs over InAlAs. This behavior of selective etching is attributed to the excess oxidation of InAlAs induced by the high electrode potential of Pt via electrochemical effects. This investigation discloses that the selection of the surface metal that lies beneath the resist openings can be very important if gate recess grooves with desired shapes are to be fabricated     

InGaAs/InAlAs HEMT with a strained InGaP Schottky contact layer

The authors have fabricated an InGaAs/InAlAs HEMT structure with a strained InGaP Schottky contact layer to achieve selective wet gate recess etching and to improve reliability for thermal stress. Strained In_0.75Ga_0.25P grown on InAlAs has been revealed to have sufficient Schottky barrier height for use as a gate contact. Threshold voltage standard deviation has been reduced to one fifth that of a conventional InGaAs/InAlAs HEMT, as a result of successful selective recess etching. After thermal treatment at 300°C for 5 min, the drain current and transconductance did not change, while those of the conventional HEMT decreased by more than 10%     

Impact ionization in InAlAs/InGaAs HFET's

The presence of an energy barrier to the transfer of holes from the channel to the gate electrode of InAlAs/InGaAs HFET's prevents the gate current from being a reliable indicator of impact ionization. Consequently, we have used a specially designed sidegate structure to demonstrate that due to the narrow bandgap of InGaAs, impact ionization takes place in the channel of these devices under normal operating conditions. The ionization coefficient was found to follow a classic exponential dependence on the inverse electric field at the drain end of the gate, for over three orders of magnitude     

Low frequency noise sources in InAlAs/InGaAs MODFETs

Detailed analysis of the 1/f low-frequency noise (LFN) in In/sub 0.52/Al/sub 0.48/As/InGaAs MODFET structures is performed, for low drain bias (below pinch-off voltage), in order to identify the physical origin and the location of the noise sources responsible for drain current fluctuations in the frequency range 0.1 Hz-10/sup 5/ Hz. Experimental data were analyzed with the support of a general modeling of the 1/f LFN induced by traps distributed within the different layers and interfaces which constitute the heterostructures. Comparative noise measurements are performed on a variety of structures with different barrier (InAIAs, InP) and different channel (InGaAs lattice matched to InP, strained InGaAs, InP) materials. It is concluded that the dominant low frequency noise sources of InAlAs/InGaAs MODFET transistors in the ON state are generated by deep traps distributed within the "bulk" InAlAs barrier and buffer layers. For reverse gate bias, the gate current appears to be the dominant contribution to the channel LFN, whereas both the gate current and the drain and source ohmic contacts are the dominant sources of noise when the device is biased strongly in the ON state. Heterojunction FET's on InP substrate with InP barrier and buffer layers show significantly lower LFN and appear to be more suitable for applications such as nonlinear circuits that have noise upconversion.     

MOVPE grown InAlAs/InGaAs/InP MODFETs with very high f/sub T/

High-performance 0.15 mu m gate length modulation-doped field-effect transistors (MODFETs) have been fabricated on a lattice-matched InAlAs/InGaAs heterostructure grown by organic vapour phase epitaxy (MOVPE). Excellent 'kink-free' DC characteristics with extrinsic transconductance g/sub m/ of 1080 mS/mm at a drain current of 508 mA/mm have been achieved. A unity current-gain cutoff frequency f/sub T/ of 187 GHz at room temperature has been measured, which is the highest value reported for MOVPE-grown lattice-matched InAlAs/InGaAs MODFETs.<>     

High performance double-doped InAlAs/InGaAs/InP heterojunction FET with potential for millimetre-wave power applications

Lattice matched InAlAs/InGaAs/InP heterojunction field-effect transistors (HJFETs), which have carrier supplying layers on and beneath the undoped InGaAs channel layer, have been successfully fabricated. A selective recess of the InGaAs channel edge at a mesa sidewall together with the use of a wide recess gate structure leads to a 5.7 V gate-drain breakdown voltage without kink effects. The fabricated HJFET with a 0.15*100 mu m/sup 2/ T-shaped gate exhibits a 700 mA/mm maximum drain current, a voltage gain of 14, and a 345 GHz maximum frequency of oscillation.<>     

Striped-channel InAlAs/InGaAs HEMTs with shallow-grating structures

Striped-channel (SC) InAlAs/InGaAs HEMTs have been demonstrated with shallow gratings. The shallow grating structure keeps the gate from touching the channel layer and thus solves the gate leakage problem observed in the deep grating devices on InP substrates. Various channel widths have been realized to study the impact of the channel width on the dc and microwave performance. Due to the enhanced charge control in the SC HEMTs, enhanced transconductance/source-drain current (G_m /I_ds) and transconductance/output conductance (G_m /G_ds) were observed. Compared with conventional HEMTs, the SC HEMTs showed degraded f_T due to additional parasitic capacitances and improved f_max due to better carrier confinement     

High electrical performance liquid-phase HBr oxidation gate insulator of InAlAs/InGaAs metamorphic MOS-mHEMT

The InAlAs/InGaAs metal-oxide-semiconductor metamorphic high electron mobility transistors (MOS-mHEMTs) were demonstrated by using liquid-phase HBr treatment technology to form a high-quality gate insulator layer. In this study, liquid-phase HBr treatment technology was used instead of traditional plasma-assisted chemical vapor deposition (PECVD) because the proposed technology can prevent the device from plasma-induced damage. The novel HBr + ultraviolet (UV) illumination treated InGaAs provided a lower surface states such that MOS structure can be efficiently obtained. Besides, based on the atomic force microscopy (AFM) measurement, the native oxides film formed by HBr + UV illumination treatment also provided a better surface roughness compared to traditional NH₄OH and only HBr treatment solutions. It is beneficial for reducing the surface traps and lowering the leakage current in MOS-mHEMTs. Based on the flicker noise and load-pull power measurement results, HBr + UV treatment mHEMT achieved a low flicker noise at high current level and the power-added efficiency can be enhanced up to 9%. Therefore, the novel liquid phase method of HBr + UV illumination treatment exhibited a highly potential for low noise microwave power device applications.     

Damage-free passivation of InAlAs/InGaAs HFETs by use of ECR-deposited SiN

Silicon nitride deposited by electron-cyclotron resonance has been used to fully passivate InAlAs/InGaAs HFETs. The passivation process did not increase the gate leakage current, and passivated 1 mu m HFETs had a breakdown voltage of 15 V. These results illustrate the potential of ECR nitride for passivation of InP-based semiconductor devices.<>     

A novel InGaAs/InAlAs insulated gate pseudomorphic HEMT with asilicon interface control layer showing high DC- and RF-performance

A novel InGaAs/InAlAs insulated gate pseudomorphic HEMT (IG-PHEMT) utilizing a silicon interface control layer (Si ICL) was successfully fabricated and its DC and RF performances were characterized. The device showed high transconductance of 177 mS/mm even for a gate length of 1.6 μm. As compared with the conventional Schottky gate PHEMTs, the gate leakage current was reduced by 4 orders of magnitudes and the gate breakdown voltage was increased up to 39 V. Well-behaved RF characteristics with the current gain cutoff frequency, f_T, of 9 GHz and the maximum oscillation frequency, f_max, of 38 GHz were obtained for the 1.6 μm-gate-length device     

Monolithically integrated long wavelength optical receiver OEICs using InAlAs/InGaAs heterojunction MESFETs (HFETs)

Monolithic optical receiver OEICs have been successfully fabricated on 2" diameter InP substrates by integrating an InGaAs pin photodetector with a simple InAlAs/InGaAs heterojunction MESFET (HFET) structure. Transimpedance receivers based on 1.5 mu m gate length FETs exhibited 3.5 GHz bandwidth and 19.9 pA/ square root (Hz) averaged noise current. Circuit functional yield as high as 67% has been achieved.<>     

Electrochemically induced asymmetrical etching in InAlAs/InGaAs heterostructures for MODFET gate-groove fabrication

We have achieved a self-controlled asymmetrical etching in metalorganic chemical vapor deposition-grown InAlAs/InGaAs heterostructures, which can be suitable for fabricating modulation-doped field-effect transistors (MODFETs) with gate-groove profiles for improved performance. The technology is based on electrochemical etching phenomena, which can be effectively controlled by using different surface metals for ohmic electrodes. When surface metals of Pt and Ni are deposited on the source and the drain, respectively, the higher electrode potential of Pt results in slower etching on the source side than on the drain side. Thus, asymmetry of gate grooves can be formed by wet-chemical etching with citric-acid-based etchant. This represents a new possibility to conduct “recess engineering” for InAlAs/InGaAs MODFETs.     

Low-conductance drain (LCD) design of InAlAs/InGaAs/InP HEMT's

The concepts of the low-conductance drain (LCD) design approach for lattice-matched InAlAs/InGaAs/InP HEMTs are demonstrated for improved device performance. The tradeoff for LCD HEMT characteristics is a tapered current gain cutoff frequency f_t under high drain-to-source bias. This behavior is, in principle, due to the fact that the LCD approach increases the effective gate length of the HEMTs in exchange for reduced peak channel electric field. Two-dimensional PISCES simulation was used to optimize the improvements while simultaneously minimizing this undesirable effect for an LCD HEMT structure     

GaAs基InAlAs/InGaAsMHEMT直流特性研究

报道了用 MBE技术生长的 Ga As基 In Al As/In Ga As改变结构高电子迁移率晶体管 (MHEMT)的制作过程和器件的直流性能。对于栅长为 0 .8μm的器件 ,最大非本征跨导和饱和电流密度分别为 3 5 0 m S/mm和1 90 m A/mm。源漏击穿电压和栅反向击穿电压分别为 4V和 7.5 V。这些直流特性超过了相同的材料和工艺条件下 Ga As基 PHEMT的水平 ,与 In P基 In Al As/In Ga As HEMT的性能相当     

Delta-doping-enhanced InGaAs/InAlAs heterobarrier diodes

Modification of the effective conduction-band offset in InGaAs/InAlAs isotype heterojunctions by incorporating, during epitaxial growth, a doping dipole formed by alternate n⁺, p⁺ delta (δ-) doping is demonstrated. Greatly improved current rectification is found when the dipole polarity enhances the potential barrier     

High-speed InAlAs/InGaAs heterojunction bipolar transistors

InAlAs/InGaAs heterojunction bipolar transistors fabricated from wafers grown by molecular beam epitaxy are discussed. A cutoff frequency of 32 GHz for a collector current of 20 mA is achieved in the emitter area of devices 6×10 μm². The use of heavily doped and nondoped InGaAs layers as the emitter cap and collector, respectively, results in a reduction of the emitter and collector charging times; this, in turn, leads to improved microwave performance     

The importance of electrochemistry-related etching in thegate-groove fabrication for InAlAs/InGaAs HFETs

For the first time, the surface metal on nonalloyed ohmic electrodes is found to significantly change the profiles of gate grooves, when resist openings are employed to monitor drain current during wet-chemical gate recess for sub-micron InAlAs/lnGaAs heterojunction field-effect transistors (HFETs). The surface metal of Ni enhances the etching rate in comparison with that in the absence of electrodes by a factor of 4 and 10, laterally and vertically, which is favorable to fabricate deep gate grooves with small side etching. The Pt surface metal, however, leads to preferential etching of InGaAs over InAlAs, which can be useful to realize large side etching. The existence of an electrochemistry-related etching component, which arises when the ohmic electrodes are present during recess etching, is considered to be responsible for these behaviors     

InAlAs/InGaAs/InP MODFET's with uniform threshold voltage obtainedby selective wet gate recess

Excellent uniformity in the threshold voltage, transconductance, and current-gain cutoff frequency of InAlAs/InGaAs/InP MODFETs has been achieved using a selective wet gate recess process. An etch rate ratio of 25 was achieved for InGaAs over InAlAs using a 1:1 citric acid:H₂O₂ solution. By using this solution for gate recessing, the authors have achieved a threshold voltage standard deviation of 15 mV and a transconductance standard deviation of 15 mS/mm for devices across a quarter of a 2-in-diameter wafer. The average threshold voltage, transconductance, and current-gain cutoff frequency of 1.0-μm gate-length devices were -234 mV, 355 mS/mm, and 32 GHz, respectively