A New Inductor Series-Peaking Technique for Bandwidth Enhancement of CMOS Current-Mode Circuits

This paper introduces a new inductor series-peaking technique for bandwidth enhancement of low-voltage CMOS current-mode circuits. The peaking inductor is in series with the capacitor constituting the dominant pole. It boosts the bandwidth by utilizing the resonance characteristics of LC networks. To reduce the value of the peaking inductor, a new negative current-current feedback mechanism is proposed. The employment of both inductive peaking and current feedback further increases the bandwidth. Both the inductor series-peaking and the current-current feedback do not affect the supply voltage and DC biasing conditions. Theoretical analysis and simulation results show that a significant bandwidth enhancement is achieved.     

A New CMOS Current-Mode Multiplexer for l0 Gbps Serial Links

This paper presents an in-depth study of the pros and cons of voltage-mode multiplexers for Gbps serial links and exploits the advantages of multiplexing in current domain. In addition, it proposes a new fully differential CMOS current-mode multiplexer where a high multiplexing speed is achieved by multiplexing at a low-impedance node. Multiplexing speed is further improved by inductive shunt peaking with active inductors. The differential configuration of the multiplexer minimizes the effect of common-mode disturbances, particularly those coupled from the power and ground rails. The flow of the output currents in the opposite directions minimizes the effect of electro-magnetic interference from channels, making the multiplexer particularly attractive for high-speed data transmission over long interconnects and printed-circuit-board (PCB) traces. The proposed multiplexer draws a constant current from the supply voltage, thereby minimizing both switching noise and noise injected to the substrate. A fully differential CMOS current-mode 8-to-l multiplexer has been implemented in TSMC’s 1.8 V 0.18 μm CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3.3v device models. Simulation results demonstrate that the multiplexer offers sufficiently large eye-opening when multiplexed at 10 Gbps.Jean Jiang received the B.Eng. degree in Electrical Engineering from Wuhan University of Technology, Wuhan, China in 1995. From 1999 to 2001, she worked for Ericsson Global IT Services where she was a technical staff to maintain computer networks. Since 2002, she has been a research assistant with the System-on-Chip research lab of Ryerson University. She is currently a M.A.Sc candidate under the supervision of Dr. Fei Yuan in the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Canada. Her research interests are in analog CMOS circuit design for high-speed data communications. She was awarded the Ontario Graduate Scholarship (OGS) in 2003–2005 for academic excellence.Fei Yuan received the B.Eng. degree in electrical engineering from Shandong University, Jinan, China in 1985, the MASc. degree in chemical engineering and PhD. degree in electrical engineering from University of Waterloo, Waterloo, Ontario, Canada in 1995 and 1999, respectively.During 1985–1989, he was a Lecturer in the Department of Electrical Engineering, Changzhou Institute of Technology, Jiangsu, China. In 1989 he was a Visiting Professor at Humber College of Applied Arts and Technology, Toronto, Canada. During 1989–1994, he worked for Paton Controls Limited, Sarnia, Ontario, Canada as a Controls Engineer. Since July 1999 he has been with the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Ontario, Canada, where he is currently an Associate Professor and the Associate Chair for Undergraduate Studies and Faculty Affairs. He is the co-author of the book “Computer Methods for Analysis of Mixed-Mode Switching Circuits” (Kluwer Academic Publishers, 2004, with Ajoy Opal). Dr. Yuan received an “Excellence of Teaching” award from Changzhou Institute of Technology in 1988, a post-graduate scholarship from Natural Science and Engineering Research Council (NSERC) of Canada during 1997–1998. He is a senior member of IEEE and a registered professional engineer in the province of Ontario, Canada.     

A 1.5 V Current-Mode CMOS RMS-to-DC Converter

A very low voltage, current-mode CMOS RMS-to-DC converter is presented. It is fully designed using MOS Translinear techniques. More specifically, its main building blocks are a squarer/divider and a geometric-mean cell which are obtained by using simple second-order MOS Translinear loops in a folded configuration, leading to a very regular and compact implementation. A novel biasing technique is employed for such loops, allowing them to operate at supply voltages as low as 1.5 V. Experimental results for a prototype IC demonstrating the correct operation of the circuit are included.     

High-Speed High-Precision CMOS Current Conveyor

In this paper a new class-AB CMOS second generation current conveyor (CCII) based on a novel high-performance voltage follower topology is proposed. Post-layout simulation results from a 0.8 m design supplied at 3.3 V show very low resistance at node X (<50 ), high frequency operation (100 MHz), high precision in the voltage and current transference and reduced offset. As application examples, a V-I converter and a current feedback operational amplifier (CFOA) have been implemented. The latter presents slew-rate levels higher than ±100 V/s.     

Design Strategies for Class A CMOS CCIIS

In this paper, solutions for class A CCIIs are discussed and design arrangements are suggested to achieve improved performance in terms of gain accuracy, impedance level, offset and linearity. The noise performance is also evaluated and compared for the various solutions. Finally, a novel CCII is proposed which is based on an innovative arrangement of the biasing. The circuit provides a THD 15 dB lower than previous solutions and has a linearity feature which has low sensitive to the mismatch of the parameters and V _T .     

一种红外探测器专用77K工作CMOS前置放大器

利用single-ended folded-cascode 结构和MOS管工作在线性区做反馈电阻，实现了一种在77K工作的高性能低功耗、低噪声前置放大器．分析了它的噪声特性，提出了减少噪声的措施．此前置放大器用1.2μm的标准CMOS工艺制造完成．经过测试，这种前置放大器在低温77K下能正常工作，反馈电阻大小为兆欧级，线性度达到了1％,等效输入噪声电流仅0.03pA/Hz，功耗小于1mW．     

2.5Gb/Scmos光接收机跨阻前置放大器

给出了一种利用0.35μm CMOS工艺实现的2.5Gb/s跨阻前置放大器。此跨阻放大器的增益为59 dB*Ω,3dB带宽为2GHz,2GHz处的等效输入电流噪声为0.8×10-22 A2/Hz。在标准的5V电源电压下,功耗为250mW。PCML单端输出信号电压摆幅为200mVp-p。整个芯片面积为1.0mm×1.1mm。     

A 10 bit Current-Mode CMOS A/D Converter with a Current Predictor and a Modular Current Reference

This paper describes a 10 bit CMOS current-mode A/D converter with a current predictor and a modular current reference circuit. A current predictor and a modular current reference circuit are employed to reduce the number of comparator and reference current mirrors and consequently to decrease a power dissipation. The 10 bit current-mode A/D converter is fabricated by the 0.6 m n-well double poly/triple metal CMOS technology. The measurement results show the input current range of 16–528 A, DNL and INL of ±0.5 LSB and ±1.0 LSB, conversion rate of 10 M samples, and power dissipation of 94.4 mW with a power supply of 5 V. The effective chip area excluding the pads is 1.8 mm×2.4 mm.     

40-Gbit/s SDH光纤通信系统前置放大器设计

基于0.35μm SiGe BiCMOS工艺,设计了共基极和共发共基两种输入结构的前置放大器.为获得更宽的电路带宽,共基极电路采用了电容峰化技术.电路仿真表明,采用这些技术使两种前置放大器的跨阻带宽都达到了28GHz以上,满足了40Gbit/s SDH光纤通信系统带宽要求.通过比较两种不同输入结构前置放大器的增益、带宽、电路稳定性以及噪声特性,提出了双极型晶体管实现高速前置放大器的设计方案.     

High Output Impedance Current-Mode Four-Function Filter with Reduced Number of Active and Passive Elements Using the Dual Output Current Conveyor

This paper reports a new single-input multi-output current-mode multifunction filter which can simultaneously realise LP, HP, BP and BR filter functions all at high impedance outputs. The circuit permits orthogonal adjustment of quality factor Q and ₀, employs only five grounded passive components and no element matching conditions are imposed. A second order all-pass function can easily be obtained. The passive sensitivities are shown to be low.     

A Novel Dual-Output CCII-Based Single-Ended to Differential Converter

In this paper a novel single-ended to differential converter topology, based on second generation current conveyors (CCIIs) is proposed. The converter architecture is very simple, being formed by a dual output current-conveyor (DOCCII) and three resistances which fix the gain of the circuit independently from the active block. Also the DOCCII topology is original, having the particular feature that output signals show a very little phase shifting between the two high impedance current outputs. The circuit has been implemented in a standard CMOS technology (AMS 0.35 m), using a supply voltage of ± 0.75 V. Theoretical values, circuit simulations and post-layout simulations are also shown and their good agreement confirms the validity of the presented idea.     

Simulation of a Monolithic Integrated CMOS Preamplifier for Neural Recordings

提出一种用于提取神经电信号的新型单片集成CMOS前置放大器.在放大器输入端引入的交流耦合电容可以消除存在于电极-电解液之间的电极极化电压,栅源电压为负值的二极管连接的nMOS晶体管能够作为大电阻,并且占用很小芯片面积,可以通过此大电阻为前置放大器提供直流偏置,同时不影响输入阻抗值.通过对输入级进行理论噪声分析,确定了放大器中的各个器件参数.仿真结果表明,由于采用电容负反馈结构,此放大器的交流增益为38.8dB,无直流增益,在0.1Hz～1kHz频率范围内,总输入等效噪声为277nVrms.     

提取神经电信号的单片集成CMOS前置放大器的仿真研究

提出一种用于提取神经电信号的新型单片集成CMOS前置放大器.在放大器输入端引入的交流耦合电容可以消除存在于电极-电解液之间的电极极化电压,栅源电压为负值的二极管连接的nMOS晶体管能够作为大电阻,并且占用很小芯片面积,可以通过此大电阻为前置放大器提供直流偏置,同时不影响输入阻抗值.通过对输入级进行理论噪声分析,确定了放大器中的各个器件参数.仿真结果表明,由于采用电容负反馈结构,此放大器的交流增益为38.8dB,无直流增益,在0.1Hz～1kHz频率范围内,总输入等效噪声为277nVrms.     

CMOS Design of a Current-Mode Multiplier/Divider Circuit with Applications to Fuzzy Controllers

Multiplier and divider circuits are usually required in the fields of analog signal processing and parallel-computing neural or fuzzy systems. In particular, this paper focuses on the hardware implementation of fuzzy controllers, where the divider circuit is usually the bottleneck. Multiplier/divider circuits can be implemented with a combination of A/D-D/A converters. An efficient design based on current-mode data converters is presented herein. Continuous-time algorithmic converters are chosen to reduce the control circuitry and to obtain a modular design based on a cascade of bit cells. Several circuit structures to implement these cells are presented and discussed. The one that is selected enables a better trade-off speed/power than others previously reported in the literature while maintaining a low area occupation. The resulting multiplier/divider circuit offers a low voltage operation, provides the division result in both analog and digital formats, and it is suitable for applications of low or middle resolution (up to 9 bits) like applications to fuzzy controllers. The analysis is illustrated with Hspice simulations and experimental results from a CMOS multiplier/divider prototype with 5-bit resolution. Experimental results from a CMOS current-mode fuzzy controller chip that contains the proposed design are also included.     

New Four-Quadrant CMOS Current-Mode and Voltage-Mode Multipliers

In this paper, a four-quadrant current-mode multiplier based on a new squarer cell is proposed. The multiplier has a simple core, wide input current range with low power consumption, and it can easily be converted to a voltage-mode by using a balanced output transconductor (BOTA) [1]. The proposed four-quadrant current-mode and voltage-mode multipliers were confirmed by using PSPICE simulation and found to have good linearity with wide input dynamic range. For the proposed current-mode multiplier, the static power consumption is 0.671 mW, the maximum power consumption is 0.72 mW, the input current range is ± 60 μ A, the bandwidth is 31 MHz, the input referred noise current is 46 pA/√Hz, and the maximum linearity error is 3.9%. For the proposed voltage-mode multiplier, the static power consumption is 1.6 mW, the maximum power consumption is 1.85 mW, the input voltage range is ± 1V from ± 1.5V supply, the bandwidth is 25.34 MHz, the input referred noise voltage is 0.85 μV/√Hz, and the maximum linearity error is 4.1%. Mohammed A. Hashiesh was born in Elkharga, New Valley, Egypt, in 1979. He received the B.Sc. degree with honors from the Electrical Engineering Department, Cairo University, Fayoum-Campus, Egypt in 2001, and he received the M.Sc. degree in 2004 from the Electronics and Communication Engineering Department, Cairo University, Egypt. He is currently a Teacher Assistant at the Electrical Engineering Department, Cairo University, Fayoum-Campus. His research interests include analog CMOS integrated circuit design and signal processing, and digitally programmable CMOS analog building blocks. Soliman A. Mahmoud was born in Cairo, Egypt, in 1971. He received the B.Sc. degree with honors, the M.Sc. degree and the Ph.D. degree from the Electronics and Communications Department, Cairo University—Egypt in 1994, 1996 and 1999 respectively. He is currently an Assistant Professor at the Electrical Engineering Department, Cairo University, Fayoum-Campus. He has published more than 50 papers. His research and teaching interests are in circuit theory, fully integrated analog filters, high frequency transconductance amplifiers, low voltage analog CMOS circuit design, current-mode analog signal processing and mixed analog/digital programmable analog blocks. Ahmed M. Soliman was born in Cairo Egypt, on November 22, 1943. He received the B.Sc. degree with honors from Cairo University, Cairo, Egypt, in 1964, the M.S. and Ph.D. degrees from the University of Pittsburgh, Pittsburgh, PA., U.S.A., in 1967 and 1970, respectively, all in Electrical Engineering. He is currently Professor Electronics and Communications Engineering Department, Cairo University, Egypt. From September 1997–September 2003, Dr Soliman served as Professor and Chairman Electronics and Communications Engineering Department, Cairo University, Egypt. From 1985–1987, Dr. Soliman served as Professor and Chairman of the Electrical Engineering Department, United Arab Emirates University, and from 1987–1991 he was the Associate Dean of Engineering at the same University. He has held visiting academic appointments at San Francisco State University, Florida Atlantic University and the American University in Cairo. He was a visiting scholar at Bochum University, Germany (Summer 1985) and with the Technical University of Wien, Austria (Summer 1987). In 1977, Dr. Soliman was decorated with the First Class Science Medal, from the President of Egypt, for his services to the field of Engineering and Engineering Education. Dr Soliman is a member of the Editorial Board of Analog Integrated Circuits and Signal Processing. Presently Dr. Soliman is Associate Editor of the IEEE Transactions on Circuits and Systems I (Analog Circuits and Filters).     

A New Static Differential CMOS Logic with Superior Low Power Performance

A new differential static CMOS logic (DSCL) family is devised. The new circuit is fully static, making it simple to design. The circuit topology of the DSCL and its operation is explained. Delay optimization of the new circuits was performed. It showed the fully static behavior of these circuits. Their performance in terms of delay, power, and area is compared to that of conventional static differential logic and dynamic differential logic. Spice simulations using a 0.18 m technology with a power supply of 1.8 V was utilized to evaluate the performance of the three circuits. Two different sets of simulations were carried out; one with equal input capacitances of all circuits and another with equal circuit delays. For each design, all circuits were optimized for minimum delay. It is shown that at equal input capacitance, the DSCL achieved 40% less delay than the DCVSL at one third the power. Also, at equal delay, the DSCL achieved 20% of the power dissipation of the DCVSL and 78% of the DDCVSL making it the most energy-efficient among the three circuits.Muhammad E.S. Elrabaa received his B.Sc. degree in computer Engineering from Kuwait University, Kuwait in 1989, and his M.A.Sc. and PhD degrees in Electrical Engineering from the University of Waterloo, Waterloo, Canada, in 1991 and 1995, respectively. His graduate research dealt with Digital BiCMOS ICs and Low-Power circuit techniques. From 1995 till 1998, he worked as a senior circuit designer with Intel Corp., in Portland, Oregon, USA. He designed and developed low power digital circuits for Microprocessors. From 1998 till 2001 he was with the EE department, UAE University as an assistant professor. In 2001, he joined the computer Engineering department, KFUPM University. His current research interests include reconfigurable computing, low-power circuits, and communication circuits. He authored and co-authored several papers, a book and holds two US patents.     

基于控阈技术的电流型CMOS全加器的通用设计方法

利用电流信号的阈值易于控制这一特点,对电流型CMOS电路中如何实现阈值控制进行了研究.以开关信号理论为指导,建立了实现阈值控制电路的电流传输开关运算并具体指导设计了具有阈值控制功能的二值和多值电流型CMOS全加器.提出了适用于任意逻辑值的可控阈电流型CMOS全加器的通用设计方法.通过对开关单元实施阈值控制后,所设计的电路在结构上得到了非常明显的简化,在性能上也获得了改善.最后给出了采用0.25μm CMOS工艺参数的HSPICE模拟结果及其能耗比较.     

Voltage/Current-Mode Universal Filter Using FTFN and CFA

A novel configuration for realizing voltage/current-mode (VM/CM) universal filter using a single four terminal floating nullor (FTFN), a single current feedback amplifier (CFA), two capacitors and three resistors is presented. The VM configuration has three inputs and a single output and implements all the five generic filtering functions through the selection of inputs. This topology enjoys cascadability and does not require any additional active element for facilitating the filter realizations. The same circuit in current-mode has a single input and four outputs and realizes LP, HP and two BP responses simultaneously from which AP and Notch can also be realized. This topology uses grounded resistors and capacitors which are ideal for monolithic integration. Both the topologies enjoy orthogonal control of natural frequency (ω₀) and quality factor (Q) by the grounded resistors. The topologies enjoy low active and passive sensitivity figures. Experimental and PSPICE simulation results are also included.     

Inductor Current Sampled Feedback Control of Chaos in Current-Mode Boost Converter

A chaos control strategy for chaotic current-mode boost converter is presented by using inductor current sampled feedback control technique.The quantitative analysis of control mechanism is performed by establishing a discrete alterative map of the controlled system.The stability criterion,feedback gain,and corresponding critical duty ratio are obtained from the eigenvalue of the map.The simulation results verify the t heoretical analysis results of the control strategy.     

驻极体传声器小型前置放大器的设计

传声器是一种将声信号转变为相应的电信号的电声换能器。驻极体传声器是一种用驻极体材料制造的新型传声器。由于驻极体传声器的输出阻抗很高不能直接与音频放大器相接,需要在传声器内接入一只输入阻抗极高的结型场效应三极管来进行阻抗变换。一些小型的驻极体传声器虽然可以将场效应管集成于传声器内部,但是价格高昂;而传统的前置放大器体积又过于庞大。针对此利用现有的技术条件,设计了一种体积小、成本低廉而性能优良的前置放大器。