Arbitrated address-event representation digital image sensor

An 80×60 pixels arbitrated address-event imager has been designed and fabricated in a 0.6 μm CMOS process. The output bandwidth is allocated according to the pixel's demand. The imager has a large dynamic range: 200 dB (pixel) and 120 dB (array). The power consumption is 3.4 mW in uniform indoor light. The imager is capable of 8.3 K effective frames per second     

A biomorphic digital image sensor

An arbitrated address-event imager has been designed and fabricated in a 0.6-/spl mu/m CMOS process. The imager is composed of 80 /spl times/ 60 pixels of 32 /spl times/ 30 /spl mu/m. The value of the light intensity collected by each photosensitive element is inversely proportional to the pixel's interspike time interval. The readout of each spike is initiated by the individual pixel; therefore, the available output bandwidth is allocated according to pixel output demand. This encoding of light intensities favors brighter pixels, equalizes the number of integrated photons across light intensity, and minimizes power consumption. Tests conducted on the imager showed a large output dynamic range of 180 dB (under bright local illumination) for an individual pixel. The array, on the other hand, produced a dynamic range of 120 dB (under uniform bright illumination and when no lower bound was placed on the update rate per pixel). The dynamic range is 48.9 dB value at 30-pixel updates/s. Power consumption is 3.4 mW in uniform indoor light and a mean event rate of 200 kHz, which updates each pixel 41.6 times per second. The imager is capable of updating each pixel 8.3K times per second (under bright local illumination).     

Vertically integrated sensors for advanced imaging applications

A thin film on ASIC (TFA) image sensor is fabricated depositing an amorphous silicon thin-film detector onto a CMOS ASIC. With regards to advanced imaging systems, TFA provides enhanced performance and more flexibility than conventional technologies. Extensive on-chip signal processing is feasible, as well as small pixels for high resolution imagers. Two new TFA imager prototypes have recently been fabricated. High-resolution image sensor (HIRISE II) with 1024×128 pixels is an active pixel sensor suited for digital photography. Local autoadaptiver sensor (LARS II) with 368×256 pixels splits the illumination information into two signals, thereby providing a dynamic range of more than 120 dB, as required by automotive applications. Both prototypes include correlated double sampling and double delta sampling for efficient suppression of fixed pattern noise     

A pixel size shrinkage of amplified MOS imager with two-line mixing

This paper describes a pixel size shrinkage of an amplified MOS image sensor (AMI). We have developed a new circuit technique to achieve the reduction of a pixel size while realizing vertical two-line mixing and high sensitivity. A 1/4-in format 250-k pixel image sensor was developed using a 0.8-μm CMOS process. The difference from the conventional CMOS process is an additional layer of ion-implantation process. The power supply voltages of this imager are 4 and 6 V. The dynamic range of 75 dB, the sensitivity of 1.8 μA/Ix, and the smear noise of less than -120 dB have been attained for the pixel size of 7.2 (H)×5.6 (V) μm². Although the measured fixed pattern noise ratio (FPN) of this imager is -55 dB, analysis with a test chip shows that FPN can be improved by 2 dB by adopting a suitable gate length for amplifier and resetting MOSFET, respectively     

A 2/3-in 2 million pixel STACK-CCD HDTV imager

A 2/3-in optical format 2 M pixel STACK-CCD imager has been developed. The STACK-CCD imager, overlaid with an amorphous silicon photoconversion layer, realizes a large signal charge handling capability of 1.0×10⁵ electrons, a -140 dB smear noise and a 90 dB dynamic range with a newly introduced device configuration and its unique operation. The 5.0 μm(H)×5.2 μm(V) unit pixel imager with sufficiently low image lag has been realized by a novel bias charge injection scheme These device performances are the best ever achieved by a CCD HDTV imager. This is the first such imager satisfying the device performances required for a practical use 2/3-in 2 M pixel HDTV imager     

A 1 K×1 K high dynamic range CMOS image sensor with on-chipprogrammable region-of-interest readout

An integrated 1024×1024 CMOS image sensor with programmable region-of-interest (ROI) readout and multiexposure technique has been developed and successfully tested. Size and position of the ROI is programmed based on multiples of a minimum readout kernel of 32×32 pixels. Since the dynamic range of the irradiance normally exceeds the electrical dynamic range of the imager that can be covered using a single integration time, a multiexposure technique has been implemented in the imager. Subsequent sensor images are acquired using different integration times and recomputed to form a single composite image. A newly developed algorithm performing the recomputation is presented. The chip has been realized in a 0.5-μm n-well standard CMOS process. The pixel pitch is 10 μm² and the total chip area is 164 mm ²     

Dynamic Reconfiguration of Differential Pixel Output for CMOS Imager Dedicated to WDM-SDM Indoor Optical Wireless LAN

A dedicated complementary metal-oxide-semiconductor (CMOS) imager with parallel photoreceivers has been deployed for new indoor wireless local area network systems where images and communications are mixed to offer location awareness and an extended data transfer bandwidth with wavelength- and space-division multiplexing for the downlink and uplink, respectively. To realize data acquisition while capturing images, dynamic reconfiguration of differential pixel output with a small area overhead is proposed for suppressing signal contamination at the sensitive photoreceiver circuitry by common mode noise from the image readout digital circuitry. A prototype CMOS imager with 64 times 64 pixels and four parallel photoreceiver channels was fabricated in a standard 0.35-mum CMOS process, and concurrent scene image capturing and multipoint data acquisition at 10-Mb/s/channel were demonstrated. The measured signal-to-crosstalk ratio was around 18 dB.     

A log-polar image sensor fabricated in a standard 1.2-μm ASICCMOS process

A CMOS log-polar or foveated image sensor for use in mobile robotic and machine vision applications has been designed, fabricated, and tested. The sensor benefits from a high degree of integration, minimal power consumption, and ease of manufacture due to the use of a standard 1.2 μm ASIC CMOS process. The sensor is composed of two distinct CMOS imager arrays which together solve the problem of obtaining good image resolution over a wide field of view. With resolution sensing is accomplished with a 40×40 array of individual pixels each measuring 9.6 μm on a side. A wide field of view is provided by an array of 64×16 pixels arranged on a log-polar grid. The maximum measured dynamic range for the fabricated log-polar array is 46 dB, while the lowest observed fixed-pattern noise is 0.5% of saturation. Combined power consumption of both arrays is under 2 mW when operating from a single 5-V supply at a frame rate of 30 frames/s     

A High Dynamic Range CMOS Image Sensor With Inpixel Light-to-Frequency Conversion

A high dynamic range CMOS image sensor with inpixel light-to-frequency conversion has been designed. The prototype chip was fabricated in a standard 0.18-mum single-poly six-metal CMOS technology. The experimental results show that, operating at 1.2 V, the sensor can achieve a linear dynamic range of over 115 dB and an overall dynamic range of over 130 dB     

Large-signal subthreshold CMOS transconductance amplifier

A folding architecture for a subthreshold CMOS transconductance amplifier is described. Good linearity is obtained for an extremely large differential input voltage, without loss in the common-mode voltage range. Theoretical noise analysis indicates a 6 dB improvement in the dynamic range compared to a simple single-pair MOS implementation. A prototype has been fabricated in a 2 μm CMOS process, and experimental results are presented     

Current mode ADC design in a 0.5-μm CMOS process

This paper presents a pipelined current mode analog to digital converter (ADC) designed in a 0.5-μm CMOS process. Adopting the global and local bias scheme, the number of interconnect signal lines is reduced numerously, and the ADC exhibits the advantages of scalability and portability. Without using linear capacitance,this ADC can be implemented in a standard digital CMOS process; thus, it is suitable for applications in the system on one chip (SoC) design as an analogue IP. Simulations show that the proposed current mode ADC can operate in a wide supply range from 3 to 7 V and a wide quantization range from ±64 to ±256μA. Adopting the histogram testing method, the ADC was tested in a 3.3 V supply voltage/±64μA quantization range and a 5 V supply voltage/±256μA quantization range, respectively. The results reveal that this ADC achieves a spurious free dynamic range of 61.46dB, DNL/INL are -0.005 to +0.027 LSB/-0.1 to +0.2 LSB, respectively, under a 5 V supply voltage with a digital error correction technique.     

A 3.3-V CMOS 10.7-MHz sixth-order bandpass ΣΔ modulatorwith 74-dB dynamic range

A 3.3-V bandpass ΣΔ modulator for IF sampling at 10.7 MHz in digital radio applications has been developed. The modulator presents a sixth-order single-loop architecture and features a 74-dB dynamic range in a 2OO-kHz signal bandwidth (FM signal), while for a 9-kHz signal bandwidth (AM signal) the dynamic range is 88 dB. The modulator has been integrated in a standard 0.35-μm CMOS technology using switched-capacitor technique and consumes 76 mW from a single 3.3V supply     

A logarithmic response CMOS image sensor with on-chip calibration

CMOS image sensors with logarithmic response are attractive devices for applications where a high dynamic range is required. Their strong point is the high dynamic range. Their weak point is the sensitivity to pixel parameter variations introduced during fabrication. This gives rise to a considerable fixed pattern noise (FPN) that deteriorates the image quality unless pixel calibration is used. In the present work a technique to remove the FPN by employing on-chip calibration is introduced, where the effect of threshold voltage variations in pixels is cancelled. An image sensor based on an active pixel structure with five transistors has been designed, fabricated, and tested. The sensor consists of 525×525 pixels measuring 7.5 μm×10 μm, and is fabricated in a 0.5-μm CMOS process. The measured dynamic range is 120 dB while the FPN is 2.5% of the output signal range     

Global Shutter CMOS Image Sensor With Wide Dynamic Range

A novel concept for global shutter CMOS image sensors with wide dynamic range (WDR) implementation is presented. The proposed imager is based on the multisampling WDR approach and it allows an efficient global shutter pixel implementation achieving small pixel size and high fill factor. The proposed imager provides wide DR by applying adaptive exposure time to each pixel, according to the local illumination intensity level. Two pixel configurations, employing different kinds of a 1-bit in-pixel memory were implemented. An imager, including two different pixels was designed and simulated in 0.18-mum CMOS technology. System architecture and operation are discussed and simulation results are presented.     

CMOS exponential function generator

A new CMOS exponential function generator is presented. The proposed circuit is compact, with low power and wide dynamic range. The proposed circuit has been fabricated in a 0.50 /spl mu/m CMOS process. Experimental results show that the output range of the proposed exponential function generator can be more than 15 dB with the linear error less than /spl plusmn/ 0.5 dB. The supply voltage is /spl plusmn/ 1.5 V and the power dissipation is less than 0.4 mW. Experimental results are given to demonstrate the proposed circuit.     

An algorithmic 15-bit CMOS digital-to-analog converter

A digital-to-analog converter (DAC) has been designed which uses an algorithm based on interpolation. The algorithm ensures monotonicity and differential linearity despite offset voltages, and hence eliminates the need for trimming. The technique has been used to design a 15-bit DAC in a 2.5-μm CMOS technology. The converter features S/(N+THD) of 74 dB with a dynamic range of 87 dB and a power consumption of 22 mW at 44-kHz sample frequency     

CMOS Differential-Mode Exponential Voltage-To-Current Converter

A CMOS differential-mode exponential voltage-to-current converter is presented which is based on the approximated Taylor's series expansion. The proposed circuit has been fabricated in a 0.5μm N-well CMOS process. Experimental results show that the output dynamic range of the proposed differential-mode exponential voltage-to-current converter can be 15dB while the nonlinear error is less than 1.35%. The experimental results are given to demonstrate the proposed circuits.     

A high-performance custom standard-cell CMOS equalizer for telecommunications applications

A high-performance CMOS programmable amplitude equalizer has been implemented with a dynamic range greater than 100 dB and supply rejection greater than 60 dB at 1 kHz from both supplies. This was accomplished using a balanced architecture. A nonreturn-to-zero sample-and-hold circuit is proposed that is also parasitic-insensitive. The circuits are implemented using a standard-cell methodology.     

High frequency/high dynamic range CMOS VGA

A novel CMOS variable gain amplifier (VGA) with high frequency and high dynamic range is proposed. The VGA has a controllable gain range of -50 dB-+50 dB which can be controlled by adjusting the external voltage as well as an enhanced operating frequency range up to 200 MHz. It is fabricated using 0.35 μm CMOS technology and has a core area of 580×660 μm     

A CMOS Hearing Aid Device

In this paper a CMOS Hearing Aid Device is described. The system is composed of a low-distortion low-noise preamplifier, an automatic gain control (AGC), a fully programmable switched-capacitor filter (equalizer), and a control system. The device has been fabricated in a 1.2 m CMOS analog process. The dynamic range of the device is 55 dB while the harmonic distortion components are below –50 dB. Experimental results show the feasibility of the proposed architecture.