手持式超高频RFID读写器天线设计技术综述

天线作为手持式超高频射频识别技术(Radio frequency identification technology,RFID)读写器中的关键部件,其性能直接影响到RFID系统的读写距离和读写器体积大小.论文分析研究各种手持式超高频RFID读写器天线的设计技术,重点介绍应用最广的微带天线设计方法、技巧及发展趋势.     

基于虚拟无线电的RFID读写器实现方案

随着通用计算机性能的不断提高,虚拟无线电技术得以发展。根据虚拟无线电处理基带信号具有更好的灵活性、通用性和开放性的优点以及Is0／IEC18000—6C标准中超高频RFID读写器的特性,在此提出了一种基于虚拟无线电的超高频RFID读写器的实现方案。该方案介绍了常见RFID系统的结构和工作原理,重点阐述了基于虚拟无线电的RFID读写器的整体结构和工作流程,并时接收端算法做了研究与实现。     

超高频RFID读写器组网与协调技术研究

在大规模的RFID技术应用场合,要部署大量的读写器,需要进行读写器网络的规划,为了保证整个读写器网络的通信需求,需要进行读写器之间的协调.本文对超高频RFID读写器组网和协调技术进行了研究,综述了现有的研究成果,并对现有的读写器冲突解决方法进行了比较,讨论了今后的研究方向.     

RFU620：RFlD读写器

RFU620是继RFU630长距离超高频RFID读写器后SICK发布的又一重要无线射频读写器产品。RFU620的发布进一步完善了SICK以高频（RFH620,RFH630）和超高频（RFU620／RFU630）为主的RFID产品系列。     

UHF射频读写器的设计

为满足市场需求,提高读写器的读写效率,提出了一种超高频读写器的设计方案,介绍了读写器的系统硬件结构,在此基础上阐述了RFID读写器的软件设计流程以及防冲撞算法的实现。相对于采用传统随机碰撞算法的读写器,此读写器适用于超高频段,能够在多标签环境下顺利读取标签,防冲撞算法性能具有一定的提高。     

UHF射频读写器的设计

为满足市场需求,提高读写器的读写效率,提出了一种超高频读写器的设计方案,介绍了读写器的系统硬件结构,在此基础上阐述了RFID读写器的软件设计流程以及防冲撞算法的实现。相对于采用传统随机碰撞算法的读写器,此读写器适用于超高频段,能够在多标签环境下顺利读取标签,防冲撞算法性能具有一定的提高。     

基于DSP技术的RFID读写器设计

文中介绍了RFID系统及RFID读写器,论述了基于DSP技术的RFID读写器设计方法.在描述RFID系统组成的基础上,给出了读写器的软硬件设计流程.重点阐述了RFID读写器的防冲突设计.该读写器已应用于门禁系统中,实际应用结果表明其性能良好.     

超高频RFID读写器调制解调模块的设计

分析了超高频RFID读写器的系统结构,设计了用于读写器射频收发机中调制和解调的模块,并在0.18μm CMOS工艺下进行了流片验证.测试结果表明,调制器输入ldB压缩点可达14dBm,插入损耗为l.17dB,关断时隔离为33dB,输入输出端皆匹配在50Ω;解调器输入ldB压缩点可达5dBm,噪声系数仅9dB,而且具有4.9dB的电压增益,克服了传统结构没有正增益的缺点;两者均无直流功耗.     

超高频RFID读写器调制解调模块的设计

分析了超高频RFID读写器的系统结构,设计了用于读写器射频收发机中调制和解调的模块,并在0.18μm CMOS工艺下进行了流片验证.测试结果表明,调制器输入ldB压缩点可达14dBm,插入损耗为l.17dB,关断时隔离为33dB,输入输出端皆匹配在50Ω;解调器输入ldB压缩点可达5dBm,噪声系数仅9dB,而且具有4.9dB的电压增益,克服了传统结构没有正增益的缺点;两者均无直流功耗.     

超高频RFID读写器射频电路设计

RFID是通过射频信号,利用空间耦合实现无接触信息传递、识别的技术,已经被广泛应用在各个行业之中。在这一背景下,文章以超高频RFID读写器射频电路仿真、PCB设计为切入点,深入探究视频电路设计的方式。目的是强化RFID的性能,提高信号传递、识别的准确性,以期为相关人员提供参考。     

Design of Reader Baseband Receiver Structure for Demodulating Backscattered Tag Signal in a Passive RFID Environment

In this paper, we present a demodulation structure suitable for a reader baseband receiver in a passive radio frequency identification (RFID) environment. In a passive RFID configuration, an undesirable DC‐offset phenomenon may appear in the baseband of the reader receiver, which can severely degrade the performance of the extraction of valid information from the received tag signal. To eliminate this DC‐offset phenomenon, the primary feature of the proposed demodulation structures for the received FM0 and Miller subcarrier signals is to reconstruct the signal corrupted by the DC‐offset phenomenon by creating peak signals from the corrupted signal. It is shown that the proposed method can successfully detect valid data, even when the received baseband signal is distorted by the DC‐offset phenomenon.     

A fully digital noncoherent and coherent GMSK receiver architecturewith joint symbol timing error and frequency offset estimation

We propose a fully digital noncoherent and coherent Gaussian minimum shift keying (GMSK) receiver architecture with joint frequency offset compensation and symbol timing recovery. Carrier phase offset can be estimated if the coherent demodulation mode is adopted. The converted base-band complex signal is first frequency discriminated and then passed through a digital filter which performs a fast Fourier transform (FFT). The frequency offset can be estimated from the DC component of the FFT, and the symbol timing error can be estimated from the phase angle of the FFT at a specified frequency which is equal to an integral multiple of half the bit rate. These two estimated parameters are then used for frequency offset compensation and symbol timing recovery during a preamble period. Coarse carrier phase can be estimated by averaging sampled in-phase and quadrature-phase signals and finding its phase angle within the preamble period after carrier frequency offset is estimated and compensated. The bit error rate (BER) performance of this GMSK receiver architecture is assessed for an additive white Gaussian noise (AWGN) channel by computer simulation     

直接变频接收机性能分析

本文对直接变频接收机中正交矢量检测法进行了误差分析，讨论了由于接收机同相与正交两支路的增益差异、相位误差、本振泄漏及直流偏置导致其性能恶化的结果。为了实现ＧＭＳＫ信号解调，接收机中ＤＳＰ实现了调制信号的误差频谱估计、位同步恢复及译码。最后，用计算机模拟方法对该接收机性能进行了比较评价。     

A novel analog/digital reconfigurable automatic gain control with a novel DC offset cancellation circuit

An analog/digital reconfigurable automatic gain control(AGC) circuit with a novel DC offset cancellation circuit for a direct-conversion receiver is presented.The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips.What’s more,a novel DC offset cancellation(DCOC) circuit with an HPCF(high pass cutoff frequency) less than 10 kHz is proposed.The AGC is fabricated by a 0.18μm CMOS process.Under analog control mode,the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz.Under digital control mode,through a 5-bit digital control word,the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB.The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV,while the offset voltage of 40 mV is introduced into the input.The overall power consumption is less than 3.5 mA,and the die area is 800×300μm~2.     

A low power mixed signal DC offset calibration circuit for direct conversion receiver applications

A low power mixed signal DC offset calibration(DCOC) circuit for direct conversion receiver applications is designed.The proposed DCOC circuit features low power consumption,fast settling time and a small die area by avoiding the trade-off between loop response time and the high pass frequency of the DCOC servo loop in conventional analog DCOC systems.By applying the proposed DC offset correction circuitry,the output residue DC offset voltages are reduced to less than 38 mV and the DCOC loop settling time is less than 100μs.The DCOC chip is fabricated in a standard 0.13-μm CMOS technology and drains only 196μA from a 1.2-V power supply with its chip area of only 0.372×0.419 mm~2.     

BER Analysis of OFDM Systems Impaired by DC Offset and Carrier Frequency Offset in Multipath Fading Channels

We perform bit-error-rate (BER) analysis of orthogonal frequency division multiplexing (OFDM) systems impaired by both direct current (DC) offset and carrier frequency offset (CFO) in multipath Rayleigh fading channels. Since the performance of OFDM systems is sensitive to the CFO, it is necessary to estimate and correct the CFO at the receiver. The existence of DC offset degrades the performance of CFO estimator and results in large residual CFO after compensation. Moreover, the process of CFO compensation spreads the DC offset energy and causes DC offset interference to all subcarriers. By deriving the BER formula for OFDM systems employing binary phase-shift keying modulation, the dependency of BER on the DC offset, CFO, and estimated CFO is accurately quantified. Simulation results validate the correctness of our theoretical analysis.     

应用于多模接收机的低功耗可编程增益放大器

针对多模接收机的应用,提出了引入一条闭环伪通路技术结构的可编程增益放大器,在保持一定的线性度及噪声性能的基础上,以较低的功耗实现较大的带宽.该电路增益步长为2 dB,增益变化范围1～39 dB.电路中内嵌了直流失调消除模块防止直流漂移引起的阻塞.芯片采用SMIC 0.13 μm 1P8M RF CMOS工艺实现.测试结...     

IQ imbalance compensation scheme in the presence of frequency offset and dynamic DC offset for a direct conversion receiver

A direct conversion architecture reduces the cost and power consumption of a receiver. However, a direct conversion receiver may suffer from direct current (DC) offset, frequency offset, and IQ imbalance. This paper presents an IQ imbalance estimation scheme for orthogonal frequency division multiplexing (OFDM) direct conversion receivers. The proposed IQ imbalance estimation scheme operates in the presence of dynamic DC offset and frequency offset. The proposed scheme calculates IQ imbalance from a simple equation. It employs the knowledge of the preamble symbols of the IEEE 802.11 a/g standards, while it does not require the impulse response of the channel. Numerical results obtained through computer simulation show that the bit error rate (BER) performance for the proposed IQ imbalance estimation scheme has a degradation of about 4dB with a large DC offset, frequency offset, and IQ imbalance.     

DSSS数字接收机的AFC算法及其实现

介绍了一种零中频直接序列扩频(DSSS)数字接收机的自动频率控制(AFC)算法及其仿真和实现.该算法从残留载波跟踪解调环的鉴相信号中提取频偏信息,对下变频本振进行AFC,并且可根据对频偏的估计切换环路特性,使环路既有较大的捕获带宽,又具有较好的跟踪和滤波性能.该算法适用于无导频的直扩BPSK信号接收机,其特点是算法复杂度低,特别易于FPGA实现.     

VSB‐Based Digital On‐Channel Repeater with Interference Cancellation System

This paper investigates the design and performance of a digital on‐channel repeater (DOCR) for use in Advanced Television Systems Committee (ATSC) digital television (DTV) broadcasting. The main drawback of a DOCR is the echo interference caused by coupling between transmitter and receiver antennas, which induces system instability and performance degradation. In order to overcome this problem, an echo canceller based on the adaptive echo channel estimation (ECE) technique has been researched and applied for a DOCR. However, in the case of ATSC, the pilot signal, which is used for carrier synchronization, may cause a DC offset error and reduce the isolation performance of the echo canceller for a DOCR in an ATSC network. Moreover, since the multipath fading effect of a radio channel usually occurs in a real environment, it should be minimized to improve the overall performance of a DOCR. Therefore, due to the limited isolation performance of echo canceller and the multipath fading effect, an interference cancellation system (ICS) is proposed for a DOCR in an ATSC network. The performance of the proposed DOCR with an ICS is evaluated by software simulation and hardware test results.