Transposed FIR filter structure with time-varying coefficients fordigital data resampling

A new time-domain derivation is presented for interpolation and decimation by a fractional factor U/D. Though it is well known that such a filter can be implemented using a direct-form I, FIR filter with time-varying coefficients, a novel time-varying alternative, using a transposed filter structure, is described. Time-varying filters are especially important for implementation on a digital signal processor. The new time-varying structure has the advantage of reduced buffer memory for downscaling, or increased parallelism for high-speed upscaling, compared to the conventional time-varying structure     

Balanced realisations and model reduction of periodicallytime-varying state-space digital filters

The authors discuss balanced realisations and model reduction of periodically time-varying (PTV) state-space digital filters. Controllability and observability Grammians of PTV state-space digital filters are discussed. It is extremely interesting to notice that although PTV state-space digital filters can be implemented by using a group of time-invariant coefficient sets, controllability and observability Grammians cannot be evaluated independently by using any one set of these time-invariant coefficients. Also, important physical interpretations of controllability and observability Grammians are considered. Based on these analysis results, balanced realisations of PTV state-space digital filters are defined and a synthesis method for balanced realisations is proposed. As one application of balanced realisations, a reduced-order model of a PTV state-space digital filter can be obtained by taking a subsystem of balanced realisation of the PTV state-space digital filter. Finally, a numerical example is given to illustrate the balanced model reduction procedure     

Sufficient stability bounds for slowly varying direct-formrecursive linear filters and their applications in adaptive IIR filters

This article derives a sufficient time-varying bound on the maximum variation of the coefficients of an exponentially stable time-varying direct-form homogeneous linear recursive filter. The stability bound is less conservative than all previously derived bounds for time-varying IIR systems. The bound is then applied to control the step size of output-error adaptive IIR filters to achieve bounded-input bounded-output (BIBO) stability of the adaptive filter. Experimental results that demonstrate the good stability characteristics of the resulting algorithms are included. This article also contains comparisons with other competing output-error adaptive IIR filters. The results indicate that the stabilized method possesses better convergence behavior than other competing techniques     

Design of Dual‐Mode Digital Down Converter for WCDMA and cdma2000

We propose an efficient digital IF down converter architecture for dual‐mode WCDMA/cdma2000 based on the concept of software defined radio. Multi‐rate digital filters and fractional frequency conversion techniques are adopted to implement the front end of a dual‐mode receiver for WCDMA and cdma2000. A sub‐sampled digital IF stage was proposed to support both WCDMA and cdma2000 while lowering the sampling frequency. Use of a CIC filter and ISOP filter combined with proper arrangement of multi‐rate filters and common filter blocks resulted in optimized hardware implementation of the front end block in 292k logic gates.     

Data smoothing by cubic spline filters

In this correspondence, a digital filter that allows the computation of a smoothing cubic spline for equispaced data with a constant control parameter is proposed. Filters to compute its first and second derivatives are also presented. Derived from the classical matrix solution, these filters offer an efficient way to calculate smoothed data and its derivatives, especially when the length of data is long. Moreover, these filters have been found to possess several interesting properties. For instance, the smoothing filter is a low-pass filter with the maximum flatness property. In addition, a useful relation between the filter bandwidth and the control parameter is established, which can be used for its optimal choice in practice. The proposed filters can easily be implemented either with a recursive structure for off-line processing or with a nonrecursive implementation for real-time processing     

Variable digital filter design using the outer product expansion

Digital filters with adjustable frequency domain characteristics are referred to as variable digital filters. Variable filters are useful in the applications where the filter characteristics are required to be changeable during the course of signal processing. Especially in real time applications, variable filters are needed to change their coefficients instantaneously such that the real time signal processing can be performed. The present paper proposes a very efficient technique for variable 1D digital filter design. Generally speaking, the variable coefficients of variable digital filters are multidimensional functions of a set of spectral parameters which define the desired frequency domain characteristics. The authors first sample the given variable 1D magnitude specification and use the samples to construct a multidimensional array, then propose an outer product expansion method for expanding the multidimensional array as the sum of outer products of 1D arrays (vectors). Based on the outer product expansion, one can reduce the difficult problem of designing a variable 1D digital filter to the easy one that only needs constant 1D filter designs and 1D polynomial approximations. The technique can obtain variable 1D filters having arbitrary desired magnitude characteristics with a high design accuracy     

A simple and efficient design of variable fractional delay FIR filters

In this paper, a simple and efficient approach for designing one-dimensional variable fractional delay finite impulse response digital filters is proposed. Two matrix equations, based respectively on the weighted least-squares function of the optimum fixed fractional delay filter and the filter coefficient polynomial fitting, are formulated in tandem to form the design algorithm, which only has the computation complexity comparable with that of designing fixed finite impulse response digital filters. A design example is also given to justify the effectiveness and advantages of the proposed design method.     

A sequentially operated periodic FIR filter for perfect reconstruction

This paper presents a sequentially operated periodic FIR filter to perform the functions of multirate filter banks for perfect reconstruction. This filter consists of an analysis filter and a synthesis filter. Each of these filters has a single-input/single-output FIR filter with periodically time-varying coefficients and a sequentially operated multichannel sampling scheme. As a result, the proposed filter can offer considerable improvements in computation and implementation. For the design of the filter, we provide a necessary and sufficient condition for perfect reconstruction in terms of the blocked transfer matrices and give a design procedure.     

Design of High-Order Extrapolated Impulse Response FIR Filters with Signed Powers-of-Two Coefficients

Expensive multiplication operations can be replaced by simpler additions and hardwired shifters so as to reduce power consumption and area size, if the coefficients of a digital filter are signed power-of-two (SPT). As a consequence, FIR digital filters with SPT coefficients have been widely studied in the last three decades. However, most approaches for the design of FIR filters with SPT coefficients focus on filters with length less than 100. These approaches are not suitable for the design of high-order filters because they require excessive computation time. In this paper, an approach for the design of high-order filters with SPT coefficients is proposed. It is a two-step approach. Firstly, the design of an extrapolated impulse response (EIR) filter is formulated as a standard second-order cone programming (SOCP) problem with an additional coefficient sensitivity constraint for optimizing its finite word-length effect. Secondly, the obtained continuous coefficients are quantized into SPT coefficients by recasting the filter-design problem into a weighted least squares (WLS) sequential quadratic programming relaxation (SQPR) problem. To further reduce implementation complexity, a graph-based common subexpression elimination (CSE) algorithm is utilized to extract common subexpressions between SPT coefficients. Simulation results show that the proposed method can effectively and efficiently design high-order SPT filters, including Hilbert transformers and half-band filters with SPT coefficients. Experiment results indicate that 0.81N∼0.29N adders are required for 18-bit N-order FIR filters (N=335∼3261) to meet the given magnitude response specifications.     

Two-Dimensional Farrow Structure and the Design of Variable Fractional-Delay 2-D FIR Digital Filters

In this paper, a 2-D Farrow structure is proposed and used to implement variable fractional-delay (VFD) 2-D FIR digital filters. Compared with the existing literature, the desired response of a VFD 2-D digital filter is analyzed in detail, and it is found that there are four types of 2-D symmetric/antisymmetric sequences that need to be used for the design of VFD 2-D FIR digital filters. Moreover, due to the orthogonality among the approach functions, the four types of 2-D sequences can be determined independently, such that the dimension for each computation can be reduced drastically. For simplicity, only the designs of even–even- and odd–odd-order VFD 2-D filters are presented in this paper, and the other cases can be achieved in the same manner. To reveal the coefficient characteristics, the symmetric/antisymmetric properties of filter coefficients and the relationships between coefficients are all tabulated. Also, design examples such as nonseparable circularly symmetric low-pass VFD filters are presented to demonstrate the effectiveness of the proposed method.      

Optimal design of transform-based block digital filters using a quadratic criterion

Block digital filtering is a powerful tool to reduce the computational complexity of digital filtering systems. However, due to their block structure, block digital filters (BDFs) are time-varying linear systems, hence, their design is not easy. The most widely spread approaches to BDF design consist of constraining the BDF to be time-invariant (by restricting the design process to a specific subset of possible solutions) and then using conventional filter synthesis techniques. In this paper, we do not restrict the design process, and we propose a simple and optimal matrix-oriented approach to optimize the BDF coefficients. Furthermore, the proposed approach takes profit of the structure of transform-based BDFs to considerably reduce the computational complexity and memory requirements of the design process. Experimental results confirm that as expected, the obtained global distortion is lower than the distortion obtained with a traditional technique such as overlap-save.     

Design of hybrid filter banks for analog/digital conversion

This paper presents design algorithms for hybrid filter banks (HFBs) for high-speed, high-resolution conversion between analog and digital signals. The HFB is an unconventional class of filter bank that employs both analog and digital filters. When used in conjunction with an array of slower speed converters, the HFB improves the speed and resolution of the conversion compared with the standard time-interleaved array conversion technique. The analog and digital filters in the HFB must be designed so that they adequately isolate the channels and do not introduce reconstruction errors that limit the resolution of the system. To design continuous-time analog filters for HFBs, a discrete-time-to-continuous-time (“Z-to-S”) transform is developed to convert a perfect reconstruction (PR) discrete-time filter bank into a near-PR HFB; a computationally efficient algorithm based on the fast Fourier transform (FFT) is developed to design the digital filters for HFBs. A two-channel HFB is designed with sixth-order continuous-time analog filters and length 64 FIR digital filters that yield -86 dB average aliasing error. To design discrete-time analog filters (e.g., switched-capacitors or charge-coupled devices) for HFBs, a lossless factorization of a PR discrete-time filter bank is used so that the reconstruction error is not affected by filter coefficient quantization. A gain normalization technique is developed to maximize the dynamic range in the finite-precision implementation. A four-channel HFB is designed with 9-bit (integer) filter coefficients. With internal precision limited to the equivalent of 15 bits, the maximum aliasing error is -70 dB, and with the equivalent of 20 bits internal precision, maximum aliasing is -100 dB. The 9-bit filter coefficients degrade the stopband attenuation (compared with unquantized coefficients) by less than 3 dB     

High Performance Reconfigurable FIR Filter Architecture Using Optimized Multiplier

In mobile communication systems and multimedia applications, need for efficient reconfigurable digital finite impulse response (FIR) filters has been increasing tremendously because of the advantage of less area, low cost, low power and high speed of operation. This article presents a near optimum low- complexity, reconfigurable digital FIR filter architecture based on computation sharing multipliers (CSHM), constant shift method (CSM) and modified binary-based common sub-expression elimination (BCSE) method for different word-length filter coefficients. The CSHM identifies common computation steps and reuses them for different multiplications. The proposed reconfigurable FIR filter architecture reduces the adders cost and operates at high speed for low-complexity reconfigurable filtering applications such as channelization, channel equalization, matched filtering, pulse shaping, video convolution functions, signal preconditioning, and various other communication applications. The proposed architecture has been implemented and tested on a Virtex 2 xc2vp2-6fg256 field-programmable gate array (FPGA) with a precision of 8-bits, 12-bits, and 16-bits filter coefficients. The proposed novel reconfigurable FIR filter architecture using dynamically reconfigurable multiplier block offers good area and speed improvement compared to existing reconfigurable FIR filter implementations.     

Complex coefficient fir digital filters

The complex FIR digital filter is a filter that has complex coefficients in itsZ-domain transfer function. The set of coefficients is determined, based on some criterion, to meet predefined requirements. On this basis, an algorithm is proposed for designing FIR digital filters with asymmetric amplitude response in conjunction with linear phase. Minimax approximation has been adopted for determining the set of coefficients, where the associated set of overdetermined linear equations is solved by using an efficient linear programming algorithm. Computer simulations show that, to meet prescribed specifications, the proposed design algorithm yields a complex FIR digital filter with the lowest order.     

Design of zero-phase recursive 2-D variable filters with quadrantal symmetries

The digital filters with adjustable frequency-domain characteristics are called variable filters. Variable filters are useful in the applications where the filter characteristics are needed to be changeable during the course of signal processing. In such cases, if the existing traditional constant filter design techniques are applied to the design of new filters to satisfy the new desired characteristics when necessary, it will take a huge amount of design time. So it is desirable to have an efficient method which can fast obtain the new desired frequency-domain characteristics. Generally speaking, the frequency-domain characteristics of variable filters are determined by a set of spectral parameters such as cutoff frequency, transition bandwidth and passband width. Therefore, the characteristics of variable filters are the multi-dimensional (M-D) functions of such spectral parameters. This paper proposes an efficient technique which simplifies the difficult problem of designing a 2-D variable filter with quadrantally symmetric magnitude characteristics as the simple one that only needs the normal one-dimensional (1-D) constant digital filter designs and 1-D polynomial approximations. In applying such 2-D variable filters, only varying the part of 1-D polynomials can easily obtain new desired frequency-domain characteristics.     

Framework for Digital Filter Design Optimization (DiFiDOT) using MCM Based Register Minimization Retiming for Noise Removal ECG Filters

In all the DSP(Digital Signal Processing) blocks such as digital filters, the filter coefficients are known before hand. Hence, full flexibility of the multiplier is not necessary. Multiplierless Multiple Constant Multiplication(MCM) technique can be used along with retiming for better digital filter optimization.This method is more efficient when compared to shift and add multiplications as intermediate results in MCM technique can be shared which reduces the area of multiplierless implementation of digital filters. The multiplierless filter circuit is further retimed to reduce the overall clock period which increases the clock frequency. Critical path and shortest path computations consume most of the time in retiming computation. The retiming minimizes the overall clock period by reducing the filter critical path. In the general purpose processor where actual retiming vectors are computed for digital filters, the speed with which the retiming transformation is performed suffers as the entire transformation code will be written in the form of a soft core. Hence, FPGA based path solver architecture are proposed in this paper can reduces the burden on general purpose processors while retiming. This work contributes to reduced processing time for retiming using FPGA based path solvers. Due to complexity and transistor size reduction, designing of VLSI architectures for DSP blocks has become very challenging. Automated Tools are required most often to introduce the products to market in a timely manner and to make the VLSI designs more stable, reliable and tractable. A framework called DiFiDOT(Digital Filter Design Optimization Tool) is developed in this work for synthesizing the optimized filter architectures. Finally, an application for Electrocardiography(ECG) is designed using MCM based retimed digital filters to remove the power supply interference, baseline drift and the broadband noise from the ECG signal.     

Time-varying performance surfaces for adaptive IIR filters:geometric properties and implications for filter stability

We present a new framework for understanding the performance of adaptive IIR filters which enhances the understanding of filter stability during on-line operation. This new understanding arises from examining geometric properties of time-varying performance surfaces which are defined by the data, rather than the standard steady-state error surfaces as defined by statistics of the data. Data-dependent descent directions used in adaptive algorithms to update filter coefficients typically are viewed as functions of gradients defined on fixed performance surfaces, and data is used to approximate these gradients at each iteration. In contrast, we view data-dependent descent directions at each iteration as functions of exact gradients on time-varying performance surfaces. By examining the shape of these time-varying performance surfaces near filter stability boundaries, we are able to identify the origin of on-line stability problems associated with existing adaptive IIR filtering formulations, and suggest corrective measures. Specifically, by using exact z-domain methods, we define time-varying performance surfaces which geometrically enforce filter stability, and maintain the geometric and physical properties of the “true” error surface at each iteration. Development of adaptive algorithms based on this measure is expected to result in adaptive filters having improved stability performance during on-line operation     

Design techniques for silicon compiler implementations ofhigh-speed FIR digital filters

Architecture design techniques for implementing both single-rate and multirate high throughput finite impulse response (FIR) digital filters are explored, with an emphasis on those which are applicable to automated integrated circuit layout techniques. Various parallel architectures are examined based on the criteria of achievable throughput versus hardware complexity. Well-known techniques for reduced complexity and computation time are briefly summarized, followed by the introduction of several new techniques which offer further gains in both throughput and circuitry reduction. An architecture for mirror-symmetric polyphase filter banks is derived which exploits the coefficient symmetry between multiple filters to reduce hardware. Finally, the evolution of a silicon compiler which utilizes all of these techniques is presented, and results are given for compiled filters along with comparisons to other compiled and custom FIR filter chips     

CSDC: a new complexity reduction technique for multiplierless implementation of digital FIR filters

We present a computation reduction technique called computation sharing differential coefficient (CSDC) method, which can be used to obtain low-complexity multiplierless implementation of finite-impulse response (FIR) filters. It is also applicable to digital signal processing tasks involving multiplications with a set of constants. The main component of our proposed CSDC method is to combine the strength of the augmented differential coefficient approach and subexpression sharing. Exploring computation reuse through algorithmic equivalence, the augmented differential coefficient approach greatly expands the design space by employing both differences and sums of filter coefficients. The expanded design space is represented by an undirected and complete graph. The problem of minimizing the adder cost (the number of additions/subtractions) for a given filter is transformed into a problem of searching for an appropriate subexpression set that leads to a minimal adder cost. A heuristic search algorithm based on genetic algorithm is developed to search for low-complexity solutions over the expanded design space in conjunction with exploring subexpression sharing. It is shown that up to 70.1% reduction in the adder cost can be obtained over the conventional multiplierless implementation. Comparison with several existing techniques based on the available data shows that our method yields comparable results for multiplierless FIR filter implementation.     

Efficient implementation of 3D filter for moving object extraction

In this paper the design and implementation of Multi-Dimensional (MD) filter, particularly 3-Dimensional (3D) filter, are presented. Digital (discrete domain) filters applied to image and video signal processing using the novel 3D multirate algorithms for efficient implementation of moving object extraction are engineered with an example. The multirate (decimation and/or interpolation) signal processing algorithms can achieve significant savings in computation and memory usage. The proposed algorithm uses the mapping relations of z-transfer functions between non-multirate and multirate mathematical expressions in terms of time-varying coefficient instead of traditional polyphase de- composition counterparts. The mapping properties can be readily used to efficiently analyze and synthesize MD multirate filters.