区域恶臭在线监控平台设计与实现

为提高恶臭污染管理水平和恶臭事件应急处理能力,填补国内区域恶臭在线监控体系建设的空白,提出了区域恶臭在线监控平台的整体设计方案。依据网络负载均衡和按需动态扩展的思想设计恶臭实时监测和远程监控两项功能。远程监控采用远程桌面协议(RDP)技术,实现参数调整、超限报警、分级采样等功能,同时设计一种基于高级加密标准(AES)及MD5数字签名技术的混合算法以弥补RDP的安全缺陷。平台已在天津市滨海新区大港石化产业园上线试运行,初步实现各项设计功能,为后续恶臭扩散模型研究和恶臭污染防控积累数据和经验,并为恶臭在线监测系统最终融入我国环保物联网做技术准备。     

Control of a Robotic Manipulator Using Artificial Neural Networks with On-line Adaptation

An adaptive neural system for positioning control of a PUMA 560 manipulator is presented". The computed torque method was implemented with a Multi-Layer Perceptron with on-line learning. The control scheme is implemented into two phases. The first one is the off-line phase in which the neural network is trained with previously known control actions. The second one is the on-line phase in which the neural network parameters are adapted while controlling the manipulator. The control system is able to respond to changes in the manipulator model and to load disturbances. As will be shown, control system performance is improved with the on-line learning strategy presented in this paper.     

基于时间延迟和掩码的抗DPA方法研究

针对时间延迟技术和掩码技术的不能完全抵御差分功耗攻击的不足,在研究差分功耗攻击防御方法的基础上,提出一种时间延迟和功耗随机化的电路结构,将其应用在AES算法中,并在FPGA开发板、示波器和PC机组成的功耗采集分析平台中进行了验证;通过DPA实验,结果表明,未加防护的AES加密算法IP核能被成功攻击,而增加时间延迟和掩码防护的AES IP核具有抗DPA攻击防护能力;文章的研究方法和思路可为功耗攻击防御研究提供一定的借鉴和参考。     

AES算法的一种快速实现方法

对称算法AES轮变换所包含的子函数ShiftRows（State）是一个字节换位的操作,它将第i行第j列的字节移到第i行第列的位置（j-c1）modN（c1为第i行要移动的偏移量）。因此,在实现AES算法时,可将ShiftRows（State）和MixColumns（State）合并成一个函数完成。用VC＋＋6.0实现了这个算法,且验证了改进后的AES算法在速度方面优于传统的AES算法。     

一种低硬件开销的高级加密标准设计

在智能卡、PDA等便携式设备中,希望使用面积小的密码芯片。通过对AES算法进行结构优化,有效地减小了硬件实现时的开销。使用Verilog HDL语言设计并在Altera APEX20K器件中验证通过,设计集成了加密／解密模式及所有3种密钥长度,为进一步的VLSI实现提供了FPGA原形验证。     

A high-speed AES design resistant to fault injection attacks

To secure the Advanced Encryption Standard against physical attacks known as fault injection attacks, different countermeasures have been proposed. The AES is used in many embedded systems to provide security. It has become the default choice for security services in numerous applications. However, the natural and malicious injected faults reduce its robustness and may cause private information leakage. In this paper, we study the concurrent fault detection schemes for achieving a reliable AES implementation. We specifically propose a new fault detection scheme based on modification of the AES architecture. For this purpose, the round AES transformation is broken into two parts and a pipeline stage is inserted in between.The proposed scheme is independent of the way the S-Box and the Inv_S-Box are implemented. Hence, it can be used for both the S-Box and the Inv_S-Box using Look-Up Table and those using logic gates based on Galois Fields. Our simulation results show the fault coverage reaches 98.54% for the proposed scheme. Moreover, the proposed and the previously reported fault detection schemes have been implemented on the most recent Xilinx Virtex FPGAs. Their area overhead, the frequency and throughput have been compared and it is shown that the proposed fault detection scheme outperform the previously reported ones.     

智能卡中抗高阶功耗攻击AES算法实现技术

在提取AES算法中各种变换的公共操作的基础上,定义相应的基于随机掩码的原子操作,并以硬件方式实现。将AES算法中各种变换转换为随机掩码原子操作的序列,密码算法运算过程中使用不同的随机量对所有中间结果进行掩码。在此基础上,以软硬件结合的方式实现AES算法,掩码的原子操作以硬件方式实现,而运算流程控制以软件方式实现;并且结合运算流程随机化技术进一步提高实现的安全性。安全分析表明,这种实现技术可以抗一阶功耗攻击和高阶功耗攻击。实验结果表明,所提出的AES算法实现方法的硬件实现开销较小,并且具有高安全性,适合于智能卡实现。     

AES算法在配送物资跟踪系统中的应用

针对配送物资跟踪系统中RFID标签的相关限制,设计了基于AES算法的数据加密方法.实现了AES算法的相关程序,对AES算法应用于配送物资跟踪系统进行了相关的安全性分析.     

针对AES的基于时间的缓存攻击

基于时间的缓存攻击是指通过分析处理器中算法的不同执行时间来恢复密钥的攻击。该文分析针对AES的时间驱动缓存攻击,给出一种改进的攻击,它可以应用于大多数的AES实现软件。在PentiumⅢ, OpenSSL v.0.9.8.(a)和Miracl环境下的实验发现,只需要224个时间信息就可以恢复出密钥,少于原攻击的228个时间信息数据。给出抵抗这种攻击的对策。     

AES算法的并发错误检测方法及其VLSI实现

提出了一种AES算法的抗差分差错分析的并发错误检测方法--二维奇偶校验方法.与原有的一维奇偶校验方法相比,该方法提供了更为优化的奇偶校验位设置,更重要的是能够同时检测水平和垂直方向上的奇数个错误,在保持了对单个错误的100%的覆盖率的同时,将对多个错误的覆盖率大大提升.由于水平和垂直校验位计算模块可以复用,因此与原有的一维奇偶校验方法相比,该方法增加的硬件开销很小,对硬件实现的关键路径和吞吐率都没有影响,是一种理想的低成本高效率的抗差分差错分析的并发错误检测方法.     

针对SoC系统的Cache攻击方法及建模分析

针对SoC平台,提出并实现了一种高效的基于Cache的AES旁道攻击方法.该方法利用AES软件运行过程中查找表操作泄漏的时间信息,结合AES算法前两轮的特征,快速确定攻击表与AES查找表间的映射关系,并最终恢复出全部128b密钥.基于此攻击方法,在充分考虑各种系统噪声影响的情况下,进一步提出了一种统计分析模型.该模型揭示了上述攻击方法的内在机理,并能够较为准确地估算攻击所需的最小样本数.该模型的重要意义在于不仅可以用来衡量特定SoC系统的抗攻击能力,同时为抗攻击研究指明了方向.     

KIM PHILBY,THE AMERICAN INTELLIGENCE COMMUNITY,AND OP-20-G: THE FOX BUILT THE HEN-HOUSE AND TOOK THE KEYS

Abstract

Lester S. Hill, who is known for the polygraphic cipher that he published in 1929, published three papers about error-detecting codes in 1926 and 1927, and he and Louis Weisner submitted a patent application for an error-detection machine in 1929. Hill's error-detection schemes of the 1920s were based upon number theory and matrix multiplication, and one of Hill's error-detecting codes essentially includes the encoding method for linear error-correcting codes, which was developed two decades later by Richard Hamming.     

抗DPA攻击的AES算法研究与实现

Mask技术破坏了加密过程中的功率消耗与加密的中间变量之间的相关性,提高了加密器件的抗DPA攻击能力。简单地对算法流程添加Mask容易受到高阶DPA攻击的。提出了一种对AES加密过程的各个操作采用多组随机Mask进行屏蔽的方法,并在8bit的MCU上实现了该抗攻击的AES算法。实验结果表明,添加Mask后的抗DPA攻击AES算法能够有效地抵御DPA和高阶DPA的攻击。     

基于小型FPGA的快速AES算法研究

AES算法在实时数据加密中的应用对其处理速度及在FPGA中实现的功耗和成本提出较高要求。针对上述情况,介绍一种基于小型FPGA的快速AES算法的改进方法,通过微处理器完成AES算法中的密钥扩展运算,同时采用共享技术实现加密和解密模块共享同一密钥。实验结果表明,该方法可有效提高处理速度,节省FPGA资源,降低芯片功耗。     

密钥管理系统在数字电影播放中的实现

高级内容访问系统(AACS)是蓝光光盘和HD DVD采用的安全标准。该文通过剖析AACS,提出使用软件解密的多处漏洞,给出以AES算法为核心的密钥管理系统(SMS)。该解密系统采用硬件实时解密,已经在数字电影服务器中使用,可以有效避免软件解密的多种问题。密钥管理系统还采取了额外的措施保护固化的密钥。     

基于随机掩码的AES算法抗DPA攻击硬件实现

该文提出了一种基于随机掩码的抗DPA（Differential Power Analysis）攻击的AES算法硬件实现方案。基于随机掩码的AES算法实现中最为关键之处就是唯一的非线性变换即S盒（SubBytes）的实现,该文将S盒中有限域GF（28）上的求逆转换到GF（24）和GF（22）上进行,有效实现了掩码防护。在该文的实现中,所有的中间结果均被随机掩码,证明了该文中AES算法实现能够抗DPA攻击,基于此掩码方案,给出了AES协处理器体系结构,设计实现128密钥的AES协处理器。在0.18μm工艺下,协处理器面积为0.298mm2 在100MHz频率下,加解密吞吐率达到了1.16Gbps。     

组合预测在分销系统辅助决策中的应用

高级内容访问系统(AACS)是蓝光光盘和HD DVD采用的安全标准.该文通过剖析AACS,提出使用软件解密的多处漏洞,给出以AES算法为核心的密钥管理系统(SMS).该解密系统采用硬件实时解密,已经在数字电影服务器中使用,可以有效避免软件解密的多种问题.密钥管理系统还采取了额外的措施保护固化的密钥.     

AES算法的CUDA高效实现方法

针对AES算法的ECB工作模式安全性低的弱点, 提出了一种新的ECB工作模式, 并在GPU最新统一计算设备架构(CUDA)下进行了实现。具体并行实现包括线程组织、数据存储结构以及共享内存的性能优化技术。实验结果表明这种新模式增强了AES算法的性能和安全性, 与传统CPU实现相比, 利用 CUDA能够实现显著的加速性能。     

Power dissipation and area comparison of 512-bit and 1024-bit key AES

Advanced Encryption Standard (AES) has replaced its predecessor, Double Encryption Standard (DES), as the most widely used encryption algorithm in many security applications. Up to today, AES standard has key size variants of 128, 192, and 256-bit, where longer bit keys provide more secure ciphered text output. In the hardware perspective, bigger key size also means bigger area and power consumption due to more operations that need to be done. Some companies that employ ultra-high security in their systems may look for a key size bigger than 256-bit AES. In this paper, 128 and 256-bit AES hardware, as well as two variants of an AES encryption algorithm for 512-bit and 1024-bit key size, are implemented and compared in terms of power consumption and area. The experiment is done in 45 nm CMOS technology at 1.1 V using a Synopys DC Compiler and Modelsim and total power consumption and area results are presented and graphically compared.     

Robust robot control with bounded input torques

A new scheme is presented to achieve effective on-line tracking control of robot manipulators in the presence of model uncertainty and torque limitations. Pointwise optimization techniques are incorporated into a “slow” feedback loop in order to generate feasible desired trajectories, optimally close to the original desired trajectories. A suction controller is used in the “fast” main feedback loop, allowing to combine robust tracking with simple controller design. Simulations show very significant performance improvement over standard techniques. The algorithm is computationally cheap and can easily be implemented on-line.