TiO2-poly(4-vinylphenol) nanocomposite dielectrics for organic thin film transistors

We report on the fabrication of organic thin film transistors (OTFTs), which operate at low voltages, by incorporating a nanocomposite gate insulator material consisting of titania (TiO₂) nanoparticles used as fillers and poly(4-vinyl phenol) (PVP) used as matrix. The surface of the nanoparticles was modified by the ligands, 4-hydroxybenzoic acid, to enhance their compatibility with the polymer. The structure of the ligand is similar to that of the repeat units in the polymer. Once the nanoparticles were homogeneously dispersed in the polymer matrix, they were immobilized by cross-linking PVP with poly(melamine-co-formaldehyde) methylated/butylated (cross-linker). Consequently, no significant aggregation of the nanoparticles, even at a concentration of 31 wt%, was found in the nanocomposites, as observed by transmission electron microscopy (TEM). As a result, the nanocomposite exhibited a low leakage current density (∼10⁻⁸ A/cm⁻²). With an increase in the concentration of TiO₂ nanoparticles added, the dielectric constant of the nanocomposites also increased proportionately as compared to that of pristine PVP. The performance of the OTFTs in terms of the charge carrier mobility, on/off ratio, threshold voltages, and hysteresis was evaluated. In addition, the relationship between the concentration of TiO₂ nanoparticles and the device performance is discussed in detail.     

Top gate ZnO-Al2O3 thin film transistors fabricated using a chemical bath deposition technique

ZnO thin films were prepared by a simple chemical bath deposition technique using an inorganic solution mixture of ZnCl₂ and NH₃ on glass substrates and then were used as the active material in thin film transistors (TFTs). The TFTs were fabricated in a top gate coplanar electrode structure with high-k Al₂O₃ as the gate insulator and Al as the source, drain and gate electrodes. The TFTs were annealed in air at 500 ℃ for 1 h. The TFTs with a 50 μm channel length exhibited a high field-effect mobility of 0.45 cm²/(V·s) and a low threshold voltage of 1.8 V. The sub-threshold swing and drain current ON-OFF ratio were found to be 0.6 V/dec and 10⁶, respectively.     

Top-gate organic field-effect transistors fabricated on paper with high operational stability

We report on top-gate organic field-effect transistors (OFETs) fabricated on specialty paper, PowerCoat™ HD 230 from Arjowiggins Creative Papers coated with a buffer layer composed of a polyvinyl alcohol (PVA) and polyvinylpyrrolidine (PVP) blend. OFETs operate at low voltages and display average carrier mobility values of 1.7 ± 1.1 × 10⁻¹ cm²/Vs, average threshold voltage values of −1.4 ± 0.2 V, and average on/off current ratio of 10⁵. OFETs also display excellent operational stability demonstrated by stable 1000 scans of the transfer characteristics and by stable on-currents displaying less than 6% change during a DC bias stress test at V_DS = V_GS = −10 V for 1 h. Furthermore, OFETs on paper display a decrease of only 7% in their on-state current during a bending test. The performance of these OFETs on paper is comparable to that displayed by top-gate OFETs with the same geometry fabricated on glass substrates.     

Inserting a Mn-doped TiO2 layer for improving performance of pentacene organic thin-film transistors

Device performance of pentacene organic thin-film transistors (OTFTs) was significantly improved via inserting a Mn-doped TiO₂ layer between pentacene semiconductor and the source–drain electrodes. In comparison with the OTFTs with only-Au electrodes, the introduction of a thin Mn-doped TiO₂ layer leads to saturation current increasing from 31.9 μA to 0.22 mA, effective field-effect mobility improving from 0.24 to 1.13 cm²/V s, and threshold voltage downshifting from −11 to −2 V. These performance enhancements are ascribed to the significant reduction of contact resistance and smoothed surface of pentacene layer. This work may provide an effective approach to improve the performance of the pentacene based OTFTs by inserting a Mn-doped TiO₂ layer.     

Design and fabrication of a novel high damage threshold HfO2/TiO2/SiO2 multilayer laser mirror

This paper describes a new method to design a laser mirror with high reflectivity, wide reflection bandwidth and high laser-induced damage threshold. The mirror is constructed by three materials of HfO2/TiO2/SiO2 based on electric field and temperature field distribution characteristics of all-dielectric laser high reflector. TiO2/SiO2 stacks act as the high reflector (HR) and broaden the reflection bandwidth, while HfO2/SiO2 stacks are used for increasing the laser resistance. The HfO2/TiO2/SiO2 laser mirror with 34 layers is fabricated by a novel remote plasma sputtering deposition. The damage threshold of zero damage probability for the new mirror is up to 39.6 J/cm2 (1064 nm, 12 ns). The possible laser damage mechanism of the mirror is discussed.     

Fully isolated lateral bipolar—MOS transistors fabricated in zone-melting-recrystallized Si films on SiO2

A four-terminal device that can be operated either as a lateral n-p-n bipolar transistor or as a conventional n-channel MOSFET has been fabricated in silicon-on-insulator films prepared by graphite-strip-heater zone-melting recrystallization. Common-emitter current gain close to 20 and emitter-base breakdown voltage in excess of 10 V have been obtained for bipolar operation. As a MOSFET, the device exhibits well-behaved enhancement-mode characteristics with a field-effect mobility of ∼ 600 cm²/V.s and drain breakdown voltage exceeding 15 V.     

The observation of negative transconductance effect caused byreal-space-transfer of electrons in metal oxide semiconductor fieldeffect transistors fabricated with Ta2O5 gatedielectric

N-channel metal oxide semiconductor field effect transistors (MOSFETs) with Ta₂O₅ gate dielectric were fabricated. An intrinsic Ta₂O₅/silicon barrier height of 0.51 eV was extracted from the gate current. The effective Ta ₂O₅/silicon barrier height including image force barrier lowering is about 0.37 eV with drain to source voltage V_DS ranging from 1.5 V to 4.0 V. Due to the low barrier height, negative transconductance effect was observed in the linear region. The decrease of drain current is due to the real space transfer of electrons from the drain terminal to the gate electrode     

Linear compatible I/SUP 2/L technology with high voltage transistors

A technology is proposed in which it is possible to realize both I/SUP 2/L circuits and linear transistors with V/SUB CBO/ of 60 V. The essential step in such a technology is an additional n/SUP +/-flat diffusion. The technological parameters are derived. From measurements on wafers processed in the outlined technology. The author established functioning I/SUP 2/L elements and high voltage transistors.     

MOS transistors with stacked SiO2-Ta2O5-SiO2 gate dielectrics for giga-scale integration ofCMOS technologies

Advances in lithography and thinner SiO₂ gate oxides have enabled the scaling of MOS technologies to sub-0.25-μm feature size. High dielectric constant materials, such as Ta₂O₅ , have been suggested as a substitute for SiO₂ as the gate material beyond t_ox≈25 Å. However, the Si-Ta ₂O₅ material system suffers from unacceptable levels of bulk fixed charge, high density of interface trap states, and low silicon interface carrier mobility. In this paper we present a solution to these issues through a novel synthesis of a thermally grown SiO₂(10 Å)-Ta₂O₅ (MOCVD-50 Å)-SiO₂ (LPCVD-5 Å) stacked dielectric. Transistors fabricated using this stacked gate dielectric exhibit excellent subthreshold behaviour, saturation characteristics, and drive currents     

High-performance enhancement-mode GaN-based p-FETs fabricated with O3-Al2O3/HfO2-stacked gate dielectric

In this letter, an enhancement-mode(E-mode) GaN p-channel field-effect transistor(p-FET) with a high current density of-4.9 mA/mm based on a O₃-Al₂O₃/HfO₂(5/15 nm) stacked gate dielectric was demonstrated on a p⁺⁺-GaN/pGaN/AlN/AlGaN/AlN/GaN/Si heterostructure. Attributed to the p⁺⁺-GaN capping layer, a good linear ohmic I-V characteristic featuring a low-contact resistivity(ρc) of 1.34 × 10^-4 Ω·cm² was obtain...     

Mechanism and Development of TiO2-Doped ZnO-Bi2O3-Based Varistors

This paper reviews the history of ZnO varistor, discribes its properties and recent technological status and forecasts its evolution. The future development trend is to produce the low-voltage high-energy multi-layer ZnO varistors. After the two additives are classified by their functions, the effect mechanism of Bi2O3 and TiO2 additives are researched theoretically. TiO2 will make ZnO grain grow bigger and V1mA/mm be depressed down. Especially the colloid TiO2 additive in the scale of nanometer brings about a new method to realize the low voltage of ZnO varistor, which resolves the problem of how to disturb nanometer powder evenly. Moreover the sintering temperature has prominent effect on the electrical properties of ZnO varistors. Generally, the appropriate sintering temperature for low-voltage ZnO varistor ceramics should not be more than 1 250℃. These provide an effective method and rationale for studying low-voltage ZnO varistors.     

Study of LDPE/TiO2 and PS/TiO2 Composites as Potential Substrates for Microstrip Patch Antennas

Low-density polyethylene (LDPE)/titania (TiO₂) and polystyrene (PS)/titania (TiO₂) composite systems have been developed as alternative substrates for microstrip patch antennas (MPA) for handheld devices. Morphological, thermal, and microwave characterizations of these composites have been conducted for different volume fractions of TiO₂ in the polymer matrix. The size of the titania particles was found to be of the order of 0.5 μm, and their distribution in the composite was quite uniform. Composite materials showed an improvement in thermal and microwave properties over the parent polymer. Verification of these composites as potential substrates for MPA was carried out by fabricating simple rectangular patch X-band antennas. Materials with optimized substrate properties were chosen to design the MPA. The patches were designed with 4% volume fraction TiO₂ in the LDPE composite system and 6% volume fraction TiO₂ in the PS composite system. Return loss of ∼18 dB was observed for both systems.     

Simulation of a high performance MOSFET with a quantum wirestructure incorporating a periodically bent Si-SiO2 interface

A MOSFET using a serrated quantum wire structure that produces one-dimensional electron confinement shows excellent subthreshold characteristics and enhanced drive capability compared to a conventional MOSFET with a flat Si-SiO₂ interface. We studied the quantum wire structure with its periodically bent Si-SiO₂ interface using simulations. The potential in the convex regions of the silicon is 0.34 V higher than that in the concave ones when the bending angle is 90°, the bending period is 100 nm, substrate doping is 3.0×10 ¹⁷ cm^-3, and a gate voltage is 0.1 V. Because of this increase in potential in the convex regions, electrons are confined in a narrow width of 13 nm in the convex regions. This 1-D electron confinement effect by the bent Si-SiO₂ interface is clearly observed at low gate voltage and is reduced as the gate voltage becomes higher. Due to the confinement effect, drain current in the MOSFET with this quantum wire structure is 270 times higher than that of a MOSFET with a flat Si-SiO₂ interface at a gate voltage of 0.05 V. In addition, the short-channel effect is more effectively suppressed in this MOSFET than in a conventional MOSFET     

Modelling of nanostructured TiO2-based memristors

The fourth fundamental circuit element memristor completes the missing link between charge and magnetic flux. It consists of the function of the resistor as well as memory in nonlinear fashion. The property of the memristor depends on the magnitude and direction of applied potential. This unique property makes it the primitive building block for many applications such as resistive memories, soft computing, neuromorphic systems and chaotic circuits etc. In this paper we report TiO2-based nanostructured memristor modelling. The present memristor model is constructed in MATLAB environment with consideration of the linear drift model of memristor. The result obtained from the linear drift model is well matched with earlier reported results by other research groups.     

Ta2O5/silicon barrier height measured fromMOSFETs fabricated with Ta2O5 gate dielectric

N-channel metal oxide semiconductor field effect transistors with Ta₂O₅ gate dielectric were fabricated. The Ta₂O₅/silicon barrier height was calculated using both the lucky electron model and the thermionic emission model. Based on the lucky electron model, a barrier height of 0.77 eV was extracted from the slope of the ln(I_g/I_d) versus ln(I_sub/I_d) plot using an impact ionization energy of 1.3 eV. Due to the low barrier height, the application of Ta₂ O₅ gate dielectric transistors is limited to low supply voltage preferably less than 2.0 V     

用Tl_2SO_4制造玻璃光波导

本文报道了用TI盐(TI_2SO_4)离子交换法制备玻璃光波导的实验结果。与用AgNO_3离子交换制备的光波导相比,波导损耗较低,折射率分布呈准阶跃型,拟合确定其折射率分布函数为费米函数,折射率增量Δn>0.13。     

Film properties of MoSi2and their application to self-aligned MoSi2gate MOSFET

Molybdenum silicide (MoSi2) gate technology has been extensively investigated in conjunction with MOS device performance and reliability. Features of the MoSi2gate technology are to realize a low resistivity of 1 × 10^-4Ω . cm for both gate and interconnection, and to give rise to higher reliability under both positive and negative bias stress of 2 MV/cm at 250° C. Problems on the ohmic contact between MoSi2and single-crystal substrates are not completely solved yet, particularly when the device is processed at high temperature after MoSi2deposition.     

Photoelectrochemical performance of La3+-doped TiO2

La-doped TiO₂ thin films on titanium substrates were prepared by the sol-gel method with titanium tetrachloride as a precursor and La₂O₃ as a source of lanthanum. The heat-treatment temperature dependence of the photoelectrochemical performance of the La-doped TiO₂ film in 0.2 mol/L Na₂SO₄ was investigated by the Mott-Schottky equation, electrochemical impedance spectroscopy, and the open-circuit potential test. The results from the Mott-Schottky curves show that the obtained films all were n-type semiconductors, and the film at 300 ℃ had the highest conduction band position and the widest space charge layer. The electrochemical impendence spectroscopy (EIS) tests of the 300 ℃ film decreased most during the change from illuminated to dark. The potential of the La-TiO₂ thin film electrode was the lowest after the 300 ℃ heat treatment. The open-circuit potential indicated that the photoelectrical performance of the La-TiO₂ films was enhanced with the addition of the La element and the largest decline (837.8 mV) in the electrode potential was achieved with the 300 ℃ heat treatment.     

Electrical measurements of voltage stressed Al2O3/GaAs MOSFET

Electrical characteristics of GaAs metal–oxide–semiconductor field effect transistor with atomic layer deposition deposited Al₂O₃ gate dielectric have been investigated. The IV characteristics were studied after various constant voltage stress (CVS) has been applied. A power law dependence of the gate leakage current (I_g) on the gate voltage (V_g) was found to fit the CVS data of the low positive V_g range. The percolation model well explains the degradation of I_g after a high positive V_g stress. A positive threshold voltage (V_th) shift for both +1.5 V and +2 V CVS was observed. Our data indicated that positive mobile charges may be first removed from the Al₂O₃ layer during the initial CVS, while the trapping of electrons by existing traps in the Al₂O₃ layer is responsible for the V_th shift during the subsequent CVS.     

Magnetron-sputtered high performance Y-doped ZnO thin film transistors fabricated at room temperature

In this report, sputtered-grown undoped ZnO and Y-doped ZnO (ZnO:Y) thin film transistors (TFTs) are presented. Both undoped ZnO and ZnO:Y thin films exhibited highly preferred c-axis oriented (002) diffraction peaks. The ZnO:Y thin film crystallinity was improved with an increase of (002) peak intensity and grain size. The electrical properties of ZnO:Y TFTs were significantly enhanced relative to undoped ZnO TFTs. ZnO:Y TFTs exhibited excellent performance with high mobility of 38.79 cm² V⁻¹ s⁻¹, small subthreshold swing of 0.15 V/decade, and high I_on/I_off current ratio of the order of 8.17 × 10⁷. The O_1s X-ray photoelectron spectra (XPS) showed oxygen vacancy-related defects present in the ZnO:Y TFTs, which contributed to enhancing the mobility of the TFTs.