CMOS射频集成电路的最新进展和应用

本文介绍RF(射频)CMOS集成电路的最新进展和应用.着重于深亚微米CMOS技术在实现高端射频(几十GHz频带)集成系统方面的潜能.首先,综述CMOS技术的主要特点,继而介绍CMOS射频集成电路的最新进展.其中有63GHz的毫米波段的CMOS压控振荡器,数据速率达50Gb/s的2:1多路复用器,40GHzCMOS低功耗注入锁定分频器,24GHzCMOS射频前端和17GHzISM/WLAN的CMOS射频前端等.同时,介绍CMOS射频集成电路的几种主要应用,如无线局域网和射频识别等.     

CMOS分数频率综合器设计技术

现代无线通信要求频率综合器同时满足快速切换时间，小信道宽度和低噪声性能三方面的要求。分数N频率综合器在这方面的优良特性使得它在现代无线通信系统中被广泛使用。文章系统地讨论了用CMOS工艺实现分数频率综合器的技术问题，并对频率综合器的发展方向和面临的挑战提出了一些看法。     

无线应用CMOS低噪声放大器的设计

基于射频CMOS集成电路技术, 设计出用于无线通信系统的CMOS低噪声放大器.对影响其增益、噪声系数的阻抗匹配进行了分析.采用TSMC的0.35 μm射频工艺库,在ADS仿真平台上对低噪声放大器电路进行了仿真.其中,低噪声放大器设计成差分结构,提供了13 dB增益、-10 dBm IIP3、-13 dBm P1dB、1.9 dB的噪声系数和55 mW的功耗.     

用于超宽带无线通信系统的CMOS射频混频器的设计

基于射频CMOS集成电路技术,设计出用于超宽带无线通信系统的CMOS下变频器。讨论了利用电容电感网络进行窄带电路阻抗匹配和电阻网络进行宽带电路阻抗匹配的思想和方法。调用SMIC的0．25μm射频工艺库在HSPICE仿真平台上对混频器电路进行了仿真,并对输出信号进行了频谱分析,仿真了该电路的关键技术参数。模拟结果和仿真参数验证了该混频器电路的正确性和可实现性。     

CMOS射频集成电路中器件模型的研究

采用硅材料CMOS工艺制造的射频集成电路具有低功耗、低成本和容易集成的优点.文章讨论了CMOS射频集成电路设计和制造中起关键作用的MOSFET高频模型和螺旋电感模型.为了验证模型,介绍了射频集成电路中的核心模块-低噪声放大器(LNA)-的设计实例.测试结果表明,该模型具有高效、实用的特点.     

一种基于0.18μm CMOS工艺用于卫星导航系统射频前端双模低噪声放大器设计

本文介绍了一种用于全球卫星导航系统射频前端的双频点低噪声放大器的设计,讨论了针对双频点或多频点的低噪声放大器的设计方法,分析了具体的电路设计和相关参数的确定并进行仿真.采用台积电0.18um 1P4M射频CMOS工艺进行流片验证,低噪声放大器噪声特性可分别在两个频点1.27GHz和1.575GHz处达到16.8dB和18.9dB,实测噪声系数可达1.5dB~1.7dB之间.此结构在1.8V工作电压下,电流小于4.3mA.流片结果与原设计情况相符,完全满足射频前端接收机的需求.     

一款应用于GPS的CMOS低功耗高增益LNA

针对当前应用于GPS射频前端的LNA存在的不足,设计了一种新型的LNA.从电路结构、噪声匹配、线性度、阻抗匹配、电压增益以及功耗等方面详细讨论了该低噪声放大器的设计.电路采用CMOS 0.18μm工艺实现,经过测试,低噪声放大器的增益为40.8dB,噪声系数为0.525dB,PldB为-29.5dBm,1.8V电压下的消耗电流仅为1.4mA.电路性能充分满足应用要求.     

2.9GHz 0.35μm CMOS低噪声放大器

随着特征尺寸的不断减小,深亚微米CMOS工艺其MOSFET的特征频率已经达到50Hz以上,使得利用CMOS工艺实现GHz频段的高频模拟集成电路成为可能,越来越多的射频工程师开始利用先进的CMOS工艺设计射频集成电路,本文给出了一个利用0．35μmCMOS工艺实现的2．9GHz单片低噪声放大器,放大器采用片内集成的螺旋电感实现低噪声和单片集成。在3伏电源下,工作电流为8mA,功率增益大于10dB,输入反射小于－12dB.     

一种基于0.18μm CMOS工艺的智能传感器网络节点设计与实现

针对当前无线监测网络节点存在无线通信距离小、数据传输周期短等问题,设计并实现了一种基于0.18 μm CMOS工艺的智能传感器网络节点.该无线传感器网络节点由无线传感器模块、CC2430处理器模块、无线通信模块以及电源模块构成.其中,CC2430处理器模块采用0.18 μm CMOS工艺控制电流损耗和模式变换时间,提高电源的运行周期,并采用0.18 μm CMOS工艺中低噪声放大器和UQ下变频对天线采集的射频信号进行操作,获取2.4 GHz的数据扩频,增强CC2420的无线通信抗干扰性能.设计了无线传感器网络节点中的SHTIO温湿度传感器、MS5534B集成压阻式压力传感器和ADXL202E双轴加速度传感器,并给出节点软件的结构和主程序流程.实验检测结果表明,设计的无线传感器网络具备较优的运行性能,丢包率较低,通信距离与运行周期明显优于传统方法.     

应用于GSM/EDGE零中频接收机的CMOS射频前端

介绍了一个零中频接收机CMOS射频前端,适用于双带(900MHz/1800 MHz)GSM/EDGE;E系统.射频前端由两个独立的低噪声放大器和正交混频器组成,并且为了降低闪烁噪声采用了电流模式无源混频器.该电路采用0.13 μm CMOS工艺流片,芯片面积为0.9 mm×1.0 mm.芯片测试结果表明:射频前端在90...     

CMOS射频集成电路的研究进展

近年来，射频集成电路(RFIC)的应用和研究得到了飞速的发展，CMOS射频IC的研究更是成为该领域的研究重点和热点。文章对CMOS技术在射频和微波领域的应用进行了详细的探讨，着重介绍了当前射频通讯中常用的收发机结构及其存在的问题和解决方案；分析了射频收发机前端关键电路模块低噪声放大器(LNA)、混频器(Mixer)、压控振荡器(VCO)、功率放大器(PA)和射频关键无源元件的最新研究进展；展望了CMOS技术在射频领域的发展前景。     

A 900-MHz fully integrated SOI power amplifier for single-chipwireless transceiver applications

This paper presents a silicon-on-insulator (SOI) fully integrated RF power amplifier for single-chip wireless transceiver applications. The integrated power amplifier (IPA) operates at 900 MHz, and is designed and fabricated using a 1.5-μm SOI LDMOS/CMOS/BJT technology. This technology is suitable for the complete integration of the front-end circuits with the baseband circuits for low-cost low-power high-volume production of single-chip transceivers. The IPA is a two-stage Class E power amplifier. It is fabricated along with the on-chip input and output matching networks. Thus, no external components are needed. At 900 MHz and with a 5-V supply, the power amplifier delivers 23-dBm output power to a 50-Ω load with 16-dB gain and 49% power-added efficiency     

A 2 MHz Wireless CMOS Transceiver for Implantable Biosignal Sensing Systems

An implementation of an implantable sensing biosystem composes of a readout circuit, a power management block, an embedded microcontroller unit (MCU), an implantable drug delivery section and a wireless uplink transceiver system. This paper describes a bi-directional wireless transceiver system for implantable sensing systems. The transceiver system is composed of an external and implantable transceiver, communicating through an inductive link. Half duplex communication between transceivers at a 10 Kbps data rate was achieved at a maximum distance of 4 cm. Command and data will be supplied to the implantable module by radio frequency (RF) telemetry utilizing an amplitude shift keying (ASK) modulated 2 MHz carrier frequency. A capacitor-less amplitude demodulation receiver architecture was produced in the research with implantable receiver core area measuring at 113.2 μm by 171.8 μm with average power dissipation at 815.1 μW at a 3.3 V single rail power supply. An active uplink transceiver utilizing load shift keying (LSK) as backward data telemetry was designed. Implantable transmitter core area measures 251.7 μm by 139.3 μm, consuming 103.62 mW while driving an RF ferrite core antenna at maximum reading range. Integrating both circuits, implantable transceiver, measuring 355.3 μm by 171.8 μm, was designed and implemented using TSMC 0.35 μm mixed-signal 2P4M 3.3 V standard CMOS process. The integrated circuit solution addressed solutions for many of the problems associated with implanted devices and introduces circuits which improve in several ways over previously published designs, in functionality and integration level. In addition to being fully integrated in plain CMOS technology, not relying at least partly on available specialized elements and expensive technologies, these building blocks improve on previous designs in performance and/or power consumption. This work succeeded in implementing building blocks for an implantable transceiver, which depends only on the absolute minimum off-chip components. A complete implantable chip is presented, which highlight the design tradeoffs and optimizations applied to the design of CMOS implantable system chips.     

RF and AMS

The paper shows four basic circuit functions which are RF transceiver, AMS, power amplifier (PA) and power management (PM), and digital signal processor (DSP). In this article, the authors emphasize the first three circuit functions, which drive analog and RF technology needs. Each of those three major parts in a RF front-end for a wireless system are discussed in a separate section with special emphasis on the device needs and technology choices for those blocks and with main focus on the frequency range from 0.8 to 10 GHz. A section on millimeter wave circuits and devices cover device and technology integration issues for applications in the frequency range starting from 10-100 GHz. Finally, we discuss the evolution of technology choices, integration issues, and potentially new emerging devices, all within the time-frame for the 2003 ITRS roadmap (2003-2018).     

Low-Power Analog Integrated Circuits for Wireless ECG Acquisition Systems

This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.     

A 900 MHz Zero‐IF RF Transceiver for IEEE 802.15.4g SUN OFDM Systems

This paper presents a 900 MHz zero‐IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a ΔΣ fractional‐N frequency synthesizer. In the RF front end, re‐use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low‐noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current‐driven passive mixer in Rx and voltage‐mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty‐cycle in local oscillator clocks. The overall Rx‐baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a 0.18 μm CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of ?2 dBm, a sensitivity level of ?103 dBm at 100 Kbps with , an Rx input P_1dB of ?11 dBm, and an Rx input IP3 of ?2.3 dBm.     

An SOI LDMOS/CMOS/BJT technology for integrated power amplifiersused in wireless transceiver applications

This paper describes a SOI LDMOS/CMOS/BJT technology that can be used in portable wireless communication applications. This technology allows the complete integration of the front-end circuits with the baseband circuits for low-cost/low-power/high-volume single-chip transceiver implementation. The LDMOS transistors (0.35 μm channel length, 3.8 μm drift length, 4.5 GHz f_T and 21 V breakdown voltage), CMOS transistors (1.5 μm channel length, 0.8/-1.2 V threshold voltage), lateral NPN transistor (18 V BV_CBO and h _FE of 20), and high Q-factor (up to 6.1 at 900 MHz and 7.2 at 1.8 GHz) on-chip inductors are fabricated. A fully-functional high performance integrated power amplifier for 900 MHz wireless transceiver application is also demonstrated     

Design of 60GHz RF Transceiver in CMOS:Challenges and Recent Advances

With more than 40 years Moore scaling, the speed of CMOS transistors is around 100 GHz. Such fact makes it possible to realize mm-wave circuits in CMOS. However, with the target of achieving broadband and power-efficient operation, 60 GHz CMOS RF transceiver faces severe challenges. After reviewing the technology issues, regarding the 60 GHz applications, this paper discusses design challenges both from the system and the building block levels, and also presents some simulated or measured circuits results.     

High-speed integrated transceivers for optical wireless

Optical wireless LANs have the potential to provide bandwidths far in excess of those available with current or planned RF networks. There are several approaches to implementing optical wireless systems, but these usually involve the integration of optical, optoelectronic, and electrical components in order to create transceivers. Such systems are necessarily complex, and the widespread use of optical wireless is likely to be dependent on the ability to fabricate the required transceiver components at low cost. A number of UK universities are currently involved in a project to demonstrate integrated optical wireless subsystems that can provide line-of-sight in-building communications at 155 Mb/s and above. The system uses two-dimensional arrays of novel microcavity LED emitters and arrays of detectors integrated with custom CMOS integrated circuits to implement tracking transceiver components. In this article we set out the basic approaches that can be used for in-building optical wireless communication and argue the need for an integrated and scalable approach to the fabrication of transceivers. Our work aimed at implementing these components, including experimental results and potential future directions, is then discussed.     

Fully integrated 2.2-mW CMOS front end for a 900-MHz wirelessreceiver

Low power consumption is the most important concern for integrated wireless devices. This paper illustrates low-power design principles in the CMOS context. They entail seeking strategic combinations of high-quality off-chip passives with RF integrated circuits and searching for better architectures in wireless receivers to low power. The principles are illustrated with a fully integrated 2.2-mW 1.2-V front end for 900-MHz receiver, fabricated in 0.35-μm CMOS