Concurrent Zero Knowledge, Revisited

We provide a more general and, in our eyes, simpler variant of Prabhakaran, Rosen and Sahai’s (FOCS ’02, pp. 366–375, 2002) analysis of the concurrent zero-knowledge simulation technique of Kilian and Petrank (STOC ’01, pp. 560–569, 2001).     

Reanalyzing the basic bandgap reference voltage circuit considering thermal dependence of bandgap energy

The basic bandgap reference voltage generator, BGR, is thoroughly analyzed and relations are reconstructed considering dependency of bandgap energy, E_g, to absolute temperature. The previous works all consider E_g as a constant, independent of temperature variations. However, E_g varies around 25 meV when the temperature is increased from 2 to 92 °C. In this paper the dependence of E_g to absolute temperature, based on HSPICE mosfet models in HSPICE MOSFET Models Manual (Version X-2005.09, 2005), is approximated by a third-order polynomial using Lagrangian interpolating method within the temperature range of 2–92 °C. Accurate analysis on the simplified polynomial reveals that the TC of V_BE must be corrected to ?1.72 mV/°K at 27 °C which has been formerly reported about ?1.5 mV/°K in Razavi (Design of analog CMOS integrated circuits, 2001) and Colombo et al. (Impact of noise on trim circuits for bandgap voltage references, 2007), ?2 mV/°K in Gray et al. (Analysis and design of analog integrated circuits, 2001), Leung and Mok (A sub-1-V 15-ppm/°C CMOS bandgap voltage reference without requiring low threshold voltage device, 2002), Banba et al. (A CMOS bandgap reference circuit with sub-1-V operation, 1999), and ?2.2 mV/°K in Jones and Martin (Analog integrated circuit design, 1997), Tham and Nagaraj (A low supply voltage high PSRR voltage reference in CMOS process, 1995). Another important conclusion is that the typical weighting coefficient of TC+ and TC? terms is modified to about 19.84 at 27 °C temperature from otherwise 16.76, when E_g is considered constant, and also 17.2, in widely read literatures, (Razavi in Design of analog CMOS integrated circuits, 2001). Neglecting the temperature dependence of E_g might introduce a relative error of about 20.5 % in TC of V_BE. Also, resistance and transistor size ratios, which denote the weighting coefficient of TC+ term, might be encountered to utmost 20.3 % error when the temperature dependence of E_g is ignored.     

Improved Cryptanalysis of AES-like Permutations

AES-based functions have attracted of a lot of analysis in the recent years, mainly due to the SHA-3 hash function competition. In particular, the rebound attack allowed to break several proposals and many improvements/variants of this method have been published. Yet, it remained an open question whether it was possible to reach one more round with this type of technique compared to the state-of-the-art. In this article, we close this open problem by providing a further improvement over the original rebound attack and its variants, that allows the attacker to control one more round in the middle of a differential path for an AES-like permutation. Our algorithm is based on lists merging as defined in (Naya-Plasencia in Advances in Cryptology: CRYPTO 2011, pp. 188–205, 2011) and we generalized the concept to non-full active truncated differential paths (Sasaki et al. in Lecture Notes in Computer Science, pp. 38–55, 2010). As an illustration, we applied our method to the internal permutations used in Grøstl, one of the five finalist hash functions of the SHA-3 competition. When entering this final phase, the designers tweaked the function so as to thwart attacks from Peyrin (Peyrin in Lecture Notes in Computer Science, pp. 370–392, 2010) that exploited relations between the internal permutations. Until our results, no analysis was published on Grøstl and the best results reached 8 and 7 rounds for the 256-bit and 512-bit versions, respectively. By applying our algorithm, we present new internal permutation distinguishers on 9 and 10 rounds, respectively.     

Algebraic integer architecture with minimum adder count for the 2-D Daubechies 4-tap filters banks

A multiplierless architecture based on algebraic integer representation for computing the Daubechies 4-tap wavelet transform for 1-D/2-D signal processing is proposed. This architecture improves on previous designs in a sense that it minimizes the number of parallel 2-input adder circuits. The algorithm was achieved using numerical optimization based o exhaustive search over the algebraic integer representation. The proposed architecture furnishes exact computation up to the final reconstruction step, which is the operation that maps the exactly computed filtered results from algebraic integer representation to fixed-point. Compared to Madishetty et al. (IEEE Trans Circuits Syst I (Accepted, In Press), 2012a), this architecture shows a reduction of \(10\cdot n-3\) adder circuits, where \(n\) is the number of wavelet decomposition levels. Standard \(512\times 512\) images Mandrill, Lena, and Cameraman were submitted to digital realizations of both proposed algebraic integer based as well as fixed-point schemes, leading to quantifiable comparisons. The design is physically implemented for a 4-level 2-D decomposition using a Xilinx Virtex-6 vcx240t-1ff1156 FPGA device operating at up to a maximum clock frequency of 263.15 MHz. The FPGA implementation is tested using hardware co-simulation using an ML605 board with clock of 100 MHz. A 45 nm CMOS synthesis shows improved clock frequency of better than 500 MHz for a supply voltage of 1.1 V.     

An Improved Full Rate Full Diversity QOSTBC with Linear Decoding in MIMO Systems

In this letter, we propose an improved Quasi-orthogonal space-time block code (QOSTBC) with full rate, full diversity, linear decoding and better peak-to-average power ratio (PAPR). Constellation rotation is used to the input symbol vector to ensure full diversity, and then the information symbol vector is interleaved in coordinates and pre-grouped by using a Given rotation matrix. The performance is evaluated by numerical experiments. The PAPR of our proposed QOSTBC is lower than that of CI-QOSTBC in Khan and Rajan (IEEE Trans Inf Theory 52(5):2062–2091, 2006). Meanwhile, the Bit-error-rate versus Signal-to-noise-ratio of our proposed QOSTBC is better than those of OSTBC (Tarokh et al. in IEEE Trans Inf Theory 45(5):1456–1467, 1999) QOSTBC (Jafarkhani in IEEE Trans Wirel Commun 49(1):1–4, 2001), G-QOSTBC (Park et al. in IEEE Commun Lett 12(12):868–870, 2008), slightly better that of the CI-QOSTBC, and as same as that of the recently proposed Minimum Decoding Complexity QOSTBCs (MDC-QOSTBC) in Yuen et al.(IEEE Trans Wirel Commun 4(5):2089–2098, 2005), Wang and Xia (IEEE Trans Inf Theory 55(3):1104–1130, 2009). Compared with MDC-QOSTBC, the proposed QOSTBC has simpler code construct and lower decoding complexity.     

Enhancements of Trapdoor Permutations

We take a closer look at several enhancements of the notion of trapdoor permutations. Specifically, we consider the notions of enhanced trapdoor permutation (Goldreich, Foundation of Cryptography: Basic Applications, 2004) and doubly enhanced trapdoor permutation (Goldreich, Computational Complexity: A Conceptual Perspective, 2011) as well as intermediate notions (Rothblum, A Taxonomy of Enhanced Trapdoor Permutations, 2010). These enhancements arose in the study of Oblivious Transfer and NIZK, but they address natural concerns that may arise also in other applications of trapdoor permutations. We clarify why these enhancements are needed in such applications, and show that they actually suffice for these needs.     

A hybrid multiagent routing approach for wireless ad hoc networks

Wireless ad-hoc networks are infrastructureless networks that comprise wireless mobile nodes able to communicate each other outside wireless transmission range. Due to frequent network topology changes in one hand and the limited underlying bandwidth in the other hand, routing becomes a challenging task. In this paper we present a novel routing algorithm devoted for mobile ad hoc networks. It entails both reactive and proactive components. More precisely, the algorithm is based on ant general behavior, but differs from the classic ant methods inspired from Ant-Colony-Optimization algorithm [1]. We do not use, during the reactive phase, a broadcasting technique that exponentially increases the routing overhead, but we introduce a new reactive route discovery technique that considerably reduces the communication overhead. In the simulation results, we show that our protocol can outperform both Ad hoc On-demand Distance Vector (AODV) protocol [2], one of the most important current state-of-the-art algorithms, and AntHocNet protocol [5], one of the most important ant-based routing algorithms, in terms of end-to-end delay, packet delivery ratio and the communication overhead.     

A Real-time Scalable Object Detection System using Low-power HOG Accelerator VLSI

As described in this paper, a real-time object detection system using a Histogram of Oriented Gradients (HOG) feature extraction accelerator VLSI is presented. The VLSI [1, 2] enables the system to achieve real-time performance and scalability for multiple object detection under limited power condition. The VLSI employs three techniques: a VLSI-oriented HOG algorithm with early classification in Support Vector Machine (SVM) classification, a dual-core architecture for parallel feature extraction, and a detection-window-size scalable architecture with a reconfigurable MAC array for processing objects of different shapes. The test chip was fabricated using 65 nm CMOS technology. The measurement result shows that the VLSI consumes 43 mW at 42.9 MHz and 1.1 V to process HDTV (1920?×?1080 pixels) at 30 frames per second (fps). A multiple object detection system and a multiple scale object detection system are presented to demonstrate the system flexibility and scalability realized by VLSI and applicability for versatile application of object detection. On the multiple object detection system, a real-time object detection for HDTV resolution video is achieved with 84 mW of power consumption on a task to detect 2 types of targets while keeping comparable detection accuracy as software-based system. On the multiple scale object detection system, a task to detect 5 scales of a target is accomplished using a single VLSI. The power consumption of the VLSI is estimated to 102 mW on the task.     

Adaptive Power Allocation for Maximizing the Sum Rate of Multiple Interfering Links Under Minimum Rate Constraints

An adaptive power control algorithm is proposed to maximize the sum rate of multiple interfering links under minimum rate constraints. The proposed algorithm efficiently minimizes the outage probability of total network system by using an iterative algorithm with complexity of \(O\left( {N^{2}\ln N} \right) \) , where \(N\) is the number of interfering links. By Monte Carlo simulations, it is shown that the proposed algorithm guarantees the optimum outage probability and the system sum rate above 80 %, compared with the geometric programming (Chiang et al in IEEE Trans Wirel Commun 6(7):2640–2651, 2007).     

Image distortion analysis based on normalized perceptual information distance

Image distortion analysis is a fundamental issue in many image processing problems, including compression, restoration, recognition, classification, and retrieval. Traditional image distortion evaluation approaches tend to be heuristic and are often limited to specific application environment. In this work, we investigate the problem of image distortion measurement based on the theory of Kolmogorov complexity, which has rarely been studied in the context of image processing. This work is motivated by the normalized information distance (NID) measure that has been shown to be a valid and universal distance metric applicable to similarity measurement of any two objects (Li et al. in IEEE Trans Inf Theory 50:3250–3264, 2004). Similar to Kolmogorov complexity, NID is non-computable. A useful practical solution is to approximate it using normalized compression distance (NCD) (Li et al. in IEEE Trans Inf Theory 50:3250–3264, 2004), which has led to impressive results in many applications such as construction of phylogeny trees using DNA sequences (Li et al. in IEEE Trans Inf Theory 50:3250–3264, 2004). In our earlier work, we showed that direct use of NCD on image processing problems is difficult and proposed a normalized conditional compression distance (NCCD) measure (Nikvand and Wang, 2010), which has significantly wider applicability than existing image similarity/distortion measures. To assess the distortions between two images, we first transform them into the wavelet transform domain. Assuming stationarity and good decorrelation of wavelet coefficients beyond local regions and across wavelet subbands, the Kolmogorov complexity may be approximated using Shannon entropy (Cover et al. in Elements of information theory. Wiley-Interscience, New York, 1991). Inspired by Sheikh and Bovik (IEEE Trans Image Process 15(2):430–444, 2006), we adopt a Gaussian scale mixture model for clusters of neighboring wavelet coefficients and a Gaussian channel model for the noise distortions in the human visual system. Combining these assumptions with the NID framework, we derive a novel normalized perceptual information distance measure, where maximal likelihood estimation and least square regression are employed for parameter fitting. We validate the proposed distortion measure using three large-scale, publicly available, and subject-rated image databases, which include a wide range of practical image distortion types and levels. Our results demonstrate the good prediction power of the proposed method for perceptual image distortions.     

Formal Verification of Analog and Mixed Signal Designs Using SPICE Circuit Simulation Traces

Analog and Mixed Signal (AMS) designs can be formally modeled as hybrid systems [45] and therefore formal verification techniques applicable to hybrid systems can be deployed to verify them. An extension to a formal verification approach applicable to hybrid systems is proposed to verify AMS designs [31]. In this approach formal verification (FV) is carried out on an AMS block using simulation traces from SPICE, a simulator widely used in the design and verification of analog and AMS blocks. A broader implication of this approach is the ability to carry out hierarchical verification using relevant simulation traces obtained at different abstraction levels of a design when modeled in appropriate platforms. This enables a seamless transition of design and verification artifacts from the highest level of abstraction to the lowest level of implementation at the transistor level of any AMS design and a resulting increase in confidence on the correctness of the final implementation. The proposed approach has been justified with its applications to different AMS design blocks. For each design, its formal model and the proposed computational techniques have been incorporated into CheckMate [11] - a FV tool for hybrid systems based on MATLAB and the Simulink/Stateflow framework from MathWorks. A further justification of the proposed approach is the resulting improvements observed in terms of reduced verification time for different specifications in each design.     

A Note on Constant-Round Zero-Knowledge Proofs of Knowledge

In this note, we show the existence of constant-round computational zero-knowledge proofs of knowledge for all $\mathcal {NP}$ . The existence of constant-round zero-knowledge proofs was proven by Goldreich and Kahan (Journal of Cryptology, 1996), and the existence of constant-round zero-knowledge arguments of knowledge was proven by Feige and Shamir (CRYPTO, 1989). However, the existence of constant-round zero-knowledge proofs of knowledge for all $\mathcal {NP}$ is folklore, to the best of our knowledge, since no proof of this fact has been published.     

A green radio resource allocation scheme for LTE-A downlink systems with CoMP transmission

In this paper, we propose a green radio resource allocation (GRRA) scheme for LTE-advanced downlink systems with coordinated multi-point (CoMP) transmission to support multimedia traffic. The GRRA scheme defines a green radio utility function, which is composed of the required transmission power, assigned modulation order, and the number of coordinated transmission nodes. By maximizing this utility function, the GRRA scheme can effectively save transmission power, enhance spectrum efficiency, and guarantee quality-of-service requirements. The simulation results show that when the traffic load intensity is greater than 0.7, the GRRA scheme can save transmission power by more than 33.9 and 40.1 %, as compared with the conventional adaptive radio resource allocation (ARRA) scheme (Tsai et al. in IEEE Trans Wireless Commun 7(5):1734–1743, 2008) with CoMP and the utility-based radio resource allocation (URRA) scheme (Katoozian et al. in IEEE Trans Wireless Commun 8(1):66–71, 2009) with CoMP, respectively. Besides, it enhances the system throughput by approximately 5.5 % and improves Jain’s fairness index for best effort users by more than 155 % over these two ARRA and URRA schemes.     

The First Year Nursing Students’ Achievement and Critical Thinking in Local Wisdom Course Using Problem Based Learning Process

The purpose of this one group—pre test post test design classroom research was to examine learning achievement, critical thinking and satisfaction of first year nurse students at school of nursing during academic year 2011. In the research activity, 94 students participated in three weeks for each scenario in Local Wisdom and Health Care which composed of 4 scenarios. Problem based learning process were included the preparation of facilitators, preparation of learners, and problem/scenario based assignments. The instruments composed of 1) 135 items, 4 multiple choices test which were covered behavioral objectives and blue print of test and validated by course lecturers 2) opinion evaluation form, open ended questionnaire and 3) the critical thinking questionnaire, 80 items in five domains which are Inference, Recognition of Assumption, Deduction, Interpretation, and Evaluation of Argument with internal consistency of .73. Data were analyzed using frequency, percentage, mean, standard deviation, percentile, t test and $\chi ^{2}$ test. It was found that the highest score of learning achievement was 88.79 % while the lowest score was 70.33 %, average learning achievement score was 80.60 $(\pm 3.47)\%$ . The highest grade levels were B+ and B equally (41.49 %). Students demonstrated higher overall critical thinking $(49.62 \pm 5.78)$ after undergone problem based learning process than before the problem based learning process $(46.69 \pm 6.00)$ statistically significance $(\text{ t}\,=\,4.443, p\,<\,.05)$ . Inference and Recognition of Assumption domain after PBL process were better than their own thoughts before PBL process significantly (t = 2.288, $p\,<\,.05$ ; t = 6.287, $p\,<\,.05$ , respectively). The ability of critical thinking was found that the high, moderate and low level (percentile $>75, 25-75$ and $<25$ ) after PBL were difference from the ability before the process significantly $(\chi ^{2}=12.219, p\,<\,.05)$ .     

More Constructions of Lossy and Correlation-Secure Trapdoor Functions

We propose new and improved instantiations of lossy trapdoor functions (Peikert and Waters in STOC’08, pp. 187–196, 2008), and correlation-secure trapdoor functions (Rosen and Segev in TCC’09, LNCS, vol. 5444, pp. 419–436, 2009). Our constructions widen the set of number-theoretic assumptions upon which these primitives can be based, and are summarized as follows:

• Lossy trapdoor functions based on the quadratic residuosity assumption. Our construction relies on modular squaring, and whereas previous such constructions were based on seemingly stronger assumptions, we present the first construction that is based solely on the quadratic residuosity assumption. We also present a generalization to higher-order power residues.
• Lossy trapdoor functions based on the composite residuosity assumption. Our construction guarantees essentially any required amount of lossiness, where at the same time the functions are more efficient than the matrix-based approach of Peikert and Waters.
• Lossy trapdoor functions based on the d-Linear assumption. Our construction both simplifies the DDH-based construction of Peikert and Waters and admits a generalization to the whole family of d-Linear assumptions without any loss of efficiency.
• Correlation-secure trapdoor functions related to the hardness of syndrome decoding.

     

Accelerating Multiresolution Gabor Feature Extraction for Real Time Vision Applications

Multiresolution Gabor filter banks are used for feature extraction in a variety of applications as Gabor filters have shown to be exceptional feature extractors with a close correspondence to the simple cells in the primary visual cortex (V1) of the brain. Yet applying the Gabor filter is a computationally intensive task. Most applications that utilize the Gabor feature space require real time results; however, the large quantity of computations involved has hindered systems from achieving real time performance. The natural solution for such compute intensive tasks is parallelization. FPGAs have emerged as attractive platforms for compute intensive signal processing applications due to their massively parallel computation resources as well as low power consumption and affordability. We present a configurable architecture for Gabor feature extraction on FPGA that enhances the resource utilization of the FPGA hardware fabric while maintaining a streaming data flow to yield exceptional performance. The increased resource utilization resulting from configurability, optimizations, and resource sharing allows for higher levels of parallelism to achieve real time feature extraction of high resolution images. Two architectures are introduced. The first is an architecture for multiresolution feature extraction with extensive resource sharing for enhanced resource utilization. The second is an architecture for many-orientation applications using a coarse to fine grain method to enhance resource utilization by reducing the number of filters applied at different orientations. Our results show that our multiresolution implementation achieves real-time performance on 2048?×?1526 images and exhibits 6X speed up over a GPU implementation while exhibiting energy efficiency with 0.4fps/W compared to the GPU that achieves 0.036fps/W.[1] The implementation for many-orientation applications using the coarse to fine grain method exhibits resource saving of at most \( 2\sqrt{O} \) for O number of orientations and higher, compared to a fully parallel architecture and 25× speedup compared to a GPU implementation for 16 orientations.     

Robust FIPP p-cycles against dual link failures

We propose a new generic flow formulation for Failure-Independent Path-Protecting (FIPP) p-cycles subject to multiple failures. While our new model resembles the decomposition model formulation proposed by Orlowski and Pioro (Networks, 2011) in the case of classical shared path protection, its originality lies in its adaptation to FIPP p-cycles. When adapted to that last pre-configured pre-cross connected protection scheme, the bandwidth sharing constraints must be handled in a different way in order to take care of the sharing along the FIPP p-cycles. It follows that, instead of a polynomial-time solvable pricing problem as in the model of Orlowski and Pioro (Networks, 2011), we end up with a much more complex pricing problem, which has an exponential number of constraints due to some subtour elimination constraints. Consequently, in order to efficiently solve the pricing problem, we consider: (i) a hierarchical decomposition of the original pricing problem; (ii) heuristics in order to go around the large number of constraints in the pricing problem. Performance evaluation is made in the case of FIPP p-cycles subject to dual failures. For small to medium size networks, the proposed model remains fairly scalable for increasing percentages of dual failures, and requires much less bandwidth than p-cycle protection schemes (ratio varies from 2 to 4). For larger networks, heuristics are required in order to keep computing times reasonable. In the particular case of single link failures, it compares very favorably (5 to 10 % of bandwidth saving) to the previously proposed column generation ILP model of Rocha, Jaumard and Stidsen (Telecommun. Syst., 2012).     

Electronically scanned RF-to-bits beam aperture arrays using 2-D IIR spatially bandpass digital filters

A beamforming system based on two-dimensional (2-D) spatially bandpass infinite impulse response (IIR) plane wave filtering is presented in a multi-dimensional signal processing perspective and the implementation details are discussed. Real-time implementation of such beamforming systems requires modeling of computational electromagnetics for the antennas, radio frequency (RF) analog design aspects for low-noise amplifiers (LNAs), mixed-signal aspects for signal quantization and sampling and finally, digital architectures for the spatially bandpass plane wave filters proposed in Joshi et al. (IEEE Trans Very Large Scale Integr Syst 20(12):2241–2254, 2012). Multi-dimensional spatio-temporal spectral properties of down-converted RF plane wave signals are reviewed and derivation of the spatially bandpass filter transfer function is presented. An example of a wideband antipodal Vivaldi antenna is simulated at 1 GHz. Potential RF receiver chains are identified including a design of a tunable combline microstrip bandpass filter with tuning range 0.8–1.1 GHz. The 1st-order sensitivity analysis of the beam filter 2-D $\mathbf z $ -domain transfer function shows that for a 12-bits of fixed-point precision, the maximum percentage error in the 2-D magnitude frequency response due to quantization is as low as $0.3\,\%$ . Monte-Carlo simulations are used to study the effect of quantization on the bit error rate (BER) performance of the beamforming system. 5-bit analog to digital converter (ADC) precision with 8-bit internal arithmetic precision provides a gain of approximately 16 dB for a BER of $10^{-3}$ with respect to the no beamforming case. ASIC Synthesis results of the beam filter in 45 nm CMOS verifies a real time operating frequency of 429 MHz.     

A Novel 2.5–3.1 GHz Wide-Band Low-Noise Amplifier in 0.18 \upmu \hbox {m} CMOS

Aiming for the simultaneous realization of constant gain, accurate input and output impedance matching and minimum noise figure (NF) over a wide frequency range, the circuit topology and detailed design of wide broadband low noise amplifier (LNA) are presented in this paper. A novel 2.5–3.1 GHz wide-band LNA with unique characteristics has been presented. Its design and layout are done by TSMC 0.18  \(\upmu \hbox {m}\) technology. Common gate stage has been used to improve input matching. In order to enhance output matching and reduce the noise as well, a buffer stage is utilized. Mid-stages which tend to improve the gain and reverse isolation are exploited. The proposed LNA achieves a power gain of 15.9 dB, a NF of 3.5 dB with an input return loss less than \(-\) 11.6, output return loss of \(-\) 19.2 to \(-\) 19 and reverse isolation of \(-\) 38 dB. The LNA consumes 54.6 mW under a supply voltage of 2 V while having some acceptable characteristics.