Improvements in Noise Suppression for I/O Circuits Using Embedded Planar Capacitors

The performance of embedded planar capacitors in noise suppression of input/output (I/O) circuits and improvements in board impedance profile have been investigated in this paper. Simultaneous switching noise (SSN) is a critical issue in today's systems and this paper shows performance improvements by introducing thin planar embedded capacitors in the board stack up. Measurement and modeling results by including the effects of transmission lines and the power ground plane pairs in the board stack up in the gigahertz range quantify the performance of the embedded capacitors.     

Effect of Shield Line on Noise Margin and Refresh Time of Planar DRAM Cell for Embedded Application

In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of 3.63 µm². We designed a 1Mb DRAM with an open bit‐line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when V_cc is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.     

Storage Estimation and Design Space Exploration Methodologies for the Memory Management of Signal Processing Applications

The storage requirements in data-dominated signal processing systems, whose behavior is described by array-based, loop-organized algorithmic specifications, have an important impact on the overall energy consumption, data access latency, and chip area. This paper gives a tutorial overview on the existing techniques for the evaluation of the data memory size, which is an important step during the early stage of system-level exploration. The paper focuses on the most advanced developments in the field, presenting in more detail (1) an estimation approach for non-procedural specifications, where the reordering of the loop execution within loop nests can yield significant memory savings, and (2) an exact computation approach for procedural specifications, with relevant memory management applications – like, measuring the impact of loop transformations on the data storage, or analyzing the performance of different signal-to-memory mapping models. Moreover, the paper discusses typical memory management trade-offs – like, for instance, between storage requirement and number of memory accesses – taken into account during the exploration of the design space by loop transformations in the system specification.     

复分接中数字化定时处理的参数化验证法

在复分接系统中，如同步数字系列，定时处理占有重要地位。数字化定时处理技术应用于ＡＳＩＣ设计时，传统方法需要的仿真代价太大。作者 定时验证的特殊性，提出了定时处理电路验证的概念。同时利用参数化方法对定时处理进行验证，大大缩短了仿真时间。     

强背景噪声中信号二次循环自相关检测与幅度估计

检测淹没在强背景噪声中的窄带信号是信号处理中的一个重要问题。通过改进传统的自相关和多重自相关检测方法,提出了二次循环自相关检测方法。在几种强背景噪声下,通过快速傅立叶变换（FFT）功率谱估计的计算机仿真实验,证明了所提的方法在检测能力方面优于传统方法。根据FFT的特性,还估计出了强噪声中信号的幅度。     

改进卡尔曼滤波算法在语音信号处理中的应用

针对传统卡尔曼滤波算法在加性噪声影响下的语音信号处理中要先对被观测系统的状态进行统计估值和计算量很大的问题．提出了改进卡尔曼滤波算法。该算法不用预先估计噪声、驱动项以及语音模型参数,可直接得到增强的语音信号。通过仿真实验证明,该方法在减少计算量的同时,有效地消除了加性噪声,并能保持较好的语音可懂度。     

Characterisation of Signal Modality: Exploiting Signal Nonlinearity in Machine Learning and Signal Processing

A novel method for online tracking of the changes in the nonlinearity within both real-domain and complex–valued signals is introduced. This is achieved by a collaborative adaptive signal processing approach based on a hybrid filter. By tracking the dynamics of the adaptive mixing parameter within the employed hybrid filtering architecture, we show that it is possible to quantify the degree of nonlinearity within both real- and complex-valued data. Implementations for tracking nonlinearity in general and then more specifically sparsity are illustrated on both benchmark and real world data. It is also shown that by combining the information obtained from hybrid filters of different natures it is possible to use this method to gain a more complete understanding of the nature of the nonlinearity within a signal. This also paves the way for building multidimensional feature spaces and their application in data/information fusion.     

基于循环谱的BPSK信号参数估计及硬件实现研究

基于信号循环平稳特性的检测和参数估计方法具有较强的干扰和噪声抑制能力。而分段谱相关函数算法（Strip Spectral Correlation Algorithm,SSCA）是一种实用的高效循环谱估计算法,对循环平稳信号的检测和参数估计的硬件实现具有重要意义。本文以SSCA的ADSPTS201S的实现为研究重点,在此基础上完成了对BPSK信号的载频和码元速率估计,为循环谱的工程应用打下坚实的基础。     

Application Exploration for 3-D Integrated Circuits: TCAM, FIFO, and FFT Case Studies

3-D stacking and integration can provide system advantages. This paper explores application drivers and computer-aided design (CAD) for 3-D integrated circuits (ICs). Interconnect-rich applications especially benefit, sometimes up to the equivalent of two technology nodes. This paper presents physical-design case studies of ternary content-addressable memories (TCAMs), first-in first-out (FIFO) memories, and a 8192-point fast Fourier transform (FFT) processor in order to quantify the benefit of the through-silicon vias in an available 180-nm 3-D process. The TCAM shows a 23% power reduction and the FFT shows a 22% reduction in cycle-time, coupled with an 18% reduction in energy per transform.      

阵列信号处理在地震震源位置及震级估计中的应用

提出了对重点地区和地震频繁爆发地区进行地震震源位置估计的新思路,并运用阵列信号处理的理论对该思路进行了详尽的数学分析,建立了实际地壳的复杂非均匀传输介质模型,并将该模型转换为一种简单的均匀传输介质模型;之后给出了具体的算法和计算机仿真模拟结果。容易发现,运用该思路对特定地区进行地震速报,将可以摆脱地震监测中震源定位难的困扰。     

Using Error Correcting Codes Without Speed Penalty in Embedded Memories: Algorithm, Implementation and Case Study

Drastic device shrinking, power supply reduction, increasing complexity and increasing operating speeds affect adversely the reliability of nowadays Integrate Circuits (ICs). In many modern designs, embedded memories occupy the largest part of the die and comprise the large majority of transistors. Furthermore, memories are designed as tight as allowed by the process, and are therefore more prone to failures than other circuits. Error correcting codes (ECCs) are an efficient mean for protecting memories against failures. A major drawback of ECCs is the speed penalty induced by the encoding and decoding circuits. In this paper, we present an architecture enabling implementing ECCs without speed penalty. Furthermore, as the manual implementation of this solution is impractical for complex System-on-Chips (SoCs), we propose an algorithm and a set of generic rules allowing automatic insertion of the delay-free ECCs in any complex architecture at Register Transfer Level (RTL). With respect to a naive insertion in the design of the new architecture, the algorithm enable up to 20 % hardware reduction. The Finite State Machines (FSM) that controls the new ECC architecture is also generated automatically. Experimental evaluations show that the hardware overhead of the speed penalty free ECCs protected memory compared to a standard implementation of ECC protected memory is about 2.5 % with an additional power consumption of 6 %.     

C-HEAP: A Heterogeneous Multi-Processor Architecture Template and Scalable and Flexible Protocol for the Design of Embedded Signal Processing Systems

The key issue in the design of Systems-on-a-Chip (SoC) is to trade-off efficiency against flexibility, and time to market versus cost. Current deep submicron processing technologiesenable integration of multiple software programmable processors (e.g., CPUs,DSPs) and dedicated hardware components into a single cost-efficient IC. Ourtop-down design methodology with various abstraction levels helps designingthese ICs in a reasonable amount of time. This methodology starts with a high-levelexecutable specification, and converges towards a silicon implementation.A major task in the design process is to ensure that all components (hardwareand software) communicate with each other correctly. In this article, we tacklethis problem in the context of the signal processing domain in two ways: wepropose a modular, flexible, and scalable heterogeneous multi-processor architecturetemplate based on distributed shared memory, and we present an efficient andtransparent protocol for communication and (re)configuration. The protocolimplementations have been incorporated in libraries, which allows quick traversalof the various abstraction levels, so enabling incremental design. The designdecisions to be taken at each abstraction level are evaluated by means of(co-)simulation. Prototyping is used too, to verify the system's functionalcorrectness. The effectiveness of our approach is illustrated by a designcase of a multi-standard video and image codec.He currently works with Magma Design Automation. E-mail:     

See-through Detection and 3D Reconstruction Using Terahertz Leaky-Wave Radar Based on Sparse Signal Processing

We experimentally demonstrate see-through detection and 3D reconstruction using terahertz leaky-wave radar based on sparse signal processing. The application of terahertz waves to radar has received increasing attention in recent years for its potential to high-resolution and see-through detection. Among others, the implementation using a leaky-wave antenna is promising for compact system integration with beam steering capability based on frequency sweep. However, the use of a leaky-wave antenna poses a challenge on signal processing. Since a leaky-wave antenna combines the entire signal captured by each part of the aperture into a single output, the conventional array signal processing assuming access to a respective antenna element is not applicable. In this paper, we apply an iterative recovery algorithm “CoSaMP” to signals acquired with terahertz leaky-wave radar for clutter mitigation and aperture synthesis. We firstly demonstrate see-through detection of target location even when the radar is covered with an opaque screen, and therefore, the radar signal is disturbed by clutter. Furthermore, leveraging the robustness of the algorithm against noise, we also demonstrate 3D reconstruction of distributed targets by synthesizing signals collected from different orientations. The proposed approach will contribute to the smart implementation of terahertz leaky-wave radar.     

嵌入式闪存中浮栅多晶硅CMP制程的研究与改善

随着CMP技术的日益发展和闪存特征尺寸的越来越小以及对多晶硅表面形态及前后层次间套准要求的提高,这一技术也被用于嵌入式闪存产品中浮动栅多晶硅的平坦化。浮动栅多晶硅厚度及表面形态对器件的电性参数及后续工艺影响较大,因此怎样得到一个稳定、厚度均匀及表面形态佳的浮动栅多晶硅显得至关重要。文章就以在90nm嵌入式闪存开发浮动栅...