DTMB外辐射源雷达纠错算法性能评估

低密度奇偶检验(LDPC)码纠错算法是地面数字多媒体广播(DTMB)外辐射源雷达参考信号重构的关键技术之一。LDPC码纠错算法可以改善噪声带来的数据误码,但是计算复杂度高。结合图形处理器(GPU)运算能力强的优点,本文提出了基于硬判决、混合判决、软判决的3类适用于GPU处理的LDPC码纠错并行算法,并对比了3类算法的复杂度、纠错性能以及对雷达信号处理的影响;最后,给出了GPU并行实现方案,对比了算法的实时化效果。仿真与实测结果论证了相较于其他算法,软判决并行算法具有优越的纠错性能和实效性。     

Development of 3T eDRAM gain cells for enhancing read margin and data retention

This paper presents three transistors (3T) based Dynamic Random Access Memory (DRAM) cell in which noise, static power, and data retention voltage (DRV) have been reduced. The spesified parameters in the proposed eDRAM gain cell were improved by connecting the source of storage device to the read word line signal instead of supply voltage. As we all know, power consumption plays a vital role in VLSI design and thus, it is enumerated among the top challenges for the semiconductor chip industries. With the intention to maintain the performance of write operation, we diminish DRV and increase the read margin of eDRAM cell with our designed circuit which is introduced as “A Boosted 3T eDRAM gain cell”. It is a kind of eDRAM cell that utilizes a read word line (RWL) via three PMOS transistors instead of NMOS transistors. PMOS devices are preferred as they have radically less gate leakage current, which confer better results for data retention and thus, boost up the read margin of the cell. Simulation results have been obtained by using Cadence Virtuoso Tool at 45 nm technology for the proposed model. Based on simulation results we can conclude that the parameters of the proposed eDRAM gain cell essentially improved as compared with convertional eDRAM gain cell and the achieved parameters are as follows: static power is 0.767 pW, DRV is 142.009 mV and noise is 8.421 nV/Hz^1/2.     

Exploiting three-dimensional (3D) memory stacking to improve image data access efficiency for motion estimation accelerators

Enabled by the emerging three-dimensional (3D) integration technologies, 3D integrated computing platforms that stack high-density DRAM die(s) with a logic circuit die appear to be attractive for memory-hungry applications such as multimedia signal processing. This paper considers the design of motion estimation accelerator under a 3D logic-DRAM integrated heterogeneous multi-core system framework. In this work, we develop one specific DRAM organization and image frame storage strategy geared to motion estimation. This design strategy can seamlessly support various motion estimation algorithms and variable block size with high energy efficiency. With a DRAM performance modeling/estimation tool and ASIC design at 65 nm, we demonstrate the energy efficiency of such 3D integrated motion estimation accelerators with a case study on HDTV multi-frame motion estimation.     

一种交错并行隐式刷新增益单元eDRAM设计

设计了一种与逻辑工艺兼容的64 kb高速高密度嵌入式增益单元动态随机存储器(eDRAM)。该存储器单元通过结构和版图的优化,典型尺寸为同代SRAM的40%。高低阈值管的引入分别改善了单元的读取速度和数据保持时间。同时交错并行隐式刷新机制利用增益存储单元读、写端口独立的结构和操作特性,配以合适的时序和仲裁机制,使得在无额外通信信号和握手接口下,实现刷新与访问互不影响,数据访问率达到100%。相比其他隐式刷新技术,该技术不需要过大的外围开销即可完成访问带宽加倍。芯片用SMIC 0.13μm CMOS工艺实现,大小为1.35 mm×1.35 mm。     

不同译码下LDPC码的图像应用

文中介绍了LDPC码的构造及其译码原理,该码在中短码长时具有很强的纠错能力,将其与图像传榆相结合,能够达到很好的图像传输质量。仿真实现了在AWGN信道下规则LDPC码的图像传输系统,用四种译码算法对LDPC码的性能做了仿真,并将其在图像传输中的效果做了比较。仿真结果发现,LDPC码采用不同的译码算法输出图像的效果是不一样的。     

状态网格图的LDPC码在OFDM系统中的应用

介绍了LDPC码的编译码技术,提出了一种新颖的2状态网格图译码算法,研究了该码在OFDM系统中的性能,对不同的译码算法进行了比较.仿真结果表明,LDPC码在OFDM基带传输系统中用2状态网格图对其译码能够更好的对错误码进行纠错,提高码字性能,信息传输速率会大大提高.     

Linear programming decoding: The ultimate decoding technique for low density parity check codes

Linear programming (LP) decoding is an alternative to iterative algorithms for decoding low density parity check (LDPC) codes. Although the practical performance of LP decoding is comparable to message-passing decoding, a significant advantage is its relative amenability to nonasymptotic analysis. Moreover, there turn out to be a number of important theoretical connections between the LP decoding and standard forms of iterative decoding. These connections allow theoretical insight from the LP decoding perspective to be transferred to iterative decoding algorithms. These advantages encouraged many researchers to work in this recent decoding technique for LDPC codes. In this paper, LP decoding for LDPC code is extensively reviewed and is discussed in different segmented areas.     

Decoding and Design of LDPC Codes for High-Order Modulations

A concatenated code model is proposed for high-order low-density parity-check (LDPC) coded modulations. A corresponding concatenated-code belief propagation (CCBP) decoding algorithm is derived for our proposed concatenated code. Moreover, the design of LDPC codes under the CCBP decoding is developed using extrinsic information transfer (EXIT) charts. Compared with other algorithms, the CCBP method provides an excellent parallel decoding process, and the EXIT-based design method offers highly accurate LDPC code ensembles. Simulation results show that the performance of the proposed CCBP algorithm is superior to that of the conventional belief propagation decoding within a wide range of modulation orders, and the EXIT-based method can design capacity-approaching LDPC codes for high-order modulations.     

DVB-S2中LDPC和积译码的GPU实现

第二代卫星数字广播系统DVB-S2采用接近Shannon限的LDPC码作为内码.在LDPC译码方式中,软判决的和积译码性能最佳,但是由于其采用大量浮点数运算,使得译码器的软硬件实现都较困难.为此,提出一种采用图形处理器(GPU)编程进行译码的实现方式.GPU的并行处理功能使其可以同时满足高精度浮点运算和高速实时解码的要求,为DVB-S2的实际应用提供了新的思路.采用计算机上NVIDIA GeForce 9600显卡编程环境,实现了满足高清视频要求的信息吞吐速率.     

Flexible and Expandable Speech Recognition Hardware with Weighted Finite State Transducers

Hardware implementation of speech recognition can not only accelerate decoding speed for real-time processing but also reduce the power consumption. Recently the weighted finite state transducer (WFST) has emerged as a major recognition network representation because it reduces the algorithmic complexity of decoding procedures by applying many optimizations on the network in offline. However, hardware implementation of continuous speech recognition (CSR) with the WFST network is challenging, mainly because Viterbi search should traverse a large sized network with limited hardware resources. This paper presents two hardware speech recognition systems with the WFST network. The first one, which is called the SRAM-oriented system, utilizes the internal SRAM as a hash table to efficiently manage active working set. This system is flexible because it can easily accommodate different speech recognition tasks as long as the SRAM space is allowed. For easy expansion, we also propose the DRAM-oriented system where the active working set is stored in the external DRAM. To hide long latency of DRAM access, a split DRAM hash table is employed, which stores active working set in the opened rows of DRAM to reduce the number of row misses. Experimental results show that the SRAM-oriented system decodes the 5k-word CSR task 4.93 times faster than real-time, while the DRAM-oriented system runs 4.48 times faster than real-time with only about a half SRAM capacity.     

LDPC码的改进及其应用的研究

在介绍LDPC(Low Density Parity Code)低密度校验码的基本原理的基础上，针对任意离散无记忆信道的传输，从两个方面对其结构进行了改进。这种改进的LDPC码是定义在有限域GF(q)上的非正则LDPC码，较之正则LDPC码具有更好的性能。采用改进的非正则LDPC码，经过最大似然概率译码，能够实现以任意逼近任何离散无记忆信道容量的速率的可靠通信。同时，讨论了对应于这种码结构的实际的迭代译码方法，并简单介绍了这种改进的非正则LDPC码在OFDM系统、压缩图像传输等方面的应用。     

数字电视传输系统中LDPC码编译码器的研究与设计

低密度奇偶校验码纠错能力强,能够在逼近香农极限的信噪比条件下获得很高的误码率特性,非常适用于无线通信。本文分析了在DMB-TH标准中LDPC码的构造、编码及解码算法原理,结合MATLAB仿真对其算法有效性进行了分析比较。     

基于ADV611/ADV612的实时视频压缩系统

介绍了基于ADV611／ADV612开发的实时视频压缩系统。该系统电路使用廉价的外部DRAM存储器，不使用昂贵的SRAM缓冲器或VRAM帧存，其硬件成本较低。该系统在数字视频信号处理方面有很好的应用前景。     

Correcting capabilities of binary irregular LDPC code under low-complexity iterative decoding algorithm

This paper deals with the irregular binary low-density parity-check (LDPC) codes and two iterative low-complexity decoding algorithms. The first one is the majority error-correcting decoding algorithm, and the second one is iterative erasure-correcting decoding algorithm. The lower bounds on correcting capabilities (the guaranteed corrected error and erasure fraction respectively) of irregular LDPC code under decoding (error and erasure correcting respectively) algorithms with low-complexity were represented. These lower bounds were obtained as a result of analysis of Tanner graph representation of irregular LDPC code. The numerical results, obtained at the end of the paper for proposed lower-bounds achieved similar results for the previously known best lower-bounds for regular LDPC codes and were represented for the first time for the irregular LDPC codes.     

An 80/20-MHz 160-mW multimedia processor integrated with embeddedDRAM, MPEG-4 accelerator and 3-D rendering engine for mobileapplications

A low-power multimedia processor for mobile applications is presented. An 80-MHz 32-b RISC with enhanced multiplier, two 20-MHz hardware accelerators with 7.125-Mb embedded DRAM for MPEG-4 visual SP@L1 decoding and 3-D graphics processing, 2-kB dual-port SRAM, and peripheral blocks are integrated together on a single chip, MPEG-4 SP@L1 video decoding and 3-D graphics rendering with a 16-b depth-buffer alpha-blending double-buffering and gouraud-shading features at 2, 2-Mpolygons/s speed are realized with the help of the dedicated hardware accelerators/ The architecture of the processor is optimized in terms of power consumption and performance, and various low-power circuit techniques are adopted in each hardware block. The chip is implemented using 0.18-μm embedded memory logic (EML) technology. Its area is 84 mm², and power consumption is 160 mW when all of the functions are activated     

分割转移构造下QC-LDPC码设计与实现

为了降低码长较长的LDPC码在随机构造下编译码的复杂度与难度,利用PS(分割转移法)构造一类不存在四环的(6075,5402)QC-LDPC码,并对其性能进行了仿真,仿真结果表明该准循环码可以达到与同等长度下随机码相同的性能。针对此结构,利用VHDL编程实现了编译码过程,并验证了其正确性,与随机LDPC码相比实现复杂度与难度大大降低。     

硬件可实现的LDPC译码算法研究

低密度奇偶校验(LDPC)码有着较强的纠错能力,已被确定为第四代移动通信技术中首选码字。分析对比了几种LDPC译码算法的过程,基于硬件可实现性这一研究热点,对传统的译码算法进行了优化,提出一种易于硬件实现的LDPC译码算法。仿真结果表明:归一化最小和算法在不增加迭代次数,码长较长的情况下也有着很好的译码性能,适合在LDPC译码器的硬件实现中推广。     

Bounds on mutual information for simple codes using information combining

For coded transmission over a memoryless channel, two kinds of mutual information are considered: the mutual information between a code symbol and its noisy observation and the overall mutual information between encoder input and decoder output. The overall mutual information is interpreted as a combination of the mutual informations associated with the individual code symbols. Thus, exploiting code constraints in the decoding procedure is interpreted as combining mutual informations. For single parity check codes and repetition codes, we present bounds on the overall mutual information, which are based only on the mutual informations associated with the individual code symbols. Using these mutual information bounds, we compute bounds on extrinsic information transfer (exit) functions and bounds on information processing characteristics (ipc) for these codes.     

一种低码率的LDPC码在LTE-A中的性能研究

本文通过分析LTE-Advanced系统中准循环LDPC码校验矩阵的构造方法,在不改变母码矩阵的基础上,采用一种灵活的扩展方法,构造了一种低码率的LDPC码。采用一种很实用的编码算法和差分译码算法,在MATLAB仿真平台下,比较了这种LDPC码和Turbo码的性能。结果表明：在短码情况下,这种LDPC码在低信噪比下性能略低于Turbo码,但随着信噪比的增加,LDPC码性能优于Turbo码;在长码情况下,LDPC码的性能明显优于Turbo码。为LTE-Advanced系统的信道编解码器的硬件设计提供了一套有效的编译码算法方案,具有较好的实用价值。     

LDPC码在OFDM通信系统中的应用与仿真

介绍了OFDM基带传输系统及其模型；概述LDPC的编译码方法，研究了其在OFDM系统中的性能，并与卷积码进行了比较。仿真表明，LDPC码在OFDM基带传输系统中具有更好的纠错能力。LDPC码可实现完全并行的编译码操作，译码简单，吞吐量大，因而将在下一代移动通信中得到广泛应用。