Decoder malfunction in BCH decoders

A t-error-correcting bounded-distance decoder either produces the codeword nearest the received vector (if there is a codeword at distance no more than t) or indicates that no such codeword exists. However, BCH decoders based on the Peterson-Gorenstein-Zierler algorithm or the Euclidean algorithm can malfunction and produce output vectors that are not codewords at all. For any integer i no greater than t/2, if the received vector is at distance at most t-2i from a codeword belonging to a (t-i)-error-correcting BCH supercode, then the BCH decoder output is that codeword from the supercode     

Asymptotically optimal soft decision decoding algorithms for Hamming codes

Asymptotically optimal soft decision decoding algorithms for d = 3 and d = 4 Hamming codes are given and analysed. Only error sequences with probability exponent larger than that of maximum-likelihood decoding are corrected. Upper bounds on the block error probability for the Gaussian channel are given.     

Optimal soft decision block decoders based on fast Hadamard transform

An approach for efficient utilization of fast Hadamard transform in decoding binary linear block codes is presented. Computational gain is obtained by employing various types of concurring codewords, and memory reduction is also achieved by appropriately selecting rows for the generator matrix. The availability of these codewords in general, and particularly in some of the most frequently encountered codes, is discussed.     

关于BCH码的广义Hamming重量上,下限

一个线性码的第ｒ广义Ｈａｍｍｉｎｇ重量是它任意ｒ维子码的最小支集大小。本文给出了一般（本原、狭义）ＢＣＨ码的广义Ｈａｍｍｉｎｇ重量下限和一类ＢＣＨ码的广义Ｈａｍｍｉｎｇ重量上限     

视频字符叠加器

文章介绍了实现在电视信号上叠加字符的方法，并具体给出了一个实际用于水井电视检修的视频字符叠加器的软硬件。     

A note on generalized Hamming weights of BCH(2)

Determines results for the first six generalized Hamming weights of double-error-correcting primitive binary BCH codes     

Extended Hamming accumulate codes and modified irregular repeataccumulate codes

Two classes of codes, called extended Hamming accumulate codes and modified nonsystematic irregular repeat accumulate (IRA) codes, are introduced. Simulation results show that the performance of modified nonsystematic IRA codes are slightly superior to turbo codes of comparable complexity on an additive white Gaussian noise channel     

扩展汉明编码的交织重排及其程序实现

本文简述将扩展汉明编码进行交织和重排以提高信道抗突发干扰能力的原理,以及采用汇编语言进行程序实现的方法.     

On the second generalized Hamming weight of the dual code of adouble-error-correcting binary BCH code

The generalized Hamming weight of a linear code is a new notion of higher dimensional Hamming weights. Let C be an [n,k] linear code and D be a subcode. The support of D is the cardinality of the set of not-always-zero bit positions of D. The rth generalized Hamming weight of C, denoted by d_r(C), is defined as the minimum support of an r-dimensional subcode of C. It was shown by Wei (1991) that the generalized Hamming weight hierarchy of a linear code completely characterizes the performance of the code on the type II wire-tap channel defined by Ozarow and Wyner (1984). In the present paper the second generalized Hamming weight of the dual code of a double-error-correcting BCH code is derived and the authors prove that except for m=4, the second generalized Hamming weight of [2^m-1, 2m]-dual BCH codes achieves the Griesmer bound     

Extended AMR-WB for high-quality audio on mobile devices

This article presents the architecture, performance, and application scenarios of the AMR-WB+ (extended AMR-WB) audio codec, which provides high quality at exceptionally low rates, and consistent quality over all audio types. This codec was recently selected by 3GPP and DVB to support low-bit-rate audio and audiovisual applications on mobile networks.     

A subband coding, BCH coding, and 16-QAM system for mobile radiospeech communications

A combined subband speech coding (SBC), Bose-Chaudhuri-Hocquenghem (BCH) error-correction coding, and 16-level quadrature amplitude modulation (16-QAM) scheme with switched diversity and speech postenhancement is proposed. The system's performance is dramatically improved by deploying some degree of fade tracking capability over fading channels. Further quality enhancement accrues by using appropriate mapping between the SBC speech codec and the Gray coded QAM words. Various BCH codes are utilized to adequately match the error-correcting power to the perceptual importance of the SBC bits. One of the proposed systems operates at 7 kBd and yields good communications-quality speech for channel signal-to-noise ratios (SNRs) in excess of 20 dB and encounters a maximum overall system delay of 55.125 ms. A more complex arrangement uses second-order switched diversity to reduce the channel SNR required to around 16 dB and the transmission rate to 5 kBd when the vehicular speed is 30 mph while the system delay is unchanged at 55.125 ms     

Optimum soft decision demodulation for ISI channels

Two different methods of soft-decision demodulation for channels with finite intersymbol interference (ISI) in the presence of additive white Gaussian noise (AWGN) are analyzed. In both schemes, the cutoff rate R₀ of the discrete channel created by the demodulator output quantization is chosen as the design criterion. Expressions for the optimal thresholds of the quantizer associated with the demodulation of binary signals are derived. Results for the channel with memory equal to one symbol duration are presented. As a special case, the (1-D) channel with soft decision demodulation is analyzed. Closed-form solutions show that a 4-b quantizer improves performance substantially in this case     

Fast low-power decoders for RAMs

Decoder design involves choosing the optimal circuit style and figuring out their sizing, including adding buffers if necessary. The problem of sizing a simple chain of logic gates has an elegant analytical solution, though there have been no corresponding analytical results until now which include the resistive effects of the interconnect. Using simple RC models, we analyze the problem of optimally sizing the decoder chain with RC interconnect and find the optimum fan-out to be about 4, just as in the case of a simple buffer chain. As in the simple buffer chain, supporting a fan-out of 4 often requires noninteger number of stages in the chain. Nevertheless, this result is used to arrive at a tight lower bound on the delay of a decoder. Two simple heuristics for sizing of real decoder with integer stages are examined. We evaluate a simple technique to reduce power, namely, reducing the sizes of the inputs of the word drivers, while sizing each of the subchains for maximum speed, and find that it provides for an efficient mechanism to trade off speed and power. We then use the RC models to compare different circuit techniques in use today and find that decoders with two input gates for all stages after the predecoder and pulse mode circuit techniques with skewed N to P ratios have the best performance     

Extended Monte Carlo localization algorithm for mobile sensor networks

A real-world localization system for wireless sensor networks that adapts for mobility and irregular radio propagation model is considered. The traditional range-based techniques and recent range-free localization schemes are not well competent for localization in mobile sensor networks, while the probabilistic approach of Bayesian filtering with particle-based density representations provides a comprehensive solution to such localization problem. Monte Carlo localization is a Bayesian filtering method that approximates the mobile node＇s location by a set of weighted particles. In this paper, an enhanced Monte Carlo localization algorithm-Extended Monte Carlo Localization （Ext-MCL） is proposed, i.e., the traditional Monte Carlo localization algorithm is improved and extended to make it suitable for the practical wireless network environment where the radio propagation model is irregular. Simulation results show the proposal gets better localization accuracy and higher localizable node number than previously proposed Monte Carlo localization schemes not only for ideal radio model, but also for irregular one.     

Low-floor decoders for LDPC codes

One of the most significant impediments to the use of LDPC codes in many communication and storage systems is the error-rate floor phenomenon associated with their iterative decoders. The error floor has been attributed to certain subgraphs of an LDPC code?s Tanner graph induced by so-called trapping sets. We show in this paper that once we identify the trapping sets of an LDPC code of interest, a sum-product algorithm (SPA) decoder can be custom-designed to yield floors that are orders of magnitude lower than floors of the the conventional SPA decoder. We present three classes of such decoders: (1) a bi-mode decoder, (2) a bit-pinning decoder which utilizes one or more outer algebraic codes, and (3) three generalized-LDPC decoders. We demonstrate the effectiveness of these decoders for two codes, the rate-1/2 (2640,1320) Margulis code which is notorious for its floors and a rate-0.3 (640,192) quasi-cyclic code which has been devised for this study. Although the paper focuses on these two codes, the decoder design techniques presented are fully generalizable to any LDPC code.     

On classical BCH codes and quantum BCH codes

It is a regular way of constructing quantum error-correcting codes via codes with self-orthogonal property, and whether a classical Bose-Chaudhuri-Hocquenghem (BCH) code is self-orthogonal can be determined by its designed distance. In this paper, we give the sufficient and necessary condition for arbitrary classical BCH codes with self-orthogonal property through algorithms. We also give a better upper bound of the designed distance of a classical narrow-sense BCH code which contains its Euclidean dual. Besides these, we also give one algorithm to compute the dimension of these codes. The complexity of all algorithms is analyzed. Then the results can be applied to construct a series of quantum BCH codes via the famous CSS constructions.     

Turbo decoders for Markov channels

We present a decoder for parallel concatenated codes that incorporates a binary-input binary-output Markov channel model, thereby allowing the receiver to utilize the statistical structure of the channel during the decoding process. These decoders can enable reliable communication at rates which are above the capacity of a memoryless channel with the same stationary bit error probability as the Markov channel, and therefore outperform systems based on the traditional approach of using a channel interleaver to create a channel which is assumed to be memoryless     

VLSI architectures for SISO-APP decoders

Very large scale integration (VLSI) design methodology and implementation complexities of high-speed, low-power soft-input soft-output (SISO) a posteriori probability (APP) decoders are considered. These decoders are used in iterative algorithms based on turbo codes and related concatenated codes and have shown significant advantage in error correction capability compared to conventional maximum likelihood decoders. This advantage, however, comes at the expense of increased computational complexity, decoding delay, and substantial memory overhead, all of which hinge primarily on the well-known recursion bottleneck of the SISO-APP algorithm. This paper provides a rigorous analysis of the requirements for computational hardware and memory at the architectural level based on a tile-graph approach that models the resource-time scheduling of the recursions of the algorithm. The problem of constructing the decoder architecture and optimizing it for high speed and low power is formulated in terms of the individual recursion patterns which together form a tile graph according to a tiling scheme. Using the tile-graph approach, optimized architectures are derived for the various forms of the sliding-window and parallel-window algorithms known in the literature. A proposed tiling scheme of the recursion patterns, called hybrid tiling, is shown to be particularly effective in reducing memory overhead of high-speed SISO-APP architectures. Simulations demonstrate that the proposed approach achieves savings in area and power in the range of 4.2%-53.1% over state of the art.