低功耗、高线性度的电流模可编程增益放大器

本文设计了一种电流模式下,带电流模直流失调消除（DCOC）电路的class-AB的可编程增益放大器。电路基于电流放大器,可以实现40dB的增益动态范围,增益步长为1dB。电流模可编程增益放大器由0.18-μm CMOS工艺实现,电路具有较宽的电流增益范围、较低的直流功耗和较小的芯片面积。放大器电路芯片面积为0.099μm2,在1.8V电压下静态电流为2.52mA。测试结果表明电路增益范围为10dB到50dB,增益误差为±0.40dB,OP1dB为11.80dBm到13.71dBm,3dB带宽为22.2MHz到34.7MHz。     

带有DCOC结构的中频可编程增益放大器

介绍了一种用于射频识别接收机、能有效消除直流失调的中频可编程增益放大器.单级放大器的仿真结果可提供.10～20 dB的增益控制范围,增益步长为2 dB,增益误差小于0.3 dB.通过在直流失调消除环路中增加一级滤波器的方法,有效地降低了直流失调和低频噪声,在40 kHz工作频率下等效输入噪声电压38.04 nV/ Hz,直流失调消除电路可将输出直流失调量抑制在输入失调量的2%范围以内.电路采用0.18μm IP6M CMOS工艺实现.     

用于77GHz毫米波雷达的模拟基带电路设计

实现了一个带宽和增益可配置、高线性度、低噪声的模拟基带电路,可应用于77 GHzCMOS毫米波雷达接收机.电路包括一个带宽可配置的5阶巴特沃斯低通滤波器模块、三个可编程增益放大器模块以及三个直流失调消除环路.增益范围为18～70 dB,增益步进为6 dB;带宽为200 kHz～2 MHz;噪声系数最小为24 dB;输出1-dB压缩点为5.1 dBm,在最高增益时,IIP3为-52dBm;功耗为14.6 mA@1 V.电路采用65 nm CMOS工艺实现,芯片面积为1.2×0.93 (mm2).     

64dB二进制增益控制带有DCOC和AB类buffer的可编程增益放大器

本文设计了一款二进制增益控制,带有直流失调消除（DCOC）电路以及AB类输出buffer的可编程增益放大器。该放大器采用二极管连接负载的差分放大器结构,电路性能对温度变化及工艺偏差不敏感。根据测试,通过6位数字信号控制,电路可以实现-2dB ~ 61dB的增益动态范围,增益步长1dB,步长误差在 0.38dB以内,最小3dB带宽为92MHz,在低增益模式下,IIP3可达17dBm,1dB压缩点可达5.7dBm。DCOC电路可使该放大器应用于直接变频接收机中,而AB类输出buffer则降低了电路的静态功耗。     

一种增益可控音频前置放大器电路的设计

设计了一种基于0.5μm CMOS工艺的增益可控音频前置放大器电路。该电路采用直流音量控制方式控制前置放大器的增益,进而实现整体音频放大器的音量控制。外部输入的直流模拟电压经过片内模数转换器转换成数字控制信号,控制前置放大器的输入电阻与反馈电阻的比值,从而实现前置放大器的增益控制。该放大器能够实现32档的音量控制范围,增益从-50 dB变化到25 dB,电路版图面积为1.2 mm×0.8 mm。     

基于低功耗约束的CMOS LNA的优化设计

针对低功耗电路发展的趋势,在传统的共源共栅结构基础上,同时引入实现噪声优化的PCSNIM技术和提高增益的级间匹配技术,通过合理调节晶体管的尺寸实现了低功耗的指标.电路采用TSMC 0.18 μm CMOS工艺进行设计,模拟结果表明,在2.45 GHz工作频率下,输入输出匹配良好,增益为14.274 dB,噪声系数为0.669 dB,1 dB压缩点为-16.1 dBm,IIP3为-4.858 dBm,直流功耗仅2.628 mW.     

一种用于GPS接收机的宽带、高增益变化范围的AGC设计

介绍了一种宽带、高增益变化范围的用于GPS接收机的模拟CMOS自动增益控电路(AGC)的设计.整个AGC环路用0.35μm CMOS工艺实现,包括可变增益运算放大器(VGA)、固定增益运算放大器(FGA)、增益控制电路和直流失调抑制电路.经过仿真验证AGC的最大增益可达80dB,增益变化范围是56dB,环路锁定时间为70μs.     

基于∑-△ ADC的低功耗运算放大器设计

介绍了一种用于∑-△ADC的低功耗运算放大器电路.该电路采用全差分折叠-共源共栅结构,采用0.35 μm CMOS工艺实现,工作于3 V电源电压.仿真结果表明,该电路的动态范围为80 dB、直流增益68 dB、单位增益带宽6.8 MHz、功耗仅为87.5 μW,适用于∑-△ ADC.     

一种指数增益控制宽范围可变增益放大器

采用中芯国际(SMIC)0.18μm CMOS工艺设计了一种具有指数增益特性的的宽增益调节范围的可变增益放大器,该放大器由Gilbert单元、指数电压转换电路、直流消除电路及超级源级跟随器组成。经过Cadence仿真验证,该放大器可以实现-11.14dB~30.39dB的增益连续变化,其-3dB带宽为250MHz,控制电压与增益成dB线性关系。     

宽带CMOS可变增益放大器的设计

采用TSMC 0.18μm RF CMOS工艺设计实现了一种对数增益线性控制型的宽带可变增益放大器.电路采用两级结构,前级采用电压并联负反馈的Cascode结构以实现良好的输入匹配和噪声性能;后级采用信号相加式电路实现增益连续可调.同时本文设计了一种新型指数控制电压转换电路,解决了射频CMOS电路中,由于漏源电流与栅源电压通常不为指数关系而造成放大器对数增益与控制电压不成线性关系的难题,实现了可变增益放大器的对数增益随控制电压呈线性变化.芯片测试结果表明,电路在1.8V电源电压下,电流为9mA,3dB带宽为430～2330MHz.增益调节范围为-3.3～9.5dB,最大增益下噪声系数为6.2dB,最小增益下输入1dB压缩点为-9dBm.     

A programmable gain amplifier with a DC offset calibration loop for a directconversion WLAN transceiver

A high-linearity PGA(programmable gain amplifier) with a DC offset calibration loop is proposed.The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity.A continuous time feedback based DC offset calibration loop is also designed to solve the DC offset problem.This PGA is fabricated by TSMC 0.13μm CMOS technology.The measurements show that the receiver PGA(RXPGA) provides a 64 dB gain range with a step of 1 dB,and the transmitter PGA(TXPGA) covers a 16 dB gain.The RXPGA consumes 18 mA and the TXPGA consumes 7 mA (I and Q path) under a 3.3 V supply.The bandwidth of the multi-stage PGA is higher than 20 MHz.In addition,the DCOC(DC offset cancellation) circuit shows 10 kHz of HPCF(high pass cutoff frequency) and the DCOC settling time is less than 0.45μs.     

Noise Analysis and Optimization of Programmable Gain Amplifier with DC Offset Cancelation

The noise contribution of a DC offset cancelation (DCOC) circuit in a programmable gain amplifier (PGA) is studied for the first time in this paper. The analysis presented shows that the DCOC-induced noise may deteriorate the PGA’s noise performance significantly if we do not pay enough attention to it. For an analog DCOC (ADCOC), it is concluded that the PGA’s noise increases rapidly as the output DC offset decreases, thereby causing difficulties to achieve both low noise and low DC offset simultaneously. We propose an optimization technique that can effectively alleviate the noise issue by increasing the feedback amplifier’s gain and the resistor’s value simultaneously, while maintaining a reasonable DC gain. For a digital DCOC (DDCOC), the extra noise comes from the transistors of the current source (sink) bank. The transistors with a longer channel length are preferred for their lower thermal and flicker noise current. The proof-of-concept prototypes are designed in a 0.18-\(\upmu \)m CMOS process, and a 3-stage PGA with ADCOC is fabricated. The measurement results validate the analysis and simulation results well.     

CMOS linear-in-dB VGA with DC offset cancellation for direct-conversion receivers

A low-power high-linearity linear-in-dB variable gain amplifier(VGA) with novel DC offset calibration loop for direct-conversion receiver(DCR) is proposed.The proposed VGA uses the differential-ramp based technique,a digitally programmable gain amplifier(PGA) can be converted to an analog controlled dB-linear VGA. An operational amplifier(OPAMP) utilizing an improved Miller compensation approach is adopted in this VGA design.The proposed VGA shows a 57 dB linear range.The DC offset cancellation(DCOC) loop is based on a continuous-time feedback that includes the Miller effect and a linear range operation MOS transistor to realize high-value capacitors and resistors to solve the DC offset problem,respectively.The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement.Fabricated using SMIC 0.13μm CMOS technology,this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58 mm~2 of chip area including bondpads.In addition,the DCOC circuit shows 500 Hz high pass cutoff frequency(HPCF) and the measured residual DC offset at the output of VGA is less than 2 mV.     

A novel zero dead zone PFD and efficient CP for PLL applications

This paper presents a high dynamic range programmable gain amplifier (PGA) with linear-in-dB and digital to analog converter (DAC) gain control using a BiCMOS process. The proposed PGA is composed of a folded Gilbert variable gain amplifier cell, a DC offset cancellation circuitry, two inductorless fixed gain amplifiers with bandwidth extension, a symmetrical exponential voltage generator, a novel buffer amplifier with active inductive peaking for testing purposes and a 10 bit R-2R DAC. The linear-in-dB and DAC gain control scheme facilitate the analog baseband gain tuning accuracy and stability, which also provides an efficient way for digital baseband automatic gain control. The PGA chip is fabricated using 0.13 μm SiGe BiCMOS technology. With a power consumption of 80 mA@1.2 V supply voltage, the fabricated circuit exhibits a tunable gain range of ? 30–27 dB (DAC linear gain step guaranteed), a 3 dB bandwidth of around 3.5 GHz and a gain resolution of better than 0.07 dB.     

一种Doppler/FMCW双模式雷达模拟基带设计

基于55 nm CMOS工艺,设计了一种应用于24 GHz Doppler/ FMCW双模式雷达系统的模拟基带电路(ABB)。低通滤波器由两个改进型Tow-Thomas二阶节级联而成,实现了增益和带宽独立调节。采用一种基于7 bit可编程电流型数模转换器(IDAC)的两步逐次逼近型直流失调消除电路(SAR DCOC),可在Doppler模式10~600 Hz极低中频条件下,对混频器输出和基带自身直流失调进行消除。在IDAC和两级运放中混合使用BJT管,减小闪烁噪声,获得良好的低频噪声性能。后仿真结果表明,在2.5 V电源电压、模拟基带消耗电流4.9 mA下,两种模式增益范围均为6~62 dB,最大线性输入幅度(IP 1 dB)为10 dBm;62 dB增益时,Doppler模式、FMCW模式下的噪声系数分别小于42 dB、27 dB。蒙特卡罗仿真结果表明,当输入存在400 mV、200 mV直流失调时,基带输出直流失调仅为21.3 mV和16.4 mV。     

A high dynamic range ultralow-current-mode amplifier with pico-ampere sensitivity for biosensor applications

A novel ultralow-current-mode amplifier (ULCA) serving for on-chip biosensor signal pre-amplification in the integrated biosensing system (IBS) has been presented and verified in SMIC 0.18 μm CMOS technology by elaborately considering gain, bandwidth, noise, offset, and mismatch. The proposed ULCA solved the noise, bandwidth, and current headroom dilemma in the reported works, and can completely satisfy the specifications of IBS. It provides a current gain of 20 dB, 3 dB bandwidth of 7.03 kHz and input dynamic range of 20 bit, with only 1 nA of DC quiescent current, while the input offset current and noise current are less than 16.0 pA and 4.67 pArms, respectively.     

A MOS switched-capacitor instrumentation amplifier

Describes a precision switched-capacitor sampled-data instrumentation amplifier using NMOS polysilicon gate technology. It is intended for use as a sample-and-hold amplifier for low level signals in data acquisition systems. The use of double correlated sampling technique achieves high power supply rejection, low DC offset, and low 1/f noise voltage. Matched circuit components in a differential configuration minimize errors from switch channel charge injection. Very high common mode rejection (120 dB) is obtained by a new sampling technique which prevents the common mode signal from entering the amplifier. This amplifier achieves 1 mV typical input offset voltage, greater than 95 dB PSRR, 0.15 percent gain accuracy, 0.01 percent gain linearity, and an RMS input referred noise voltage of 30 /spl mu/V/input sample.     

提取神经电信号的单片集成CMOS前置放大器的仿真研究

提出一种用于提取神经电信号的新型单片集成CMOS前置放大器.在放大器输入端引入的交流耦合电容可以消除存在于电极-电解液之间的电极极化电压,栅源电压为负值的二极管连接的nMOS晶体管能够作为大电阻,并且占用很小芯片面积,可以通过此大电阻为前置放大器提供直流偏置,同时不影响输入阻抗值.通过对输入级进行理论噪声分析,确定了放大器中的各个器件参数.仿真结果表明,由于采用电容负反馈结构,此放大器的交流增益为38.8dB,无直流增益,在0.1Hz～1kHz频率范围内,总输入等效噪声为277nVrms.     

Simulation of a Monolithic Integrated CMOS Preamplifier for Neural Recordings

提出一种用于提取神经电信号的新型单片集成CMOS前置放大器.在放大器输入端引入的交流耦合电容可以消除存在于电极-电解液之间的电极极化电压,栅源电压为负值的二极管连接的nMOS晶体管能够作为大电阻,并且占用很小芯片面积,可以通过此大电阻为前置放大器提供直流偏置,同时不影响输入阻抗值.通过对输入级进行理论噪声分析,确定了放大器中的各个器件参数.仿真结果表明,由于采用电容负反馈结构,此放大器的交流增益为38.8dB,无直流增益,在0.1Hz～1kHz频率范围内,总输入等效噪声为277nVrms.