基于PUF的高效低成本RFID认证协议

已提出的针对低成本RFID系统的安全机制,要么存在安全缺陷,要么硬件成本太高。为此设计了一个基于物理不可克隆功能(PUF)的RFID安全认证协议,利用PUF和线性反馈移位寄存器(LFSR)实现了阅读器和标签之间强的安全认证,解决了已有安全协议存在的问题。安全性分析表明:该协议成本低、安全性高,能够抵抗物理攻击和标签克隆,并有极强的隐私性。     

基于PUF的低成本RFID系统安全协议

针对低成本无线射频识别(RFID)系统存在的安全性问题,提出一种基于PUF的低成本RFID安全协议。利用PUF的物理不可克隆性识别标签的身份,并利用线性反馈移位寄存器(LFSR)产生随机系列,加密阅读器与标签之间的通信,能抵抗重放攻击、跟踪攻击、物理攻击、窃听攻击等多种攻击。在Altera DE2板上使用FPGA实现PUF和LFSR,采用Quartus II 8.0编程。实验结果证明,该协议的执行时间和门电路数量能达到低成本标签的要求。     

基于混沌的反馈移位寄存器设计

针对线性反馈移位寄存器产生的序列周期小,不适用于大数据量信息加密的缺点和单纯的混沌序列在有限精度下易出现小周期的问题,将二者结合,提出一种基于混沌的反馈移位寄存器设计方法,并对这一方法下产生的序列进行了大量的数据试验。分析结果证明,该法产生的二值序列密码具有优良的密码学特性,很适合用于数据加密。     

基于LFSR的演化随机序列发生器

针对基于线性反馈移位寄存器的随机序列发生器产生的随机数线性复杂度低的问题,设计一个新的随机序列发生器,使用遗传算法演化线性反馈移位寄存器产生的随机序列,新产生的序列可以通过SP800—22的测试。测试结果表明,生成的序列周期大、线性复杂度高,能够满足安全协议和密码算法的安全强度要求。     

基于多输入特征寄存器的哈希方法

无源器件的能量和计算资源有限。针对这种器件的安全认证需求,提出了一种新的哈希方法M—hash。该方法基于低复杂性的并行输入LFSR,即多输入特征分析寄存器（MISR）,采用并行压缩方法,具有硬件复杂性低、速度快等特点。理论分析和具体硬件实现表明,M-hash在硬件复杂性、压缩速度和安全性等方面均优于另外一种基于LFSR的Toeplitz希方法。     

Design,implementation and analysis of hardware efficient stream ciphers using LFSR based hash functions

Design and implementation of hardware efficient stream ciphers using hash functions and analysis of their periodicity and security are presented in this paper. The hash generation circuits used for the design and development of stream ciphers are low power, low hardware complexity Linear Feedback Shift Register (LFSR) based circuits. One stream cipher design uses LFSR based Toeplitz hash generation circuit together with LFSR keystream generator circuit, while the other design combines LFSR based filter generator circuit with LFSR based polynomial modular division circuit. Both designs possess good security and periodicity properties for the keystreams generated. The developed circuits can compete with the most popular classic LFSR based stream ciphers in hardware complexity at the same time providing additional advantage that the same circuit can be used for hash generation.     

本原σ-LFSR的计数研究

针对σ-LFSR能够充分利用现代通用CPU且具有结构简单、适合软件快速实现的特点,利用本原σ-LFSR的距离向量和基判别定理,将本原σ-LFSR的计数问题转化为线性空间上基的问题,以此为基础,利用F2上次数小于n的互素多项式的对数解决一上本原σ-LFSR的计数问题。     

LFSR加密新算法的研究与FPGA实现

提出了一种改进的线性反馈移位寄存器结构的安全加密模型,利用移位寄存器的灵活性高和成本低的特点结合FPGA器件的高速度和可重构的性能,从而使系统达到低成本、可实时配置算法文件和重组安全策略的目的,并详细论述了该模型的改进后的线性反馈移位寄存器加密算法的加密原理,然后介绍了该算法的FPGA实现及可重构技术,最后,通过对改进算法的加密时序图的分析和总体性能的评估,证明了该算法在保证安全性能的基础上具有很好的成本优势和可重构性。     

可重构线性反馈移位寄存器设计

线性反馈移位寄存器是序列密码的重要组成部分,介绍了一种可重构线性反馈移位寄存器的设计.根据需要,它可以被配置成为GF(2),GF(28),GF(216)或GF(232)域上一定长度范围内的任意一个线性反馈移位寄存器.该可重构线性反馈移位寄存器原型已在Altera公司的EP2S60F1020C5 FPGA上实现,最高可工作在100 MHz时钟下.试验结果表明:该可重构线性反馈移位寄存器占用硬件资源少,性能稳定.     

一种新型内建自测试重播种技术

测试数据压缩是SoC(System on a Chip)测试领域研究的一个热点问题.本文提出一种新型的内建自测试重播种技术,这项技术利用一个LFSR(Linear Feedback Shift Register)的种子对多个确定性测试向量进行编码压缩,能够显著提高测试数据的压缩率.在ISCAS89基准电路上进行的实验数据显示,这项技术可以减少约30%的LFSR种子数量,进而降低了测试成本.     

Modified dynamic current mode logic based LFSR for low power applications

Shift Register, which is a cascade of flip flops shares the same clock and the outputs are connected to the data input of the next one in the chain. Linear-feedback shift register or shortly LFSR is one such shift register whose input is a linear function of its previous state. Exclusive-OR (XOR) is the most commonly used linear function. LFSR's help in generating pseudo-random numbers, fast digital counters, pseudo-noise sequences and whitening sequences. LFSR's can be realised both using hardware and software. When it comes to hardware implementation, MOS current mode logic (MCML) method can be used for designing the LFSR. There are lots of drawbacks with the traditional MCML method including the static power dissipation, more power consumption at low frequencies as compared with CMOS circuits, inappropriate for large systems involving power-down modes and it's not a cost effective solution either. To overcome these issues and to achieve the high speed characteristics of MCML, we present the modified dynamic current mode logic and is a good solution for battery powered systems and portable solutions. Our simulation results also confirm the same where a 16 bit adder circuit fabricated using CMOS technology has only a delay of 1.22 ns and dissipates 19.0 mW at 400 MHz.     

Security analysis of reversible logic cryptography design with LFSR key on 32-bit microcontroller

This paper presents a detailed security analysis of the research article on the digital image encryption scheme entitled "Reversible Logic Cryptography Design (RLCD) with Linear Feedback Shift Register (LFSR) key" (Karunamurthi S, and Natarajan VK, Microprocessors and Microsystems, 2019). Although the inadequate length of its 4-bit LFSR key makes the scheme extremely vulnerable to quick brute force attack, analyzing the various error metrics concerning the security of the encrypted images, this scheme provides statistically pleasing results. The major shortcoming identified on this RLCD-LFSR scheme is the traceable patterns that appear on its encrypted images due to the absence of confusion to break the pixels' correlation. In addition to the chosen plaintext attack, edge detection based cryptanalysis proposed in this paper to be sufficient to crack the RLCD-LFSR scheme. The enhancement made by the insertion of a confusion module in RLCD-LFSR scheme wipes out the perceptible patterns and edges from the encrypted images to resist the attacks. The failure of enhanced RLCD-LFSR under NIST tests confirms the flaws in the design of the Reversible Logic Gate (RLG) based diffusion process and its ineffectiveness for image encryption. Besides the security analysis, the performance of RLCD-LFSR scheme and the proposed improved version of the same is implemented on a 32-bit microcontroller to evaluate their suitability for real-time embedded applications.     

Wavelet based fault detection in analog VLSI circuits using neural networks

This paper deals with a new method of testing analog VLSI circuits, using wavelet transform for analog circuit response analysis and artificial neural networks (ANN) for fault detection. Pseudo-random patterns generated by Linear Feedback Shift Register (LFSR) are used as input test patterns. The wavelet coefficients obtained for the fault-free and faulty cases of the circuits under test (CUT) are used to train the neural network. Two different architectures, back propagation and probabilistic neural networks are trained with the test data. To minimize the neural network architecture, normalization and principal component analysis are done on the input data before it is applied to the neural network. The proposed method is validated with two IEEE benchmark circuits, namely, the operational amplifier and state variable filter.     

基于混沌的序列密码算法

利用序列密码中的前馈模型设计了一个混沌序列密码算法,以线性反馈移位寄存器序列为初始序列,将Logistic映射和Chebyshev映射作为滤波函数,结合了压缩变换、SMS4算法的S盒变换、有记忆变换和移位变换。分析和实验结果证明算法具有足够的安全强度和较高的加密速度。     

A built-in test pattern generator

Built-in testing is currently of more concern due to the difficulties in testing a VLSI byusing an external tester.In addition,Built-In Testing is also necessary for on-line testing and afault-tolerant computing system.Using a Linear Feedback Shift Register(LFSR)as a built-intest pattern generator(BITPG)is a realistic and simple approach.An LFSR with maximumlength can generate pseudo-random test patterns or all non-null vectors for exhaustive testing.This paper presents an LFSR design with non-maximum length to serve as a BITPG to generatea given test set T,which efficiently saves testing time.A search-verification process fordesigning this kind of LFSR is employed and implemented by the program SVBITPG.Thispaper presents the diagram of tire program and gives stone examples to illustrate the design ofthe BITPG.     

基于Viterbi算法LFSR的恢复与设计

通过优化传统Viterbi算法的存储结构，使其能够对约束长度较大、码率很低卷积码进行译码。离线构造Hamming距离对照表，给出了一种可查表的Viterbi硬判决快速译码算法。实验表明，当误码率为37%以下时，生成多项式的次数在60以内的LFSR(线性反馈移位寄存器)序列的初始状态，可进行快速恢复。与传统的Viterbi译码算法相比，算法的译码效率提高了几乎10倍左右。     

[a,b]-缩减生成器

利用两个反馈移位寄存器（LFSR）构造了一类新型的缩减生成器——［a,b］-缩减生成器,证明了其输出序列的周期、线性复杂度、重量复杂度、k-错线性复杂度及其0、1个数。理论分析和局部随机性检验表明这类缩减生成器序列具有好的统计特性,适合流密码系统的使用。     

Chaos blended cellular automata on fractals: the effective way of reconfigurable hardware assisted medical image privacy

In more recent times data continues to be generated at a very unprecedented scale. This is a result of the pervasive nature of modern-day digitisation. As such, it is absolutely critical that this data only be accessed by the trusted parties concerned in an effort to maintain the privacy of individuals. One particular type data that could severely compromise the identity and privacy of an individual is ‘medical data’. With a focus on medical images, this work proposes a novel ‘fractalized’ chaos-cellular automata encryption scheme, implemented on Cyclone IV EP2C35F672C6 FPGA, resulting in a hardware-based concurrent security solution. The scheme entails three stages of diffusion, which arise from different mechanisms. In tandem with the diffusion process is the “On the Fly” process of confusion governed by a Linear feedback Shift Register (LFSR), all of which in implemented by applying the nature of fractals. The security architecture occupies 16,351 Logic Elements (LEs) with 230 registers on the target FPGA with the power dissipation of 133.39 mW. Further, the encryption achieves near zero correlation with the average entropy of 15.17156 that ensures the statistical properties. In addition, the security framework requires 12.13 ms to encrypt a 256?×?256?×?16 DICOM image which results in the throughput of 86.44 Mbps. The proposed encryption resists the brute force attack and chosen plain text attack by achieving a very large span of keyspace.

     

基于线性反馈移位寄存器和组合猫映射的伪随机序列生成方法

分析了线性反馈移位寄存器(LFSR)和猫映射的基本结构,给出了一种基于LFSR与猫映射的伪随机序列生成方法。该方法根据LFSR的计算结果产生相应的选择函数,通过选择函数确定当前迭代计算中猫映射的系数矩阵;应用选定的系数矩阵进行迭代计算产生相应的混沌序列,将其二值化后作为反馈值与LFSR的反馈值进行异或运算,运算结果作为LFSR的最终反馈值,实现对LFSR生成序列的随机扰动。通过实验对生成序列的性能进行了分析,结果表明,产生的混沌序列具有良好的随机性和安全性。