高性能二维9/7离散小波变换VLSI结构

为了降低二维小波变换中的存储消耗并同时提高电路处理速度,提出了一种二维并行的VLSI结构。通过充分挖掘二维变换中行变换和列变换之间的关系,优化了行变换核和列变换核的并行数据扫描输入方式,将9/7小波变换的中间存储降低至4N。同时,采用基于翻转格式的流水线技术,将电路的关键路径缩短至一级乘法器延时,有效地提高了电路处理速度,并通过伸缩电路合并的优化方法将乘法器个数降低至10个,从而有效地减少了硬件资源消耗。     

一种新的有效的小波变换VLSI结构

基于提升的小波变换算法,提出了一种新的功率面积有效的5—3和9—7小波变换的VLSI实现结构。采用时分复用和嵌入式并行流水线技术优化设计结构,有效地减少了所用乘法器、加法器运算单元和寄存器单元数量,以及对存储器的访问次数,从而有效地减少系统占用面积和功耗。系统实现了每一个时钟产生一个输出,输入信号的细节分量和近似分量交替输出。该结构具有简单、规则,以及扩展性好的特点,非常适合于VLSI设计实现。     

基于System Generator的FIR数字滤波器的设计与实现

数字滤波器的功能是对输入离散的数字信号进行运算处理,以达到改变信号频谱的目的。System Generator是基于定点的仿真系统。的本设计内容全部基于System Generator。首先由DDS（Direct Digital Synthesizer数字信号发生器）生成正弦波信号,之后加入高斯白噪声,将信号通过两种结构的数字滤波器进行滤波,随后将程序下载至FPGA中,通过DA将信号输出,最后在比较两种滤波器的在硬件平台上的实际性能以及消耗资源情况。     

Design and implementation of low power and high speed multiplier using quaternary carry look-ahead adder

Need of Digital Signal Processing (DSP) systems which is embedded and portable has been increasing as a result of the speed growth of semiconductor technology. Multiplier is a most crucial part in almost every DSP application. So, the low power, high speed multipliers is needed for high speed DSP. Array multiplier is one of the fast multiplier because it has regular structure and it can be designed very easily. Array multiplier is used for multiplication of unsigned numbers by using full adders and half adders. It depends on the previous computations of partial sum to produce the final output. Hence, delay is more to produce the output. In the previous work, Complementary Metal Oxide Semiconductor (CMOS) Carry Look-ahead Adders (CLA) and CMOS power gating based CLA are used for maximizing the speed of the multiplier and to improve the power dissipation with minimum delay. CMOS logic is based on radix 2(binary) number system. In arithmetic operation, major issue corresponds to carry in binary number system. Higher radix number system like Quaternary Signed Digit (QSD) can be used for performing arithmetic operations without carry. The proposed system designed an array multiplier with Quaternary Signed Digit number system (QSD) based Carry Look-Ahead Adder (CLA) to improve the performance. Generally, the quaternary devices require simpler circuit to process same amount of data than that needed in binary logic devices. Hence the Quaternary logic is applied in the CLA to improve the speed of adder and high throughput. In array multiplier architecture, instead of full adders, carry look-ahead adder based on QSD are used. This facilitates low consumption of power and quick multiplication. Tanner EDA tool is used for simulating the proposed multiplier circuit in 180 nm technology. With respect to area, Power Delay Product (PDP), Average power proposed QSD CLA multiplier is compared with Power gating CLA and CLA multiplier.     

Implementation of Digital Electronic Arithmetics and its application in image processing

In this paper we introduce new algorithm implementations of a new parametric image processing framework that will accurately process images and speed up computation for addition, subtraction, and multiplication. Its potential applications include computer graphics, digital signal processing and other multimedia applications. This Parameterized Digital Electronic Arithmetic (PDEA) model replaces linear operations with non-linear ones. The implementation of a parameterized model is presented. We also present the design of arithmetic circuits including parallel counters, adders and multipliers based in two high performance threshold logic gate implementations that we have developed. We will also explore new microprocessor architectures to take advantage of arithmetic. The experiments executed have shown that the algorithm provides faster and better enhancements from those described in the literature. The FPGA chips used is Spartan 3E from Xilinix. The critical length in the circuit implemented on the FPGA had the minimum period for the proposed subsystem is 10.209 ns (maximum frequency 97.957 MHz). Maximum power consumed is 2.4 mW using 32 nm process and we used parallelism and reuse of the Hardware components to accomplish and speed up the process.     

Power and delay efficient fir filter design using ESSA and VL-CSKA based booth multiplier

FIR filter plays a major role in digital image processing applications. The power and delay performance of any FIR filter depends on the switching activities between the filter coefficients (FCs) and its basic arithmetic operations (i.e., multiplication and addition) performed in the convolution equations. In this paper, a new FIR filter is designed using Enhanced Squirrel Search Algorithm (ESSA) and Variable latency Carry skip adder (VL-CSKA) based booth multiplier. The proposed ESSA algorithm selects an optimal FC by minimizing the switching activities of FC based on the ripple contents, power and Transition width parameter to meet the required specifications of FIR filter in the frequency domain. Also, the VL-CSKA based booth multiplier is proposed to reduce the delay of FIR filter with parallel addition of partial products (PPs). In this design, the VL-CSKA adders utilize variable size and compound gate-based skip logic to deduce the delay with low power. The proposed FIR filter is simulated in Xilinx working platform by developing Verilog coding. The simulation result shows that the proposed FIR filter outperforms the state-of-the-art FIR filters by consuming only 0.142 mW power with delay of 28.175 ns.     

有效的JPEG2000小波变换VLSI结构设计

基于提升的小波变换算法,提出了一种有效的JPEG2000小波变换的VLSI实现结构。采用了时分复用技术优化结构设计,实现了数据变换的细节分量和近似分量交替输出,以及有效减少了所用乘法器、加法器运算单元和寄存器单元数量,从而有效减少系统占用面积和功耗。该结构实现简单、规则,具有很好的扩展性,非常适合于VLSI设计实现。     

一种改进的基于FPGA的32位对数变换器的设计与实现

对数变换器是对数乘法器的重要组成部分,它们以精度换取更快的速度.设计并实现了一种基于FPGA的32位二进制对数变换器,主要由先导"1"检测电路、移位逻辑和误差校正电路组成,通过有效的误差校正算法提高了计算精度;给出了一种新的4位、16位和32位的基于FPGA的并行先导"1"检测电路PLOD,在保持低延时的同时,减小了先导"1"检测电路的功耗和面积;改进了现有的6-域校正算法,在提高精度的同时保持了硬件电路的规整性,降低了系统复杂度及面积和功耗开销;分两站流水实现校正操作,提高了系统的吞吐率;改进后的校正电路将对数操作的最大误差由30%降低到20%,区域1的平均误差大幅度降低.     

On high-performance parallel decimal fixed-point multiplier designs

High-performance, area and power efficient hardware implementation of decimal multiplication is preferred to slow software simulations in various key scientific and financial applications, where errors caused by converting decimal numbers into their approximate binary representations are unacceptable. This paper presents a parallel architecture for fixed-point 8421-BCD-based decimal multiplication. In essence, it applies a hybrid 8421–5421 recoding scheme to generate partial products, and accumulates them with 8421 carry-lookahead adders organized as a tree structure. In addition, we propose a 4221-BCD-based decimal multiplier that is built upon a novel 4221-BCD full adder; operands of this 4221 multiplier are directly represented in the 4221 BCD. The proposed 16 × 16 decimal multipliers are compared with other best-known decimal multiplier designs with a TSMC 90-nm technology, and the evaluation results show that the proposed 8421–5421 multiplier achieves the lowest delay and area, as well as the highest power efficiency, among all the existing hardware-based BCD multipliers.     

高速浮点乘法部件的CMOS电路设计

本文提出了一种有效的高速乘法器结构,该结构具有连线简单、速度快的优点,阐述了用传输管实现的串行进位加法器、存储进位加法器(CSA)和子倍数选择电路的设计思想。     

Integer squarers with overflow detection

Squaring is commonly used in digital signal processing applications. Significant performance increase can be achieved by supporting squaring in hardware. This paper presents overflow detection methods applicable to integer squarers with unsigned and two’s complement operands. These methods are unified for a combined squarer design. Presented methods can be applied to any squarer independent of size and architecture. The proposed squarer designs have approximately 50% less area and delay compared to the conventional squarer designs with overflow detection.     

Performance Measurement of Energy Efficient and Highly Scalable Hybrid Adder

The adders are the vital arithmetic operation for any arithmetic operations like multiplication, subtraction, and division. Binary number additions are performed by the digital circuit known as the adder. In VLSI (Very Large Scale Integration), the full adder is a basic component as it plays a major role in designing the integrated circuits applications. To minimize the power, various adder designs are implemented and each implemented designs undergo defined drawbacks. The designed adder requires high power when the driving capability is perfect and requires low power when the delay occurred is more. To overcome such issues and to obtain better performance, a novel parallel adder is proposed. The design of adder is initiated with 1 bit and has been extended up to 32 bits so as verify its scalability. This proposed novel parallel adder is attained from the carry look-ahead adder. The merits of this suggested adder are better speed, power consumption and delay, and the capability in driving. Thus designed adders are verified for different supply, delay, power, leakage and its performance is found to be superior to competitive Manchester Carry Chain Adder (MCCA), Carry Look Ahead Adder (CLAA), Carry Select Adder (CSLA), Carry Select Adder (CSA) and other adders.     

A novel power efficient 0.64-GFlops fused 32-bit reversible floating point arithmetic unit architecture for digital signal processing applications

Floating point digital signal processing technology has become the primary method for real time signal processing in most digital systems presently. However, the challenges in the implementation of floating point arithmetic on FPGA are that, the hardware modules are larger, have longer latency and high power consumption. In this work, a novel efficient reversible floating point fused arithmetic unit architecture is proposed confirming to IEEE 754 standard. By utilizing reversible logic circuits and implementation with adiabatic logic, power efficiency is achieved. The hardware complexity is reduced by employing fused elements and latency is improved by decomposing the operands in the realization of floating point multiplier and square root. To validate the design, the proposed unit was used for realization of FFT and FIR filter which are important applications of a DSP processor. As detection is one of the core baseband processing operations in digital communication receivers and the detection speed determines the data rates that can be achieved, the proposed unit has been used to implement the detection function. Simulation results and comparative studies with existing works demonstrate that the proposed unit efficiently utilizes the number of gates, has reduced quantum cost and produced less garbage outputs with low latency, thereby making the design a computational and power efficient one.     

Partial product addition in Vedic design-ripple carry adder design fir filter architecture for electro cardiogram (ECG) signal de-noising application

Design of adder plays a major role in deciding overall performance of system as it is a major building block through generations of design in an innovative design of circuits. In VLSI system and signal processing field applications, various versions of adders are utilized. In applications of signal processing, in recent days, major role is contributed by Finite Impulse Response (FIR) filter. Various authors and papers described its design in a several ways. With the design of effective multiplier, signal denoising application was not explained by any of the existing works. For the generation of partial products, 8-bit multiplier based on a Vedic Mathematics –UrdhvaTiryagbhyam sutra- is proposed in this work. In Vedic multiplier, carry skip method is used for realizing addition of partial product. Four Vedic multipliers of 4 × 4 size are used for designing 8-bit multiplier. Carry skip and UrdhvaTiryagbhyam methods are used for this design. For addition of partial product, this multiplier is designed. Ripple carry adder's logic levels are modified for adding these Vedic multiplier's output. Powerful elimination of ECG noise can be done using this proposed fast FIR filter. In applications of healthcare and biomedical field, they are used. In Vedic design, Ripple Carry Adder (RCA) is used for carrying out partial product addition. Operation of FIR filter with Electro Cardiogram (ECG) signal is done by proposing architecture of FIR filter. It is termed as PPAVD-RCA-FIR and used in de-noising applications. From de-noised signal, Signal to Noise Ratio (SNR), Bit Error Rate (BER) and Mean Square Error (MSE) are computed, which are used for evaluating the performances. When compared with general Vedic multiplier, speed of the proposed design is increased about 13.65% as shown by results.     

基于MIPS指令集的超标量和超长指令字混合架构处理器设计

针对嵌入式和移动设备对处理器高性能低功耗日趋强烈的要求,提出一种基于MIPS指令集的顺序超标量和超长指令字混合架构处理器设计方案,便于以同构多核架构代替目前业界普遍采用的CPU与DSP异构结构,降低功耗面积,同时以VLIW模式获得较好的DSP性能。在PD（Processor Designer）平台下以LISA语言建立处理器的周期精度软件模拟器,通用性能和DSP性能分别由dhrystone、coremark基准测试程序及EEMBC的telecom测试程序进行验证。测试结果表明该设计以较低的硬件开销通过混合架构获得较高的数字信号处理性能,在高性能低功耗的处理器应用场景中拥有良好的适用性。     

An efficient VLSI architecture for lifting based 1D/2D discrete wavelet transform

In this paper, high performance VLSI architectures for lifting based 1D and 2D-Discrete wavelet transforms (DWTs) are proposed. The proposed logic used for area efficient lifting based DWT is to perform the whole operation with one processing element. Similarly, the proposed logic used for delay efficient lifting based DWT is to perform the whole operation with multiple processing elements in parallel. In both the cases, the processing element consists of one floating point adder and one proposed fused multiply add design. The proposed and existing lifting based 1D and 2D lifting based DWTs are implemented with 45 nm technology. The results show that the proposed designs achieve significant improvement compared with existing architectures. For example, 9-point 2-parallel proposed (9, 7) single level 1D-DWT achieves 33.5% of reduction in total cycle delay compared with direct form. Similarly, 9-point single PE proposed (9, 7) single level 1D-DWT achieves 59.8% and 75.5% of reduction in total area and net power over direct form respectively.     

CNFET-based approximate ternary adders for energy-efficient image processing applications

Nowadays, low power design has attracted more attentions. This purpose is achieved through some techniques such as low-power design methods, multiple valued logic and more recently by approximate computing. Carbon nanotube field-effect transistor (CNFET) is an appropriate candidate device for low-power multiple valued logic applications. In approximate computing, reducing the precision of arithmetic blocks leads to reduction in power consumption. In this paper, two approximate CNFET-based ternary full adder cells are proposed. The proposed designs considerably reduce the design complexity and the number of transistors by utilizing the unique properties of CNFETs as well as the switching logic style. The simulation results demonstrate that the proposed approximate designs improve the delay, power and energy dissipation by about 90% as compared to their exact counterparts. Also, as the adder cells are commonly used in the reduction step of multiplier circuits, the efficiency of the proposed cells is investigated in the structure of ternary multipliers through the normalized error distance and power-error tradeoff metrics. Moreover, as the approximate circuits are used in image processing applications, an inexact ternary multiplier is utilized for pixel by pixel image multiplying and the results are compared with the exact ones. According to the simulation results, the proposed inexact methods enhance the performance of arithmetic circuits while maintaining the required accuracy for such applications.     

滤波器组框架理论及其在图信号处理中的应用

滤波器组框架理论是应用数学、信号处理、图像处理和数字通信等领域的重要问题之一,对滤波器组框架的分析和设计问题进行研究有着重要的科学意义和应用前景.近年来,随着高维非规则化数据信息大量涌现,很多学者开始研究图信号处理的滤波器组方法.因此对滤波器组框架理论及其在图信号处理中的应用进行了综述研究.首先对传统滤波器组框架理论的基础知识进行概述,总结滤波器组框架分析与设计方法;然后重点介绍两类图信号处理架构以及图滤波器组的最新研究成果;最后对未来的研究进行展望.     

一种高性能乘法器生成器的设计

全新的基于全定制传输门结构42压缩高性能乘法生成器能根据用户输入自动产生并行乘法器的Verilog代码,并对Wallace Tree的连线进行了优化。最后在末级加法器阶段,生成器能根据到达的时延不同自动选择不同加法器最优的分段。在设计某些乘法器时生成器产生的代码综合结果在面积增加10％～20％左右时比Synopsys Design Ware库里相应的乘法器快5％-9％左右。