共查询到20条相似文献,搜索用时 15 毫秒
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提出了基于FPGA设计混沌信号发生器的改进方法.采用Euler算法将连续混沌系统转换为离散混沌系统;基于IEEE-754单精度浮点数标准和模块化设计理念,使用Quartus Ⅱ软件,采用VHDL和原理图相结合的方式设计混沌信号发生器.最后,在FPGA实验系统上进行实验,在示波器上显示了混沌吸引子的相图及时域混沌信号.由于采用了基于数据选择器的面积优化方法,复用耗费逻辑资源较多的浮点运算模块,大大减少了混沌信号发生器所占用的FPGA逻辑资源.实验结果表明了该方法的有效性和通用性. 相似文献
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基于FPGA的数字信号发生器的设计与实现 总被引:1,自引:2,他引:1
使用AD9854芯片和FPGA,基于DDS理论设计并实现了多模式多波形雷达信号源.它可模拟LFM、NLFM、单频、相位编码等多种脉冲信号波形,能有效验证脉冲压缩与信号处理单元的工作性能. 相似文献
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《Journal of Systems Architecture》2007,53(7):369-378
In this paper, we present an implementation of the image compression technique set partitioning in hierarchical trees (SPIHT) in programmable hardware. The lifting based Discrete Wavelet Transform (DWT) architecture has been selected for exploiting the correlation among the image pixels. In addition, we provide a study on what storage elements are required for the wavelet coefficients. A modified SPIHT (Set Partitioning in Hierarchical Trees) algorithm is presented for encoding the wavelet coefficients. The modifications include a simplification of coefficient scanning process, use of a 1-D addressing method instead of the original 2-D arrangement for wavelet coefficients and a fixed memory allocation for the data lists instead of the dynamic allocation required in the original SPIHT. The proposed algorithm has been illustrated on both the 2-D Lena image and a 3-D MRI data set and is found to achieve appreciable compression with a high peak-signal-to-noise ratio (PSNR). 相似文献
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Microsystem Technologies - The paper discusses a unique method to design low power circuits, which is called Gate Diffusion Input (GDI) method. Complex functions can be implemented using only two... 相似文献
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Numerous VLSI architectures for 2-D discrete wavelet transform (DWT) have been brought forward. While most of the designs
displayed good performance through parallel processing, few of them addressed thoroughly how to sustain such high throughput
computing which is crucial in real-time applications. Although the affordable data transfer bandwidth has been increased tremendously
during the past decade, the pressure on data communication has not yet been relieved from stream-intensive applications. The
design of 2-D DWT belongs to such cases. In this paper, we expose the performance gap between the computing core and the entire
system, distinguishing them by quantitative approach with metrics of peak performance and mean-time performance. In order
to narrow down the discrepancy without degrading either of the two criteria, on the one hand, we introduce a software-pipelining lifting-based computing kernel to remove data dependence for peak performance, on the other hand, we apply loop fusing technique
and a hierarchical pipelining method to enhance data locality and boost the mean-time performance. The architecture has been
implemented in Xilinx Virtex-II FPGA, taking advantage of Virtex-II’s embedded multipliers and block RAMs. We use Daubechies
(9, 7) and LeGall (5, 3) filters (the default lossy and lossless filters in JPEG2000) for illustration whereas it is a general
method for other DWT filters. The post-place and routing operation frequency for Daubechies (9, 7) is 138 MHz. Notably, the
mean-time performance parameterized by image size and decomposition level achieves closely to peak performance.
Chunhui Zhang received his B.S. degree in Electronic Engineering and his M.S. degree in Microelectronics both from Tsinghua University, Beijing, China, in 1998 and 2001 respectively. He completed his Ph.D. in Electrical and Computer Enginnering from the University of California, Irvine. In 2005, he joined Intel in the Mobile Wireless Communication Group. His research interests include VLSI architectures and algorithms for signal processing, reconfigurable computing, and memory access optimization for multimedia systems. Yun Long received B.S. in 1997 and M.S. in 2001, both in Electronic Engineering from Tsinghua University, China. While pursuing Ph.D. degree in Dept. of EECS, UC-Irvine, he is working with nVidia corp., Santa Clara, CA, on ASIC design and verification. His research interest includes high performance application specific system design, reconfigurable architecture, and data scheduling optimization, especially on multimedia applications. Fadi Kurdahi received his PhD from the University of Southern California in 1987. Since then, he has been a faculty at the Department of Electrical& Computer Engineering at UCI, where he conducts research in the areas of Computer Aided Design of VLSI circuits, high-level synthesis, and design methodology of large scale systems. He was Associate Editor for IEEE Transactions on Circuits and Systems II 1993–1995, Area Editor in IEEE Design and Test for reconfigurable computing, and served as program chair, general chair or on program committees of several workshops, symposia and conferences in the area of CAD, VLSI, and system design. He received the best paper award for the IEEE Transactions on VLSI in 2002, the best paper award at ISQED in 2006, and three distinguished paper awards. He is a Fellow of the IEEE. 相似文献
Chunhui ZhangEmail: |
Chunhui Zhang received his B.S. degree in Electronic Engineering and his M.S. degree in Microelectronics both from Tsinghua University, Beijing, China, in 1998 and 2001 respectively. He completed his Ph.D. in Electrical and Computer Enginnering from the University of California, Irvine. In 2005, he joined Intel in the Mobile Wireless Communication Group. His research interests include VLSI architectures and algorithms for signal processing, reconfigurable computing, and memory access optimization for multimedia systems. Yun Long received B.S. in 1997 and M.S. in 2001, both in Electronic Engineering from Tsinghua University, China. While pursuing Ph.D. degree in Dept. of EECS, UC-Irvine, he is working with nVidia corp., Santa Clara, CA, on ASIC design and verification. His research interest includes high performance application specific system design, reconfigurable architecture, and data scheduling optimization, especially on multimedia applications. Fadi Kurdahi received his PhD from the University of Southern California in 1987. Since then, he has been a faculty at the Department of Electrical& Computer Engineering at UCI, where he conducts research in the areas of Computer Aided Design of VLSI circuits, high-level synthesis, and design methodology of large scale systems. He was Associate Editor for IEEE Transactions on Circuits and Systems II 1993–1995, Area Editor in IEEE Design and Test for reconfigurable computing, and served as program chair, general chair or on program committees of several workshops, symposia and conferences in the area of CAD, VLSI, and system design. He received the best paper award for the IEEE Transactions on VLSI in 2002, the best paper award at ISQED in 2006, and three distinguished paper awards. He is a Fellow of the IEEE. 相似文献
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基于FPGA的并行DDS信号发生器的设计与实现 总被引:1,自引:0,他引:1
针对DDS(直接数字频率合成)电路的运算速度受相位累加器的累加速度和ROM读取速度的约束问题,采用多路并行和流水线相结合的方法改进了DDS电路的结构,有效地扩展了DDS电路的输出带宽。通过在FPGA内设计基于双DDS电路结构的信号发生器,用数字的方法直接实现了标准波形和各种调制波形的双通道输出。该方案结构简单,控制灵活,实验测试结果表明,该信号发生器能输出稳定、高带宽、高速度、高精度的信号波形。 相似文献
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无人机系统常采用脉冲宽度调制信号(PWM)控制舵机执行机构,在进行飞行控制系统闭环半物理仿真中,需要实时采集舵机控制信号作为无人机模型的控制输入,进而构成闭环仿真.提出并实现了一种以FPGA为核心的PWM信号转换器的设计,给出了PWM信号转换器各部分模块的详细设计,并用Verilog在FPGA中实现了其全部功能.在对FPGA设计的PWM信号转换器模块功能仿真和时序仿真正确后,下载到Altera开发板中进行验证.测试结果表明,利用FPGA设计的PWM信号转换器模块具有测量精度高、简单高效的特点,满足了实时仿真的要求. 相似文献
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小波变换在ECG信号处理中的应用得到了很多研究人员的关注。本文研究了5层5/3提升小波变换及其反变换的FPGA实现,并将其应用于ECG信号的压缩,在均方误差可控的范围内获得了较大的压缩比,并利用设计的硬核实现了信号的重建。 相似文献
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介绍了一种基于FPGA的高性能视频信号采集与显示系统的硬件设计与实现,模数转换系统采用高性能的A/D采集电路,通过高速的FPGA控制,将采集到的数据进行处理后,通过系统中的PCI接口传输给监控系统以供显示、监控等功能的实现。本模块已经投入运行,性能稳定。 相似文献
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