基于Verilog HDL的高速可综合FSM设计

有限状态机（finite state machine,FSM）广泛应用于数字系统的控制器设计中,用Verilog设计的可综合状态机有多种编码风格,通常这些编码风格生成的状态机带有组合逻辑输出.时序分析指出组合逻辑输出型状态机不适合高速系统,提出了一种适合高速系统的寄存器输出型状态机.最后通过实例给出了寄存器输出型状态机的状态编码方法及其可综合Verilog编码风格.     

基于FPGA的航空发动机电子控制器设计技术研究

基于FPGA的并行运行、可重配置以及采用软/硬件协同设计的技术特点,提出了一种基于FPGA的片内分布式航空发动机电子控制器设计方法。重点研究了FPGA内嵌处理器选型、硬件协处理器及同步数据总线设计等3个关键技术问题。在此基础上,基于Altera FPGAEP2C35设计了控制器原理样机,并进行了硬件性能测试,结果表明该控制器设计方法在当前的技术条件下具有实施的可行性。所提出的发动机电子控制器设计方法有利于克服当前集中式电子控制器设计时存在的软件高度定制、可重用性差、并行实时任务开发难度大、开发效率低等缺     

A Youla–Kučera parameterization approach to output feedback relatively optimal control

This paper presents a continuous time solution to the problem of designing a relatively optimal control, precisely, a dynamic control which is optimal with respect to a given initial condition and is stabilizing for any other initial state. This technique provides a drastic reduction of the complexity of the controller and successfully applies to systems in which (constrained) optimality is necessary for some “nominal operation” only. The technique is combined with a pole assignment procedure. It is shown that once the closed-loop poles have been fixed and an optimal trajectory originating from the nominal initial state compatible with these poles is computed, a stabilizing compensator which drives the system along this trajectory can be derived in closed form. There is no restriction on the optimality criterion and the constraints. The optimization is carried out over a finite-dimensional parameterization of the trajectories. The technique has been presented for state feedback. We propose here a technique based on the Youla–Kučera parameterization which works for output feedback. The main result is that we provide conditions for solvability in terms of a set of linear algebraic equations.     

Sequential algorithm for low-power encoding internal states of finite state machines

A heuristic method for encoding internal states (state assignment) of finite state machines (FSMs) so as to reduce their power consumption is proposed. A feature of the proposed approach is that the state assignment procedure takes into account the activity function of the memory elements when the FSM transits from a current state to other states that have already been encoded. A procedure for determining the power consumption of the FSM based on the codes of its internal states and probabilities of appearance of units at each input of the FSM is described. Experiments showed that the proposed approach makes it possible to reduce the power consumption of the FSM by 39% on the average compared with the NOVA algorithm and sometimes by 68%. In conclusion, the possibilities of improving the performance of the proposed algorithm in the synthesis of a specific FSM are discussed and promising directions of further research are indicated.     

基于函数级FPGA原型的硬件内部进化

电路进化设计是现阶段可进化硬件（EHW）研究的重点内容，针对制约进化设计能力的主要“瓶颈”，该文提出并讨论了一种简洁高效的内部进化方法，包括基于函数变换的染色体高效编码方案，与之配套的函数级FPGA原型和进化实验平台以及在线评估与遗传数自适应方法等，交通灯控制器，4位可级联比较器等相对复杂且具应用价值的电路的成功进化，证明该方法适用于组合，时序电路的进化设计，并可显著地减少运算量，提高进化设计的速度和规模。     

基于NiosⅡ的U盘安全控制器设计与实现

针对U盘等存储设备的安全隐患及用户的安全需求,分析目前常见的解决方法,遵循灵活方便、高安全性的原则,利用SoPC技术,设计实现了一款基于NiosⅡ的U盘安全控制器.详细论述了安全控制器的系统设计、硬件架构、固件划分和工作流程.采用高强度的密码算法,对普通U盘中的数据进行扇区级的加解密,保证U盘中数据的安全,具有灵活安全...     

Relatively optimal control and its linear implementation

Motivated by the fact that determining a feedback solution for the optimal control problem under constraints is a hard task we introduce the concept of relative optimality, roughly optimality for a specific (nominal) plant initial condition. We consider a generic discrete-time finite-horizon constrained optimal control problem for linear systems, and we seek for a state feedback (possibly dynamic) controller. As a fundamental requirement, we do not admit preactions or controller-state initialization based on the plant initial state and we assume our controller to be time-invariant. In particular, we do not consider controllers simply achieved by the feedforward and tracking of the optimal trajectory. A relatively optimal control is a stabilizing controller such that, if initialized at its zero state, produces the optimal (constrained) trajectory for the nominal initial condition of the plant. We show that one of such controllers is linear, dead-beat, and its order is equal to the length of the horizon minus the plant order, thus, of complexity which is known a priori. Some additional features such as the assignment of the compensator poles to achieve strong stabilization are proposed. We show that, by means of the proposed approach, we can face several problems such as optimal point-to-point operations, optimal impulse response and optimal tracking.     

一种逆向分析协议状态机模型的有效方法

网络协议的逆向分析技术无论对可信软件的验证、保护还是对恶意软件机理的分析都具有重要用途。由于协议的内在复杂性,重构与其源程序一致的高级模型对分析尤为有益,其中又以有限状态机模型最为典型。建立一种重构网络协议状态机模型的有效方法,主要依据所记录的协议会话的消息流及协议软件实际执行的指令流,通过对指令流反编译并应用改进的形式分析及验证技术构建出状态对象、转移关系及状态转移条件。该方法从协议的会话实例重构出充分一般的状态机模型,效率可行并具有逻辑上可证明的精确性。在详细阐述理论基础之后,也讨论了该方法的实现和应用。     

基于PSoC的数控运动控制器

采用PSoC可编程片上系统设计了一个数控运动控制器,由于PSoC具有灵活的可自由配置的模拟、数字资源和输入输出接口以及对多种通信接口的支持,该运动控制器具有良好的可扩展性和可移植性。介绍了系统的整体结构、控制器的硬件模块设计以及直线、圆弧、Nurbs曲线插补方式和速度控制方案的软件实现,使用该控制器控制一台三轴雕刻机进行雕刻,结果表明该系统具有良好的性能。     

椭圆曲线点乘的抗故障攻击FSM控制器设计

为提高有限状态机(FSM)控制器的抗故障攻击能力,提出一种非并发故障检测方案。方案利用线性码的故障检错特性,通过在状态机电路中建立故障传播路径来实现。设计了基于NAF编码的从左至右扫描点乘算法的安全有限状态机电路,并对该电路进行了仿真验证与分析。通过仿真验证,与并发故障检测方案相比,该设计能够在减少状态机频繁译码工作量的情况下,正确检测错误并报警,提高了抗故障攻击能力。     

基于DSP的直线直流电机数字控制器设计

为了实现短行程直线直流电机的位置伺服控制,设计了一种基于DSPTMS320F2812的数字控制器。数字控制器的硬件电路采用总线隔离驱动技术进行了系统扩展,主要对16位双极性A/D转换器、16位双极性D/A转换器和直线位移检测电路的原理及实现方法进行了描述。实际应用结果表明,基于DSP的数字控制器的硬件设计是合理的,并能可靠的运行。     

Reconfiguration point decision method based on dynamic complexity for reconfigurable manufacturing system (RMS)

To address the problem of how to identify the best time to implement reconfiguration for the reconfigurable manufacturing system (RMS), a dynamic complexity-based RMS reconfiguration point decision method is proposed. This method first identifies factors that affect RMS dynamic complexity (including both positive and negative complexity) at the machine tool and manufacturing cell levels. Next, based on information entropy theory, a quantitative model for RMS dynamic complexity is created, which is solved via state probability analysis for processing capability and the processing function. This model is combined with cusp catastrophe theory to establish an RMS reconfiguration decision model. Both positive and negative complexity are control variables for cusp catastrophe. Cusp catastrophe’s state condition is used to identify RMS state catastrophe at the final stage of production. This catastrophe point is the RMS reconfiguration point. Finally, the case study result shows that this method can effectively identify the RMS state catastrophe moment so that system reconfiguration is implemented promptly to improve RMS’s responsiveness to the market.     

The use of evolutionary programming based on training examples for the generation of finite state machines for controlling objects with complex behavior

It is proposed to use evolutionary programming to generate finite state machines (FSMs) for controlling objects with complex behavior. The well-know approach in which the FSM performance is evaluated by simulation, which is typically time consuming, is replaced with comparison of the object’s behavior controlled by the FSM with the behavior of this object controlled by a human. A feature of the proposed approach is that it makes it possible to deal with objects that have not only discrete but also continuous parameters. The use of this approach is illustrated by designing an FSM controlling a model aircraft executing a loop-the-loop maneuver.     

面向峰值电流优化的FSM状态分配

有限状态机(FSM)状态分配与峰值电流有密切关系.针对峰值电流过大易导致电路失效的问题,提出2种优化峰值电流的方法.1)提出一种考虑峰值电流和动态功耗的成本函数,采用遗传算法对两者进行同时优化;2)首先基于遗传算法得到功耗优化后的状态分配解,然后提出基于布尔可满足性(SAT)的启发式算法对功耗优化的状态分配进行重新编码,以降低峰值电流.将这2种方法应用于LGSynth93标准电路的实验结果表明,与传统的功耗优化算法相比,第1种方法虽然功耗略有增加,但能有效地降低峰值电流;第2种方法在实现不增加功耗额外开销的前提下能有效地降低峰值电流,并可将其有效地集成到不同的FSM功耗优化算法中,获得低功耗、低峰值电流的FSM状态分配解.     

GIS间隔控制器的研究与开发

研究基于IEC61850标准的GIS间隔控制器,阐述以ARM9微处理器为核心的GIS间隔控制器嵌入式硬件平台。以GIS间隔控制器的需求功能为依据、以IEC61850建模思想为指导,建立GIS间隔控制器的标准化信息模型。将GIS间隔控制器硬件作为载体,实现 GOOSE报文通信,使GIS间隔控制器具备符合IEC61850标准的过程层通信功能,完成GIS与间隔层保护、测量装置间开关位置信息和控制信息传输的数字化。通过GPS和报文分析工具搭建实验平台,结果证明,GIS控制器通信服务符合变电站装置智能化的设计需求。     

普适计算广播安全协议的研究

广播是普适计算环境中最基本的一种通信方式。对广播通信安全协议的研究显得十分重要。点对点的鉴别模式并不适用于广播安全;数字签名方法则对普适计算硬件要求太高。给出一种基于对称密钥算法的安全鉴别方案,通过对密钥发布方式的改进,满足普适计算硬件环境的广播安全鉴别,对μTESLA进行改进,避免了其由于时间同步错误导致的节点攻击。改进的方案获得更高的安全性能。     

基于FPGA的RC4加密算法设计及实现

针对通信安全问题,采用自顶向下的设计方法,设计了一种RC4算法基于FPGA的实现方式,实现了通信数据的加密传输。根据RC4加密算法的原理和设计流程,使用Verilog HDL编程语言,采用有限状态机（FSM）的编程方式实现算法,通过Modelsim SE 10.1a仿真软件进行仿真,并在FPGA开发板上进行验证。采用本文提出的FPGA设计方法实现的RC4加密算法相比软件加密方式和已有的FPGA实现方式速度有明显提高。     

Adaptive fault-tolerant control of non-linear systems: an improved CMAC-based fault learning approach

The conventional cerebellar model articulation controllers (CMAC) learning scheme equally distributes the correcting errors into all addressed hypercubes, regardless of the credibility of those hypercubes. This paper presents the adaptive fault-tolerant control scheme of non-linear systems using a fuzzy credit assignment CMAC neural network online fault learning approach. The credit assignment concept is introduced into fuzzy CMAC weight adjusting to use the learned times of addressed hypercubes as the credibility of CMAC. The correcting errors are proportional to the inversion of learned times of addressed hypercubes. With this fault learning model, the learning speed of fault can be improved. After the unknown fault is estimated, online, by using the fuzzy credit assignment CMAC, the effective control law reconfiguration strategy based on the sliding mode control technique is used to compensate for the effect of the fault. The proposed fault-tolerant controller adjusts its control signal by adding a corrective sliding mode control signal to confine the system performance within a boundary layer. The numerical simulations demonstrate the effectiveness of the proposed CMAC algorithm and fault-tolerant controller.     

Digital redesign of uncertain systems with state and input delays using evolutionary programming

This paper presents two novel issues: (i) digital modeling of the analog uncertain system in the presence of state and input delays and unstructured large parametric uncertainties; and (ii) digital redesign of the analog robust output tracking controller for the parametric uncertain system with state and input delays. The Newton's forward formula together with the evolutionary programming (EP) is utilized to find an equivalent discrete-time time-delayed parametric uncertain model of the continuous-time parametric uncertain system with multiple delays in both the state and input. Also, based on the EP global optima-search technique, the integration of the available analog robust controller and a parameter tuning algorithm is established to find a practically implementable "best" digital controller for the analog time-delayed uncertain system. The worst-case parameter set obtained from the analog time-delayed uncertain system with respect to the implemented "best" digital controller is searched to show the capability of the proposed robust digital controller.