Power and delay efficient fir filter design using ESSA and VL-CSKA based booth multiplier

FIR filter plays a major role in digital image processing applications. The power and delay performance of any FIR filter depends on the switching activities between the filter coefficients (FCs) and its basic arithmetic operations (i.e., multiplication and addition) performed in the convolution equations. In this paper, a new FIR filter is designed using Enhanced Squirrel Search Algorithm (ESSA) and Variable latency Carry skip adder (VL-CSKA) based booth multiplier. The proposed ESSA algorithm selects an optimal FC by minimizing the switching activities of FC based on the ripple contents, power and Transition width parameter to meet the required specifications of FIR filter in the frequency domain. Also, the VL-CSKA based booth multiplier is proposed to reduce the delay of FIR filter with parallel addition of partial products (PPs). In this design, the VL-CSKA adders utilize variable size and compound gate-based skip logic to deduce the delay with low power. The proposed FIR filter is simulated in Xilinx working platform by developing Verilog coding. The simulation result shows that the proposed FIR filter outperforms the state-of-the-art FIR filters by consuming only 0.142 mW power with delay of 28.175 ns.     

A novel power efficient 0.64-GFlops fused 32-bit reversible floating point arithmetic unit architecture for digital signal processing applications

Floating point digital signal processing technology has become the primary method for real time signal processing in most digital systems presently. However, the challenges in the implementation of floating point arithmetic on FPGA are that, the hardware modules are larger, have longer latency and high power consumption. In this work, a novel efficient reversible floating point fused arithmetic unit architecture is proposed confirming to IEEE 754 standard. By utilizing reversible logic circuits and implementation with adiabatic logic, power efficiency is achieved. The hardware complexity is reduced by employing fused elements and latency is improved by decomposing the operands in the realization of floating point multiplier and square root. To validate the design, the proposed unit was used for realization of FFT and FIR filter which are important applications of a DSP processor. As detection is one of the core baseband processing operations in digital communication receivers and the detection speed determines the data rates that can be achieved, the proposed unit has been used to implement the detection function. Simulation results and comparative studies with existing works demonstrate that the proposed unit efficiently utilizes the number of gates, has reduced quantum cost and produced less garbage outputs with low latency, thereby making the design a computational and power efficient one.     

CNFET-based approximate ternary adders for energy-efficient image processing applications

Nowadays, low power design has attracted more attentions. This purpose is achieved through some techniques such as low-power design methods, multiple valued logic and more recently by approximate computing. Carbon nanotube field-effect transistor (CNFET) is an appropriate candidate device for low-power multiple valued logic applications. In approximate computing, reducing the precision of arithmetic blocks leads to reduction in power consumption. In this paper, two approximate CNFET-based ternary full adder cells are proposed. The proposed designs considerably reduce the design complexity and the number of transistors by utilizing the unique properties of CNFETs as well as the switching logic style. The simulation results demonstrate that the proposed approximate designs improve the delay, power and energy dissipation by about 90% as compared to their exact counterparts. Also, as the adder cells are commonly used in the reduction step of multiplier circuits, the efficiency of the proposed cells is investigated in the structure of ternary multipliers through the normalized error distance and power-error tradeoff metrics. Moreover, as the approximate circuits are used in image processing applications, an inexact ternary multiplier is utilized for pixel by pixel image multiplying and the results are compared with the exact ones. According to the simulation results, the proposed inexact methods enhance the performance of arithmetic circuits while maintaining the required accuracy for such applications.     

FPGA implementation of XOR-MUX full adder based DWT for signal processing applications

In the recent past there is a rapid development in the field of digital technology especially in signal processing and image processing based applications Excellent performance high speed, compactable in size low power and less delay are the essential needs of the devices used for applications such as signal processing, audio processing and software define radio and so on. Particularly, digital gadgets are prone to have more critical logic size and power consumption and take large area in VLSI Implementation due to arithmetic operations of adders and multiplier designs. Thus priority architecture of Digital Wavelet Transform (DWT) is affected as it comprises a number of Filter banks in level basics, thus all Filter banks have number of adders and multipliers due to coefficient decompositions of low and high pass filters. On this n-size repeated filter logic takes more logic size and power consumption. Here, the proposed work presents a novel approach of DWT by replacing conventional adders and multipliers with XOR-MUX adders and Truncations multipliers thereby reducing the 2n logic size to n-size logic. Finally, the proposed DWT architecture designed in VHDL and also implemented in FPGA XC6SLX9-2TQG144 proved the performance in terms of delay, area and power.     

Design of low power multi-ternary digit multiplier in CNTFET technology

This work introduces the method to implement energy efficient designs of arithmetic units such as a ternary full adder, ripple carry adder, single-trit multiplier and multi-trit multiplier using carbon nanotube field effect transistors (CNTFETs). A CNTFET unique feature of the threshold voltage variation by changing the CNT diameter, make it a suitable alternative for being employed in ternary logic designs. In designing the proposed circuits, decoder circuit functionality is realized by various threshold detector circuits tuned to a specific logical threshold voltage value. The multiplier circuit is designed by combing the capacitive logic and the minority function. In order to test the practicability of proposed circuits in cascaded circuits, multi-digit adder and multiplier circuits are constructed. The proposed multi-digit multiplier structure is based on classical Wallace multiplier and includes various optimized versions of adder and multiplier circuits. Extensive simulation has been done to examine the competency of proposed designs under different test conditions. The design of 3-trit multiplier formed by combing the proposed adder and multiplier circuits shows 16 times reduction in power consumption as well as energy consumption in comparison to previous multiplier design.     

基于互补电阻开关的忆阻乘法器设计

现有的忆阻算术逻辑多采用单个忆阻器作为存储单元,在忆阻交叉阵列中易受到漏电流以及设计逻辑电路时逻辑综合复杂度高的影响,导致当前乘法器设计中串行化加法操作的延时和面积开销增加。互补电阻开关具有可重构逻辑电路的运算速度和抑制忆阻交叉阵列中漏电流的性能,是实现忆阻算术逻辑的关键器件。提出一种弱进位依赖的忆阻乘法器。为提升忆阻器的逻辑性能,基于互补电阻开关电路结构,设计两种加法器的优化方案,简化操作步骤。在此基础上,通过改进传统的乘法实现方式,并对进位数据进行拆解,降低运算过程中进位数据之间的依赖性,实现并行化的加法运算。将设计的乘法器映射到混合CMOS/crossbar结构中,乘法计算性能得到大幅提高。在Spice仿真环境下验证所提乘法器的可行性。仿真实验结果表明,与现有的乘法器相比,所提乘法器的延时开销从O(n²)降低为线性级别,同时面积开销降低约70%。     

Design and implementation of low power and high speed multiplier using quaternary carry look-ahead adder

Need of Digital Signal Processing (DSP) systems which is embedded and portable has been increasing as a result of the speed growth of semiconductor technology. Multiplier is a most crucial part in almost every DSP application. So, the low power, high speed multipliers is needed for high speed DSP. Array multiplier is one of the fast multiplier because it has regular structure and it can be designed very easily. Array multiplier is used for multiplication of unsigned numbers by using full adders and half adders. It depends on the previous computations of partial sum to produce the final output. Hence, delay is more to produce the output. In the previous work, Complementary Metal Oxide Semiconductor (CMOS) Carry Look-ahead Adders (CLA) and CMOS power gating based CLA are used for maximizing the speed of the multiplier and to improve the power dissipation with minimum delay. CMOS logic is based on radix 2(binary) number system. In arithmetic operation, major issue corresponds to carry in binary number system. Higher radix number system like Quaternary Signed Digit (QSD) can be used for performing arithmetic operations without carry. The proposed system designed an array multiplier with Quaternary Signed Digit number system (QSD) based Carry Look-Ahead Adder (CLA) to improve the performance. Generally, the quaternary devices require simpler circuit to process same amount of data than that needed in binary logic devices. Hence the Quaternary logic is applied in the CLA to improve the speed of adder and high throughput. In array multiplier architecture, instead of full adders, carry look-ahead adder based on QSD are used. This facilitates low consumption of power and quick multiplication. Tanner EDA tool is used for simulating the proposed multiplier circuit in 180 nm technology. With respect to area, Power Delay Product (PDP), Average power proposed QSD CLA multiplier is compared with Power gating CLA and CLA multiplier.     

一个并行高速乘法器芯片的设计与实现

本文介绍了一种并行高速乘法器的设计原理与方法。该乘法器基于一片ＦＰＧＡ芯片实现，应用在通用数字神经处理芯片中，运作良好，工作主频可达３０ＭＨＺ，达到了预期的目标。同时，这个高速乘法器也可用作ＤＳＰ数字信号处理器的基本运算单元     

Partial product addition in Vedic design-ripple carry adder design fir filter architecture for electro cardiogram (ECG) signal de-noising application

Design of adder plays a major role in deciding overall performance of system as it is a major building block through generations of design in an innovative design of circuits. In VLSI system and signal processing field applications, various versions of adders are utilized. In applications of signal processing, in recent days, major role is contributed by Finite Impulse Response (FIR) filter. Various authors and papers described its design in a several ways. With the design of effective multiplier, signal denoising application was not explained by any of the existing works. For the generation of partial products, 8-bit multiplier based on a Vedic Mathematics –UrdhvaTiryagbhyam sutra- is proposed in this work. In Vedic multiplier, carry skip method is used for realizing addition of partial product. Four Vedic multipliers of 4 × 4 size are used for designing 8-bit multiplier. Carry skip and UrdhvaTiryagbhyam methods are used for this design. For addition of partial product, this multiplier is designed. Ripple carry adder's logic levels are modified for adding these Vedic multiplier's output. Powerful elimination of ECG noise can be done using this proposed fast FIR filter. In applications of healthcare and biomedical field, they are used. In Vedic design, Ripple Carry Adder (RCA) is used for carrying out partial product addition. Operation of FIR filter with Electro Cardiogram (ECG) signal is done by proposing architecture of FIR filter. It is termed as PPAVD-RCA-FIR and used in de-noising applications. From de-noised signal, Signal to Noise Ratio (SNR), Bit Error Rate (BER) and Mean Square Error (MSE) are computed, which are used for evaluating the performances. When compared with general Vedic multiplier, speed of the proposed design is increased about 13.65% as shown by results.     

Design and analysis of high-speed 8-bit ALU using 18 nm FinFET technology

All modern computational devices consist of ALU. With increase in complexity of software and the consistent shift of software towards parallelism, high speed processors with hardware support for time consuming operations such as multiplication would benefit. Smaller, compact devices such as IoT devices need to run software such as security software and be able to offload computation cost from the cloud. In this paper, a high speed 8-bit ALU using 18 nm FinFET technology is proposed. The arithmetic and logical unit consists of fast compute units such as Kogge Stone fast adder and Dadda multiplier along with basic logic gates. In this paper, an ALU with each compute unit optimized for speed is proposed, while responsibly consuming area. Dadda multiplier is of 8 × 8 architecture as opposed to conventional approach of 4 × 4 making it a true 8-bit ALU. Simulation and analysis is done using Cadence Virtuoso in Analog Design Environment. The transistor count of proposed design is 5298, the power consumption is 219 µW and maximum delay is 166.8 ps. The design is also expected to consume a maximum of one clock cycle for any computation.

     

基于四叉树的高速乘法器算法研究

提出了一种基于四叉树结构的高速乘法器自动综合优化算法以提升乘法器运算速度。首先对延时较大的高位积采用四叉树递归直接构建,取代传统部分积进位链,缩短关键路径时延,进而进行分支折合和合并,相邻乘法结果共享部分四叉树,降低硬件开销。算法同时支持不同面积约束下的自动综合。依此算法的乘法器相比基于Booth算法和Wallace树的乘法器速度提高了10%。     

An area- and energy-efficient hybrid architecture for floating-point FFT computations

Floating-point fast Fourier transform (FFT) has been widely expected in scientific computing and high-resolution imaging applications due to the wide dynamic range and high processing precision. However, it suffers high area and energy overhead problems in comparison to fixed-point implementations. To address these issues, this paper presents an area- and energy-efficient hybrid architecture for floating-point FFT computations. It minimizes the required arithmetic units and reduces the memory usage significantly by combining three different parts. The serial radix-4 butterfly (SR4BF) is used in the single-path delay commutator (SDC) part to minimize the required arithmetic units with 100% adder utilization ratio obtained. A modified single-path delay feedback (MSDF) architecture is proposed to achieve a tradeoff between arithmetic resources and memory usage by using the new half radix-4 butterfly (HR4BF) with 50% adder utilization ratio obtained. The intermediate caching buffer is modified accordingly in the MSDF part. By combining both the advantages on arithmetic units reducing and memory usage optimization in different parts, the optimized area and power are obtained without throughput loss. The logic synthesis results in a 65 nm CMOS technology show that the energy per FFT is about 331.5 nJ for 1024-point FFT computations at 400 MHz. The total hardware overhead is equivalent to 460k NAND2 gates.     

A novel ternary half adder and multiplier based on carbon nanotube field effect transistors

A lot of research has been done on multiple-valued logic (MVL) such as ternary logic in these years. MVL reduces the number of necessary operations and also decreases the chip area that would be used. Carbon nanotube field effect transistors (CNTFETs) are considered a viable alternative for silicon transistors (MOSFETs). Combining carbon nanotube transistors and MVL can produce a unique design that is faster and more flexible. In this paper, we design a new half adder and a new multiplier by nanotechnology using a ternary logic, which decreases the power consumption and chip surface and raises the speed. The presented design is simulated using CNTFET of Stanford University and HSPICE software, and the results are compared with those of other studies.     

一种改进型整数倍多相滤波器在FPGA中的应用

在现代通信系统中,到处都有数字信号处理（DSP）的应用。DSP设计人员的主要工具之一是有限脉冲响应（FIR）滤波器。为提高系统性能要求,所需要的FIR滤波器系数越多（有大量的抽头）,当然滤波器的响应也越好。由于大量的抽头增加了对逻辑资源的需求、增加了计算的复杂性,增加了功耗。在多速率信号处理系统中,特别是高倍数的抽取和...     

罗兰C前端数字带通滤波器设计与实现

分析了罗兰C信号的特征,并根据信号特征决定选用FIR滤波器,利用MATLAB工具设计了满足滤波要求的高阶数字带通滤波器。详细研究了分布式算法的原理和分布式算法在FPGA上实现FIR数字滤波器的方法。最终采用改进的分布式算法在FPGA上实现了127阶FIR数字带通滤波器。利用实际采集的信号进行仿真和现场测试,结果均显示由该方法设计的滤波器性能良好,方法简单易行,相对于传统的乘累加结构不仅能节省硬件资源,而且可以改善数据处理速度,具有一定的推广价值。     

宽频二阶程控低通滤波器的设计

设计了一种宽频二阶程控低通滤波器.二阶低通滤波电路由模拟乘法器、电流反馈运算放大器、可编程电阻网络及电容构成,充分利用了模拟乘法器和电流反馈运算放大器的优点,并通过主控电路调节数模转换电路的输出电压和低通滤波电路可编程电阻网络的值,实现截止频率程控.该滤波器具有截止频率高、信号处理范围宽、速度高等特点.     

VLIW处理器可重组乘法器单元设计

在VLIW多媒体芯片的设计过程中,针对传统乘法器与加法器的不足,提出了一种新的分叉华莱氏树结构的乘法器模型,采用可重用的模块化设计思想,通过重用一位全加器阵列对乘法器进行扩展,处理器可以在一个乘法器单元内部同时支持多个32/16/8位的乘法运算,同时使乘法单元的速度和面积均得以优化。仿真测试表明,新的乘法器结构可有效减少FFT、滤波等信号处理以及多媒体处理中常用算法的执行周期,提高了实际运行速度,进一步增强了VLIW处理器在多媒体与信号处理运算上的能力。     

基于GPS校准的数字式守时钟守时算法研究

通常守时系统都采用高稳晶体振荡器作为频率标准,但由于温度和老化等原因导致其长期稳定度不尽如人意,严重影响时钟的守时精度,改变电路的分频比可以对其进行补偿。数字式守时钟采用了固定频率晶振驱动的分频比可精细微调的基于加法器的时钟电路。首先介绍了一种GPS校准的数字式高精度守时钟并讲述了其工作原理,然后对如何快速、准确的在数字式守时钟中得到晶振的分频比补偿值进行了研究,提出了算术平均值滤波算法和卡尔曼滤波算法这两种算法,并搭建了实验平台。经验证,卡尔曼滤波算法在快速性和准确性上要优于算术平均值算法。     

高精度测频方法及其在四频激光陀螺中的应用

为了减小普通电子计数法测频时的±1量化误差,采用数字滤波来滤除量化噪声,设计了一种高精度测频电路.使用现场可编程逻辑阵列(FPGA)器件和VHDL语言设计了测频系统,对信号发生器所产生的标准信号的测量结果表明快速滤波基本消除了量化误差的影响,实现了高速、高精度测频.该方法具有等间隔测量的特点,已用于四频激光陀螺的测试研究.     

The secure wavelet transform

There has been an increasing concern for the security of multimedia transactions over real-time embedded systems. Partial and selective encryption schemes have been proposed in the research literature, but these schemes significantly increase the computation cost leading to tradeoffs in system latency, throughput, hardware requirements and power usage. In this paper, we propose a light-weight multimedia encryption strategy based on a modified discrete wavelet transform (DWT) which we refer to as the secure wavelet transform (SWT). The SWT provides joint multimedia encryption and compression by two modifications over the traditional DWT implementations: (a) parameterized construction of the DWT and (b) subband re-orientation for the wavelet decomposition. The SWT has rational coefficients which allow us to build a high throughput hardware implementation on fixed point arithmetic. We obtain a zero-overhead implementation on custom hardware. Furthermore, a Look-up table based reconfigurable implementation allows us to allocate the encryption key to the hardware at run-time. Direct implementation on Xilinx Virtex FPGA gave a clock frequency of 60 MHz while a reconfigurable multiplier based design gave a improved clock frequency of 114 MHz. The pipelined implementation of the SWT achieved a clock frequency of 240 MHz on a Xilinx Virtex-4 FPGA and met the timing constraint of 500 MHz on a standard cell realization using 45 nm CMOS technology.