A 6K-gate CMOS gate array

Combining advanced 2 /spl mu/m CMOS technology with a newly developed double layer metallization technology, a high-performance 6K-gate CMOS gate array has been developed, featuring an inverter propagation delay time of 0.4 ns with a power dissipation of 10 /spl mu/W/MHz/stage. As a demonstration vehicle of the high-performance gate array, a 16 bit/spl times/16 bit parallel multiplier has been designed and fabricated in which 3365 basic cells are used. Typical multiplying time has been measured to be 130 ns at a 5 MHz clock rate with a power dissipation of 275 mW.     

A triple-level wired 24K-gate CMOS gate array

A 24K-gate CMOS gate array has been developed using triple-level wiring and a hierarchical layout method. A typical delay time is 1.6 ns with a fanout of 3 and a 3-mm metal interconnect length. The master chip was designed to be freely divided into blocks. A previously developed digital signal processor has been realized on the array. The design time was reduced to 25% of the normal design cycle although the chip size is 3.3 times larger than was realized by a handcrafted design.     

A CMOS/SOS gate array with a new customization technique of cutting

A 770-gate single-level metallized Si-gate CMOS/SOS gate array has been fabricated using a new customization technique: cutting pre-defined n⁺epitaxial silicon lines. Simple process and quick turnaround time are both realized. Total fabrication steps are reduced to 53 percent of those of the double-level metallized CMOS/bulk gate array because of a simplified CMOS/SOS process and only three-mask customization. Customization steps are also reduced to 55 percent. High packing density and high switching speed comparable to those of the double-level metallized CMOS/bulk gate array are also obtained. The number of the silicon wiring channels of the conventional single-level metallized gate array is reduced by a factor of two by the cutting technique. This value corresponds to a 24 percent decrease in the chip area. Even with a conservative 4-µm technology, gate delay of 0.8 ns is obtained at the power-supply voltage VDDof 5 V. Up to 25 MHz operations are verified for a shift register. On this gate array a control unit for a CCD camera is fabricated; 95 percent of the internal basic cells are utilized. The active power dissipation of this unit is 1.0 mW at VDDof 5 V.     

CMOS/SOS automated universal array

The CMOS/SOS automated universal array (AUA) is a new, minimum-cost approach for generating custom LSI devices. This is achieved by implementing a compatible automatic placement and routing program which automatically generates a single, customized interconnect metal level that defines the desired logical function. The AUA topological design is specifically configured to be compatible with automatic layout techniques, and as a result the AUA system can guarantee 100 percent connectivity with greater than 90 percent gate utilization for any random-logic application. The CMOS/SOS AUA is an equivalent 800-gate design consisting of a repetitive pattern of 640 basic internal cells and 62 basic peripheral cells for I/O functions, as well as a variety of special cells located in the periphery which meet the needs of most digital applications that may be encountered. Depending on the logic design complexity and computer used, an artwork tape depicting the metallized layout pattern can be generated within 24 h.     

Submicrometer polysilicon gate CMOS/SOS technology

A process is described for the fabrication of CMOS/SOS submicrometer devices and integrated circuits. The process utilizes the lateral diffusion of boron into polycrystalline silicon and a subsequent anisotropic etchant to define the narrow poly gates. Devices with channel lengths as small as 0.3 µm have been fabricated and characterized. Both avalanche and tunnel injection of carriers into the gate dielectric have been measured and both can have an impact on the limit of voltage operation. At present, these mechanisms appear to place an upper limit of about 8 V on the operating voltage of dynamic circuits containing 0.5- µm channel length devices. The propagation delay of 0.5-µm channel length CMOS/SOS inverters is about 200 ps at 5 V and dynamic binary counters will operate with a maximum input frequency of 550 MHz and 8 V while dissipating 130 mW.     

A 6 K-gate GaAs gate array with a new large-noise-margin SLCF circuit

A 6 K-gate GaAs gate array has been successfully designed and fabricated using a novel large-noise-margin Schottky-diode level-shifter capacitor-coupled FET logic (SLCF) circuitry and a WN/SUB x/ gate selfaligned lightly doped drain (LDD) structure GaAs MESFET process. Chip size was 8.0/spl times/8.0 mm/SUP 2/. A basic cell can be programmed as an SLCF inverter, a two-input NOR, or a two-input NAND gate. The unloaded propagation delay time was 76 ps/gate a 1.2-mW/gate power dissipation. The increases in delay time due to various loading capacitances were 10 ps/fan-in, 45 ps/fan-out, and 0.64 ps/IF. A 16-b serial-to-parallel-to-serial (S/P/S) data-conversion circuit was constructed on the gate array as an application example. A maximum operation frequency of 852 MHz was achieved at a 952-mW power dissipation, including I/O buffers.     

A subnanosecond 2000 gate array with ECL 100K compatibility

This paper describes a subnanosecond gate array with 2000 gate complexity using an advanced bipolar process. The high performance of this process and the optimized circuit design have made it possible to achieve a 700-ps delay time for a basic ECL gate under a general usage condition of a 3 fan-in, 3 fan-out and 3-mm wiring length, in spite of a low power dissipation of 1.9 mW/gate. A 450-MHz typical toggle frequency has been obtained by using a series-gated flip-flop. Utilizing the integrated computer aided design (CAD) system, a quick and error-free design can be achieved. As a result, 100 percent routability has been attained for automatic placement and wiring in spite of 90 percent cell utilization. Low thermal resistance (6°C/W) packages are employed for this LSI chip to enable installation in an air cooled system.     

A subnanosecond 2000 gate array with ECL 100K compatibility

Describes a subnanosecond-gate array with 2000 gates fabricated by an advanced bipolar process. A 700-ps delay time was achieved for a basic ECL gate under a general usage condition of a 3 fan-in, 3 fan-out and 3-mm wiring length, with power dissipation of 1.9 mW/gate. A 450-MHz typical toggle frequency has been obtained by using a series-gated flip-flop. Utilizing an integrated computer-aided design system, 100% routability has been attained for automatic placement and wiring in spite of 90% cell utilization. Low thermal resistance (6/spl deg/C/W) packages are used for this LSI chip to permit its installation in an air-cooled system.     

CAD-compatible high-speed CMOS/SIMOX gate array using field-shieldisolation

A specific 0.5 μm CMOS/SIMOX technology was developed for a gate array/sea of gate (SOG) using field-shield (FS) isolation to overcome a pending problem of source-to-drain breakdown voltage (BV_ds) lowering. FS isolation is capable of improving BV_ds because surplus holes generated by impact ionization at the drain region are collected through the body region under the FS gate. BV_ds was maintained at a level of junction breakdown before reaching the punchthrough limitation at a gate length of around 0.3 μm using the FS isolation. The FS isolation technique was successfully applied to an SOG gate array on a SIMOX substrate. The gate array has the same area as that on the bulk-Si and is compatible to a conventional bulk-Si CAD system because the layout is basically the same. A 53-stage ring oscillator fabricated on the FS isolated SOG gate array exhibited 1.7 times higher speed operation than that on a bulk-Si counterpart, keeping low power consumption characteristics up to a drain voltage of 3 V     

A CMOS gate array architecture for digital signal processingapplications

A new CMOS gate array architecture for digital signal processing (DSP) is presented. The basic cell structure takes into account the high degree of regularity of DSP datapaths. Therefore, it supports in particular the implementation of systolic arrays in connection with a pipelining scheme of one addition per half clock cycle. Together with a new gate array approach (macrocell design style), macrocells can be implemented efficiently on the new architecture. All DSP macrocells use dynamic transmission gate latches. Furthermore, the routing is done exclusively by cell abutment which results in short intercell routing. The macrocell design style is compared with the conventional gate array approach. In the common gate array approach, conventional gate array architectures are used together with conventional design equipment and layout strategies. The comparison shows a reduction in area and power consumption by a factor of 2.5 and 3.7, respectively. The efficiency increases by a factor of at least nine. These results were proved by analog circuit simulations and test chip measurements     

High-performance BiCMOS 100 K-gate array

A BiCMOS gate array in 0.8-μm technology with CMOS intrinsic gate delays of 100 ps plus 60 ps/fan-out and BiCMOS intrinsic delays of 200 ps with a 17-ps/fan-out drive factor is discussed. A compact base cell (750 μm²/gate) has been designed with full bipolar drive capability for the efficient layout of both primitive gates and large-arrayed macros, such as register files and multipliers. A 106 K-gate array has been built on a 1.14-cm² chip with ECL I/O capability. The place and route in three levels of metal provide array utilization greater than 90%. The gate array was used to implement a 74 K-gate filter design with testability features such as JTAG and two-phase scan     

A 20 K CMOS array with 200-ps gate delay

A 20 K NAND2 equivalent CMOS gate array prototype with 0.5-μm channel length FETs is described. The 7.5×7.5-mm chip is designed for high performance with 200-ps gate delay. Large macros such as a 32-b RISC (reduced instruction-set computer) processor and 128×8 SRAM (static random-access memory) have been implemented with automatic placement and wiring tools. Their respective predicted performances of 17-ns cycle and 6.1-ns access time have been verified. This confirms that the speed of complex functions in half-micrometer-channel-length CMOS technology is getting close to the speed achieved by current bipolar hardware     

CMOS/SOS serial-parallel multiplier

A 24-bit serial-parallel multiplier was integrated in CMOS/silicon-on-sapphire (SOS) technology on a 155 mil/spl times/170 mil chip. The operation of this multiplier is described, showing how the parallel loaded multiplier x combines with the serial loaded multiplicand, a, to form the serial product. An addend, b, can also be accommodated to produce ax+b. The design of the multiplier cells are based on functional majority logic adders and weak or trickle inverter master-slave latches. The chip operates at clock rates up to 18 MHz. Power dissipation at 10 MHz and V/SUB DD/ of 5 V is about 20 mW, and the energy consumption for multiplying two 16-bit numbers is about 64 nJ. Typical application areas are mentioned.     

A CMOS/SOS 4K static RAM

Discusses high density CMOS/SOS technology used to develop a fully static 4096-bit RAM with a five-transistor storage cell. Selection of a five-transistor memory cell has reduced the access to the flip-flop storage element to a single word line transistor and bit line. The word line transistor must be able to prevent data altering currents from entering the memory cell at all times except for the write operation. The write operation is enhanced by reducing the bias voltage across the memory cell, thereby making the current needed to alter the cell smaller. Through the use of a 5 /spl mu/m design rule, the memory cell occupies 2913 /spl mu/m/SUP 2/. The 4096-bit static CMOS/SOS RAM contains 22553 transistors in 20 mm/SUP 2/. Organised as 1024 4-bit words, the RAM has a read cycle time of 350 ns and standby power dissipation of 50 /spl mu/W at V/SUB cc/=5 V and temperature of 27/spl deg/C.     

A deep-submicrometer microwave/digital CMOS/SOS technology

0.35-μm complementary metal-oxide-semiconductor (CMOS)/silicon-on-sapphire (SOS) n- and p-channel MOSFETs with a metal-over-polysilicon T-gate structure for monolithic microwave integrated circuit (MMIC) and digital applications are reported. The measured values for the current-gain cutoff frequency f_T were ⩾20 GHz for both n-channel and p-channel devices, and the values for the unilateral power-gain cutoff frequency f_max were 37 GHz for the p-channel and 53 GHz for the n-channel MOSFETs. The low effective resistance of the T-gate structure contributed to the very high f_max values. It is believed that these are the highest f_T and f_max values ever reported for MOS devices. The potential of SOS submicrometer MOSFETs for microwave circuit applications is demonstrated     

A 4K CMOS gate array with automatically generated test circuits

A 2-/spl mu/m CMOS 4K-gate array using a newly devised scan bus method has been developed. This method is applied to the array by using a double-latch structure, parallel scanning, and normal-test common pin techniques. The gate array can be tested for 95-100% of all DC faults using computer-generated test circuits and test data, without placing restrictions on the logic design. Due to an access-to-output flip-flop structure and a gate-isolated three-input type basic cell, including embedded transistors, the area increase and operating speed degradation due to test circuits are considerably reduced. Furthermore, besides the flip-flop blocks, a built-in RAM macroblock is available. Degradation of operating speed is evaluated as 10%. The scan operation is done at a clock cycle of 120 ns, and the access time of the RAM macroblock is 34 ns. The gate array includes 4032 three-input gates on a 7.2/spl times/7.02-mm chip.     

CMOS/SOS EAROM memory arrays

A new low-voltage nonvolatile memory cell has been fabricated using standard CMOS/SOS processing. The cell can be programmed at 10 V, conducts 400 /spl mu/A when programmed, and can be erased either electrically or with UV light. Using this cell, a family of memories have been built which dissipate only 50 /spl mu/W at 5 V, retain data for 17.3 years at 125/spl deg/C, and have a WRITE/ERASE endurance in excess of 300 cycles.     

CMOS/SOS semi-static shift registers

Complementary metal-oxide-semiconductor (CMOS) technology has been combined with thin silicon on sapphire films (SOS) for the fabrication of shift registers designed for full TTL compatibility d.c. storage capability, 20 MHz operating frequency, single phase clock and data inputs, and double rail data outputs. Typical power dissipation levels were on the order of 500 nW per stage during standby and 250 /spl mu/W per stage when operating at 20 MHz.     

CMOS subnanosecond true-ECL output buffer

An emitter coupled logic (ECL) 100 K compatible output buffer circuit fabricated in a submicrometer CMOS-only process is presented. High speed (0.9-ns delay) and sufficient precision are achieved through the use of a novel circuit principle. Negative feedback and an error correction technique are applied in such a way that external components and/or additional power supplies are not required. Aspects of stability and accuracy are investigated and simulation results are discussed to explain the circuit technique. The actual design and practical aspects of it, such as layout, implementation in silicon, and technology features, are shown. Measured and simulation results, showing the good performance of the ECL output buffer across a wide range of capacitive loading, are presented