Polycrystalline silicon thin film transistors fabricated in various solid phase crystallized films deposited on glass substrates

In this work, we have characterized various types of polysilicon films, crystallized upon thermal annealing from films deposited by low pressure chemical vapor deposition in the amorphous phase and a mixed phase using silane or in the amorphous phase using disilane. Polysilicon thin film transistors (TFTs) were fabricated, at low processing temperatures, in these three types of films on high strain point Corning Code 1734 and 1735 glass substrates. Double layer films, with the bottom layer deposited in a mixed phase and the top in the amorphous phase, allowed TFT fabrication at a drastically reduced thermal budget; optimum values of thicknesses and deposition rates of the layers are reported for reducing the crystallization time and improving film quality. Optimum deposition conditions for TFT fabrication were also obtained for films deposited using disilane. The grain size distribution for all types of films was shown to be wider for a larger grain size. Fabricated TFTs exhibited field effect electron mobility values in the range of 20 to 50 cm²/V·s, subthreshold swings of about 0.5–1.5 V/dec and threshold voltage values of 2–4 V.     

Polycrystalline silicon thin films on glass by aluminum-inducedcrystallization

This work focuses on the development and characterization of device quality thin-film crystalline silicon layers directly onto low-temperature glass. The material requirements and crystallographic quality necessary for high-performance device fabrication are studied and discussed. The processing technique investigated is aluminum-induced crystallization (AIC) of sputtered amorphous silicon on Al-coated glass substrates. Electron and ion beam microscopy are employed to study the crystallization process and the structure of the continuous polycrystalline silicon layer. The formation of this layer is accompanied by the juxtaposed layers of Al and Si films exchanging places during annealing. The grain sizes of the poly-Si material are many times larger than the film's thickness. Raman and thin-film X-ray diffraction measurements verify the good crystalline quality of the Si layers. The electrical properties are investigated by temperature dependent Hall effect measurements. They show that the electrical transport is governed by the properties within the crystallites rather than the grain boundaries. The specific advantages of AIC are: (1) its simplicity and industrial relevance, particularly for the processes of sputter deposition and thermal evaporation, (2) it requires only low-temperature processing at 500°C, (3) its short processing times, and (4) its ability to produce polycrystalline material with good crystallographic and electrical properties. These advantages make the poly-Si material formed by AIC highly interesting and suitable for subsequent device fabrication such as for poly-Si thin-film solar cells     

Fabrication of thin film transistors by chemical mechanicalpolished polycrystalline silicon films

A top-gate p-channel polycrystalline thin film transistor (TFT) has been fabricated using the polycrystalline silicon (poly-Si) film as-deposited by ultrahigh vacuum chemical vapor deposition (UHV/CVD) and polished by chemical mechanical polishing (CMP). In this process, long-term recrystallization in channel films is not needed. A maximum field effect mobility of 58 cm²/V-s, ON/OFF current ratio of 1.1 10⁷, and threshold voltage of -0.54 V were obtained. The characteristics are not poor. In this work, therefore, we have demonstrated a new method to fabricate poly-Si TFT's     

Selected area laser-crystallized polycrystalline silicon thin films by a pulsed Nd:YAG laser with 355 nm wavelength

Selected area laser-crystallized polycrystalline silicon(p-Si) thin films were prepared by the third harmonics (355 nm wavelength) generated by a solid-state pulsed Nd:YAG laser.Surface morphologies of 400 nm thick films after laser irradiation were analyzed.Raman spectra show that film crystallinity is improved with increase of laser energy.The optimum laser energy density is sensitive to the film thickness.The laser energy density for efficiently crystallizing amorphous silicon films is between 440-634 mJ/cm2 for 300 nm thick films and between 777-993 mJ/cm~2 for 400 nm thick films.The optimized laser energy density is 634,975 and 1571 mJ/cm~2 for 300,400 and 500 nm thick films,respectively.     

脉冲Nd:YAG激光器选区晶化制备多晶硅薄膜

采用三倍频后的Nd:YAG固体脉冲激光系统(波长为355 nm)选区诱导晶化非晶硅薄膜,以制备多晶硅薄膜。分别测试了激光晶化前后薄膜的表面形貌和拉曼光谱。在文中分析了400 nm厚薄膜在激光扫描前后的表面形貌变化。拉曼光谱显示薄膜的晶化程度随着激光能量的增加而提高。最优的激光晶化能量密度与薄膜的厚度相关。对于300 nm和400 nm厚的非晶硅薄膜,有效晶化非晶硅的能量密度分别在440-634 mJ/cm²,777-993 mJ/cm²之间。在激光能量密度分别为634 mJ/cm²,975 mJ/cm²和1571 mJ/cm²时,300 nm、400 nm和500 nm厚薄膜达到最好的晶化效果。     

High-mobility CMOS transistors fabricated on very thin SOS films

It is reported that the mobility of CMOS transistors fabricated on very thin silicon-on-sapphire (SOS) films is a function of the film growth rate. Transistors with mobilities nearly as high as those obtained on 1.0-μm-thick films have been fabricated on SOS films 0.2 μm thick that have been grown at growth rates above 4 μm/min     

Pure germanium epitaxial growth on thin strained silicon-germanium graded layers on bulk silicon substrate for high-mobility channel metal-oxide-semiconductor field-effect transistors

We demonstrate epitaxially grown high-quality pure germanium (Ge) on bulk silicon (Si) substrates by ultra-high-vacuum chemical vapor deposition (UHVCVD) without involving growth of thick relaxed SiGe buffer layers. The Ge layer is grown on thin compressively strained SiGe layers with rapidly varying Ge mole fraction on Si substrates resulting in several SiGe interfaces between the Si substrate and the pure Ge layer at the surface. The presence of such interfaces between the Si substrate and the Ge layer results in blocking threading dislocation defects, leading to a defect-free pure Ge epitaxial layer on the top. Results from various material characterization techniques on these grown films are shown. In addition, capacitance-voltage (CV) measurements of metal-oxide-semiconductor (MOS) capacitors fabricated on this structure are also presented, showing that the grown structure is ideal for high-mobility metal-oxide-semiconductor field-effect transistor applications.     

Analysis of punch-through breakdown in bulk silicon RF power LDMOS transistors

The design and electrical performance of bulk silicon power LDMOS transistors for base station applications are analyzed in this paper. Power LDMOS transistors have been fabricated with a seven mask levels process technology including a LOCOS oxide in the drift region and a polysilicon field plate. Specific on-state resistances in the range of 3 mΩ × cm² have been experimentally measured on fabricated LDMOS transistors with a voltage capability of 80 V and a threshold voltage around 2.5 V. Moreover, the impact of the basic geometrical and technological parameters on the voltage capability and on the on-state resistance is also analyzed. Special emphasis has been made on the existence of a premature breakdown by a punch-through mechanism due to the combination of a low Boron dose in the body region and an excessive phosphorous dose in the drift region. Technological solutions for avoiding this undesired phenomenon are also discussed.     

Half-micrometre-base lateral bipolar transistors made in thin silicon-on-insulator films

NPN and PNP lateral bipolar transistors having a base length shorter than 0.5 ?m have been made in thin (100 nm) silicon-on-insulator films. Current gains of 75 and 40 have been obtained in NPN and PNP devices, respectively. Measurements indicate a base generation lifetime of 1 ?s, and leakage currents of a fraction of a picoampere have been measured. The device fabrication is compatible with an SOI CMOS fabrication process.     

Optoelectronic study in porous silicon thin films

A photoconductivity (PC) study in as deposited porous silicon (PS) thin films is presented in this work. PS thin films were produced by the electrochemical anodizing method at different anodizing times. The films surfaces were characterized by SEM and porosity was determined by gravimetric methods. Photoluminescence and PC measurements were taken at room temperature. The maximum of the photoluminescence spectra are located around 650 nm, whereas those of PC are placed around 400 nm. The maximum of the photoluminescence signal shifts toward short wavelengths as the quantum dimension of the material skeleton diminishes, while any spectral displacement of the photocurrent signal as the porosity of the material increases is not observed. The spectral position of the PC signal does not change because it is strongly affected by the large quantity of defects present in the sample surface which diminishes the mean free path of the carriers to reach the electrodes. In all the samples photocurrent is small around 10^?1 μA and the intensity of the signal goes down as the porosity increases. Two mechanisms exist that compete with one another, the carrier generation and recombination through light emission centers which diminish the photocurrent.     

A self-alignment process for amorphous silicon thin film transistors

A new method of fabricating amorphous Si thin film transistors (a-Si TFT's) has been developed. This method uses the self-alignment process, which also includes the successive deposition of gate insulator and active amorphous Si layers in one-pumpdown time in an RF glow discharge apparatus. This method greatly simplifies the fabrication process and results in stable device performance. The practicability of this method was confirmed by experimentally fabricated devices.     

Conductivity of thin nanocrystalline silicon films

It is shown in this paper that thin (200–250 Å) hydrogenated nanocrystalline silicon films have low longitudinal conductivity, comparable to that of undoped amorphous silicon, and high transverse conductivity. These films can be used as doping layers in barrier structures with low surface current leakage. It was found that film conductivity decreases by 8–10 orders of magnitude along the layer as the layer thickness is reduced from 1500 to 200 Å. The observed dependence of the conductivity on thickness can be explained (in terms of percolation theory) by destruction of a percolation cluster made up of nanocrystallites as the layer thickness is decreased.     

High-performance thin-film transistors in low-temperature crystallized LPCVD amorphous silicon films

Thin-film transistors (TFT's) were fabricated in low-temperature (550°C) crystallized amorphous LPCVD silicon films. The performance of these devices was found to depend upon the deposition temperature. Low threshold voltages and effective mobilities as high as 32 cm²/V.s are reported for devices fabricated in 150-nm-thick films with maximum processing temperature of 860°C. The performance of these devices is shown to be far superior to devices fabricated in as-deposited polycrystalline silicon films.     

Laser-recrystallized silicon thin-film transistors on expansion-matched 800°C glass

Laser-recrystallized silicon thin-film transistors (TFT's) have been fabricated, for the first time, on a novel, potentially low-cost glass substrate, The 0.5-µm-thick silicon films were deposited along with appropiate dielectric layers on Corning Code 1729 glass substrates and recrystallized using an argon ion laser. The n-channel enhancement-mode transistors were made using conventional IC device fabrication procedures modified to have a maximum processing temperature of 800°C. Transistor's made in the recrystallized silicon show field-effect electron mobilities as high as 270 cm²/V.s, approximately 15 times that of comparable devices made in as-deposited polycrystalline-silicon films. The recrystallized silicon devices also exhibit lower threshold voltages and lower leakage currents than do comparable polycrystalline-silicon devices.     

Planarization of amorphous silicon thin film transistors by liquidphase deposition of silicon dioxide

A planarized device structure was developed for amorphous silicon thin film transistors to overcome the gate leakage problem. Utilizing the liquid phase deposition technique, a silicon oxide film with thickness exactly equal to the gate height was grown around the gate to planarize the surface for the fabrication of inverted staggered thin film transistors. The planarized thin film transistor has smaller leakage current and better performance, i.e., field effect mobility, subthreshold swing, etc. This novel process has a potential to improve the yield of large area liquid crystal display     

Quantum size impacts on the threshold voltage in nanocrystalline silicon thin film transistors

Based on the analysis of Poisson equation, an analytical threshold voltage model including quantum size effect of nc-TFTs (nanocrystalline silicon thin film transistor) has been proposed in this paper. The results demonstrate that the proposed simplified expression of threshold voltage agree perfectly with numerical calculation. The threshold voltage in nc-TFTs strongly depends on the size of silicon grain when the size of silicon grain is less than 20 nm. Such a strong dependent relation results from the large changes in the bandgap and dielectric constant due to quantum size effects when the size of silicon grain is in the regime of nano-scale. The theoretical investigation also demonstrates that the grain boundary trap density compared to the active dopant density gives a main contribution to the threshold voltage. This implies that the grain size must be larger than 30 nm in order to avoid threshold voltage variation from different technological processes.     

Controlled nanorubbing of polythiophene thin films for field-effect transistors

We present results obtained by applying the nanorubbing process to improve the electrical performance of regioregular poly(3-hexylthiophene-2,5-diyl) (P3HT) thin films. Essentially, we use a scanning atomic force microscope tip to induce a controlled deformation on the surface consisting of parallel grooves with a period imposed by the scanning parameters. The optical characterization of the rubbed zones highlights an orientation of P3HT chains along the scanning direction. When the nanorubbing process is orienting the polymer chains within the channel of a field-effect transistor, we observe that the charge carrier mobility increases (decreases) when the tip scans parallel (perpendicular) to the source–drain axis. This difference likely stems from the polymer chains orientation induced by the alignment process.     

Hydrogenation of polycrystalline silicon thin film transistors byplasma ion implantation

Both n- and p-channel polycrystalline silicon (poly-Si) thin film transistors (TFT's) have been hydrogenated using the plasma ion implantation (PII) technique. Significant improvements in device characteristics have been obtained. Because PII is capable of greater dose rates than plasma immersion, it allows for significantly shorter process times than other methods investigated thus far