ESD issues in compound semiconductor high-frequency devices and circuits

The need of ESD protection for high frequency devices and circuits is underlined by reviewing the compound semiconductor material properties with emphasis on ESD stress and by collecting their ESD failure thresholds. Basic requirements for possible ESD protection structures in the microwave frequency regime are discussed and possible ESD protection devices and circuit concepts are proposed.     

High-resolution sampling SEM for quantitative investigations of semiconductor devices and integrated circuits

A scanning microscope has been interfaced with sampling circuitry to record high-speed voltage waveforms at internal points in devices. The system is capable of resolving rise times of 100 ps and voltage steps with an uncertainty of less than 10 mV. Results demonstrate the operation of the 4-GHz sampling SEM.     

半导体器件扫描电镜低电压成像技术应用

针对使用扫描电镜(SEM)进行半导体器件破坏性物理分析(DPA)和失效分析(FA)时,芯片表面不作喷镀处理的问题,提出了减小或消除电荷累积的试验方法。试验结果表明,正确应用SEM低电压技术,选择加速电压1.0 kV~2.0 kV、电子束斑2.0,结合积分技术,可在芯片表面不作喷镀处理,并满足国军标要求下,得到分辨率和性噪比均很好的图片。     

Dielectric materials, devices, and circuits

Dielectric materials are continuing to play a very important role in the microwave communication systems. These materials are key in realization of low-loss temperature-stable resonators and filters for satellite and broadcasting equipment, and in many other microwave devices. High dielectric-constant materials are critical to the miniaturization of wireless systems, both for the terminals and base-stations, as well as for handsets. In this paper, a sequential evolution of the dielectric materials applications in microwave devices will be reviewed. This includes dielectric waveguides, low-loss temperature-stable ceramic materials, dielectric resonators, and filters. The recent advances in the multilayer circuit modules, dielectric antennas, and ferroelectrics are also described     

Generation of self-sustained optical pulses from transients inexternal cavity, semiconductor lasers

A novel technique to achieve self-sustained picosecond optical pulse-train generation at Gbit/s rates is presented. The technique relies on the nature of external cavity laser-switching transients and injection-locking. Preliminary experimental results confirm the practicality of the proposed technique     

Theory of field enhanced non-equilibrium transients in MIS devices under a linear voltage sweep

A theoretical method has been formulated to simulate the field enhanced non-equilibrium transients in MIS devices under linear voltage sweep. Unlike previous theories the carrier emission probability is assumed to be field-dependent. The one dimensional Poole-Frenkel model and Hartke model are used to the carrier emission probability of traps dependent on the applied electric field. These models are quite available for coulombic centers. A reasonable model of the effective generation region is applied to analyse the transients, and the non-steady-state generation effect is taken into account. The I/V characteristics at different voltage sweep rates have been obtained. The effect of field enhanced carrier emission and the effect of non-steady-state generation on I/V characteristics are discussed in detail.     

An investigation on capacitance-trigger ESD protection devices for high voltage integrated circuits

A novel cascaded complementary dual-directional silicon controlled rectifier (CCDSCR) structure has been proposed and implemented in a 0.5 μm 20 V Bipolar/CMOS/DMOS process as an ESD (electrostatic discharge) protection device. The ESD characteristics of the capacitance-trigger CCDSCR has been investigated by transmission line pulse (TLP) testing. Compared with the substrate-trigger insulated gate bipolar transistor with the enhanced substrate parasitic capacitance, the gate-driven trigger insulated gate bipolar transistor with the gate coupling capacitance and the normal dual-directional silicon controlled rectifier, the CCDSCR has the highest holding voltage of about 25.4 V and the best current conduction uniformity. In addition, it has the best figure of merit (FOM) with the value of about 0.64 mA/μm². The good current conduction uniformity in CCDSCR due to the enhanced substrate parasitic capacitance-trigger effect is finally confirmed by Sentaurus simulations.     

Superconductor-semiconductor hybrid devices, circuits, and systems

The discovery of superconductors whose critical temperatures are above liquid nitrogen temperature has prompted considerable interest in hybrid superconducting-semiconducting electronics applications. The authors review the efforts to hybridize these technologies. Some of these efforts have already been demonstrated on a laboratory scale; others are at present just theoretical proposals. Hybridization is possible on the system, circuit, and device levels. The authors review studies of the applications of superconductors for interconnecting semiconductor systems and combining semiconductor and superconductor devices to enhance the performance of both digital and analog systems. Novel circuit combinations of superconducting and semiconducting devices are mentioned, as are proposals to combine these materials on the device level. It is noted that the use of hybrid combinations may permit some electronic functions to be performed better than either technology could perform separately     

Josephson-logic devices and circuits

A review of the recent advances in Josephson logic devices and circuits is presented. The Josephson junction is almost an ideal digital switch exhibiting very abrupt threshold, ultra-high switching speeds (∼10 ps), and very low power dissipation (∼1 µW). Logic devices based on the Josephson junctions combine Josephson junctions with other circuit elements to provide isolation to the input signals as well as to provide higher gain than a single junction. These devices can be classified into two groups, the first group uses magnetically coupled SQUID's (Superconducting QUantum Interference Devices) to provide isolation, whereas the second group of circuits utilizes the high-resistance state of a Josephson junction in series with the signal input to provide isolation. Logic circuits based on these two isolation Schemes are compared. In both schemes, higher gains are achieved by the use of either multiple Josephson junctions in parallel or a buffer stage. The buffer stage is a Current-Injection Device (CID) which provides gain and the AND function between the two signal currents injected into it. Some of the unique features of Josephson logic circuits such as terminated superconducting transmission lines, ac power supply, Timed Inverter, and Latch circuits are also examined. The dynamic behavior of the Josephson junctions is modeled by very simple equivalent circuits. The computer simulations based on these models are compared with experiments and found to be in excellent agreement. A family of experimental logic circuits has been designed and experimentally tested using 2.5-µm minimum feature size. These circuits have fully loaded logic delays of about 40 ps/gate and power dissipation of about 4 µW/gate. The gate delays and power-delay products are compared with leading semiconductor technologies.     

Direct determination of doping concentration and built-in voltage from extraction current transients

We have extended the analytical framework of the charge extraction by linearly increasing voltage (CELIV) theory to the case with doping, taking the effect of built-in voltage, diffusion and band-bending into account. Not taking the built-in voltage into account in dark CELIV will lead to an underestimation of the charge carrier density, while the mobility is overestimated. Furthermore, based on the analysis we propose to use CELIV in the doping-induced capacitive regime for direct determination of doping concentration and built-in voltage from extraction current transients in the time-domain of doped thin-film semiconductor devices. The analytical framework is confirmed numerically with a one-dimensional drift–diffusion model and experimentally on aged P3HT:PCBM bulk heterojunction solar cell devices. An excellent agreement between the experimental extraction current transients and the analytical prediction is found. The presented analytical treatment is not limited to sandwich-type thin-film devices, but is more general and the technique can also be extended to pn-junctions.     

毫米波器件与电路技术

阐述了近来毫米波器件及电路的技术动向。异质结FET和HBT在InP系突现出优越的性能,在GaAs系已完全进入系统应用阶段。在此应用观点的影响下,相继开发成功了宽带无线通信系统和车载雷达用的CPWMMIC芯片以及倒装片封装模块。     

Concentration profiles of recombination centers in semiconductor junctions evaluated from capacitance transients

The effect of stationary charges trapped in the region near the p-n boundary and in the edge region of a semiconductor junction space-charge layer on the evaluation of the concentration profiles of the recombination centers as well as doping impurities, from high-frequency capacitance transient data, is studied. Both the theory, its simplification for junctions with low concentration of recombination centers, and two experimental examples are given to illustrate the importance of the edge effect. One of the examples is an aluminum on n-Si Schottky diode with a very low concentration of process-induced donor trap, and the other is a phosphorus and gold diffused diode with a gold concentration about 20 percent of the boron concentration.     

Experimental studies of the adequacy of laser simulations of dose rate effects in integrated circuits and semiconductor devices

Comparative experimental studies of the responses of typical representatives of integrated circuits (ICs) and semiconductor devices (SDs) with various designs to high-energy pulsed ionizing radiations from simulation facilities and laser simulators have been carried out. The differences between the hardness values under exposure to radiations from simulation facilities and laser simulators have been found to be no larger than the dosimetry errors when the power supply ionization current calibration procedure is used. The shapes of power supply ionization currents and output voltages in the ICs are almost identical qualitatively. The levels and patterns of the functional IC failures are completely identical for both types of radiation sources. As a result, we have proven that a joint application of simulation facilities and laser simulators provides a rational combination of the reliability and efficiency of testing ICs and SDs for hardness to dose rate.     

Molecular electronics: from devices and interconnect to circuits and architecture

As the dominating CMOS technology is fast approaching a "brick wall," new opportunities arise for competing solutions. Nanoelectronics has achieved several breakthroughs lately and promises to overcome many of the limitations intrinsic to current semiconductor approaches. Most of the results in this area reported until now focus on devices and interconnect; this work goes several steps further and presents issues related to circuits and architecture. Based on proposed nanoscale interconnect and device structures, we explore the design space available to the nanoelectronic circuit designer and system architect.     

Theoretical performance of voltage multiplier circuits

An expression for the equivalent source resistance of the capacitor diode voltage multiplier circuit is derived. The source resistance is found to increase as the cube of the multiplication factor, explaining the poor regulation observed with large multiplication. The distribution of capacitors that minimizes source resistance is presented. Good regulation is shown to be necessary for high efficiency, and to require relatively larger capacitors than needed for ripple filtering.     

Transient simulation of silicon devices and circuits

In this paper, we present an overview of the physical principles and numerical methods used to solve the coupled system of non-linear partial differential equations that model the transient behavior of silicon VLSI device structures. We also describe how the same techniques are applicable to circuit simulation. A composite linear multistep formula is introduced as the time-integration scheme. Newton-iterative methods are exploited to solve the nonlinear equations that arise at each time step. We also present a simple data structure for nonsymmetric matrices with symmetric nonzero structures that facilitates iterative or direct methods with substantial efficiency gains over other storage schemes. Several computational examples, including a CMOS latchup problem, are presented and discussed.     

A survey of semiconductor devices

This paper attempts to present a complete collection of semiconductor devices. A total of 67 “major” devices have been identified, together with about 110 device variations which are considered to be “related” devices to the former. These devices are organized into groups and subgroups for a better overview, and the justification for such classification is discussed. After the list is presented, the author offers some comments and observations from his viewpoint