正辛胺模板法制备Si／Al复合空心微球及其结构表征

以正辛胺为模板、正硅酸乙酯(TEOS)为硅源、异丙醇铝为铝源,在盐酸的催化作用下通过溶胶一凝胶方法制备出圆形度和分散性好、结构完整的Si/Al复合空心微球.分析了不同反应时间和反应温度下Si/Al复合空心微球的形貌、粒径、成分和结构.结果表明:Si/Al复合空心微球的平均粒径随反应温度和反应时间的增加而缓慢增大,但明显小于同样条件SiO2空心微球的粒径.Si/Al复合空心微球的平均粒径为8～16μm,壳层厚度为2.18～3.61μm.Si/Al复合空心微球中的铝主要以氧化物的形式存在;壳层表面具有微孔结构,比表面积为431～912 m2/g;可几孔径为1.2～2.0nm.     

Notching效应在MEMS单步干法制造工艺中的应用

研究了一种基于深反应离子刻蚀（DRIE）中notching效应的MEMS单步干法制造工艺.首先,基于DRIE刻蚀SOI硅片时notching现象产生的机理,设计了多种不同线宽的槽结构,验证notching效应的发生条件.实验结果表明,对于所采用的具有30μm器件层的SOI硅片,发生notching现象的临界槽宽为12μm,而notching释放的极限结构宽度同样为12μm.其次,为实现大面积结构的notching释放,研究了正方形、矩形、三角形及六边形等4种典型释放孔结构的干法释放效果.实验结果表明,六边形释放孔不但能够快速有效地释放结构,同时还能降低notch-ing效应的磨损,有利于惯性MEMS器件的加工.最后,设计了一种Z轴微机械陀螺结构以验证提出的设计及工艺.加工及测试结果表明,所提出的单步干法制造工艺完全满足微机械陀螺设计加工要求,工艺简单、成品率高,所测试的陀螺在常压下即可达到122的品质因数.     

采用真空镀膜制备的叠层结构有机场效应晶体管的研究

本文报道了一种叠层结构有机场效应管,它有别于一般的顶接触式和底接触式结构OFET.该器件采用真空镀膜制备,以SiO2作为绝缘层,酞菁铜CuPc作为沟道层.测量出其输出特性曲线,可看见较明显的场效应特性.对器件温度特性的研究表明,漏极电流随着温度的升高而增大.XRD分析表明,在Si/SiO2和Si/SiO2/Al两种衬底上蒸镀制备的CuPc薄膜呈多晶结构,且两种衬底上的CuPc薄膜晶粒尺度大致相等.     

基于中间硅片厚度可控的三层阳极键合技术

三层键合Glass-Silicon-Glass(GSG)结构在光MEMS、微惯性器件、微流体芯片、射频MEMS以及低成本圆片级封装技术领域里是一项重要技术.基于MEMS精密研磨抛光工艺和阳极键合,结合新型玻璃通孔的腐蚀工艺,开展了中间硅片厚度可控的三层阳极键合工艺研究,成功制备了带有通孔的GSG微流体器件.总厚度1360μm,中间硅片厚度60μm,通孔直径100μm,孔间距(圆孔的中心距离)200μm,孔内边缘圆滑无侧蚀.三层结构的键合几率为90%,为探索多层键合技术打下坚实基础.     

基于PZT薄膜面内极化工作的低应力压电微传声器

本文设计、制作并测试了一种基于压电PZT薄膜面内极化工作的压电微传声器.利用压电薄膜的纵向压电常数,并通过压电微传声器面内电极的设计提高电极间距,以提高压电微传声器的灵敏度.由于基于PZT薄膜的多层结构常具有很大的残余应力,通过5种不同振动膜材料与PZT薄膜的应力匹配实验,研究了降低振动膜应力的方法.结果表明,对于相同尺寸的膜片,PZT/ZrO2/LTO/Si3N4具有最小的变形,其中心处的变形(200 nm)仅为膜片PZT/ZrO2/Si3N4/SiO2中心处变形(17μm)的1%.采用体硅微加工工艺制作了具有方形振动膜(2 mm×2 mm)的压电微传声器结构,采用LTO/Si3N4多层结构作为振动膜结构,方形膜片中心的圆形结构为PZT薄膜,环形叉指结构为Au/Cr电极.压电微传声器在0.15 kHz~6 kHz频率范围内的灵敏度约为0.1 mV/Pa.     

Lu-Si-O体系在高温水蒸气环境中的腐蚀行为

采用溶胶-凝胶法制得三种镥硅酸盐体系粉体材料.以氧化物的摩尔比来表示此三种粉体,分别为:Lu2O3.SiO2、Lu2O3.2SiO2和Lu2O3.2.26SiO2.在1400℃、50%H2O-50%O2静态常压气氛下,研究了它们的耐水蒸气腐蚀性能.以单位面积重量变化率表征材料的耐水蒸气腐蚀性能,结合X射线衍射(XRD)、傅里叶红外光谱(FTIR)和扫描电镜能谱分析(SEM-EDS)等分析手段,揭示了镥硅酸盐体系在高温水蒸气环境中的腐蚀机制和反应机理.结果表明:三种原始粉体主要物相依次为:Lu2SiO5+Lu2Si2O7、Lu2Si2O7+SiO2和Lu2Si2O7+SiO2.在水蒸气作用下,Lu2SiO5相与Al2O3反应生成新相Lu3Al5O12,而Lu2Si2O7相并未受到水蒸气的作用而发生任何反应,表现出优异的化学稳定性.     

用于微机电系统的SiO2/Si3N4驻极体的制备及电荷稳定性

驻极体微型发电机是近期提出的微电子机械系统开发中的一个新领域,驻极体电荷稳定性则是影响驻极体微型发电机性能的关键.用等离子体增强化学气相沉积(PECVD)方法制备SiO2/ Si3N4双层膜,采用电晕充电和热极化方法对材料进行注极形成驻极体,探讨了器件加工工艺及存储环境对双层膜驻极体电荷稳定性的影响.结果表明,电晕充电后SiO2/ Si3N4双层膜的电荷存储稳定性明显优于SiO2单层膜;传统的电晕注极方法仅适用于大面积驻极体的制备,但对微米量级的材料表面不适用;微器件制备的工艺流程对驻极体电荷稳定性有显著影响,但存储环境对热极化驻极体电荷稳定性的影响很小.     

日本开发8英寸SiC单晶制造技术

日本Air Warer公司和大阪府立大学共同开发了8英寸大直径SiC单晶的制造技术，这在世界尚属首次。该技术是用化学气相沉积法(CVD)在SOI基板上生长SiC晶体层。制造工艺如下：①在Si基板中嵌入SiO2氧化层(形成SOI基板)；②使表面Si层减至极薄；③生成SiC种层；④进行SiC单晶层的外延生长。生长SiC单晶层使用的是该公司自制的高真空外延生长装置“VCE”。     

用于微等离子体无掩膜刻蚀的微悬臂梁探针的设计和加工

设计了一种用于微等离子体无掩膜刻蚀加工的微悬臂梁探针结构,即将微等离子体放电器集成在SiO2悬臂梁探针端部的空心针尖上,等离子体从针尖处的纳米孔导出,以实现高精度、高效率的无掩膜扫描刻蚀加工.设计了该悬臂梁探针的加工工艺流程,即对(100)硅片进行各向异性湿法刻蚀得到倒金字塔槽,并双面氧化,然后依次沉积并图形化微放电器的上、下电极和绝缘层,最后背面释放出带空心针尖的SiO2悬臂梁,并加工出针尖尖端的纳米孔.成功制作出质量良好、具有很高成品率的带薄壁空心针尖的SiO2悬臂梁探针阵列及倒金字塔型微放电器.实验结果表明,该微放电器能在3～15 kPa的SF6气体中稳定放电,为悬臂梁探针阵列和微放电器的工艺集成以及Si基材料的无掩膜扫描刻蚀加工奠定基础.     

基于线算法的ICP深反应离子刻蚀模型

电感耦合等离子体(ICP)刻蚀是目前集成电路与微机电系统制造的关键工艺之一.利用一种改进的复合交替深刻蚀(TMDE)模型对ICP深反应离子刻蚀(Deep-RIE)进行了工艺仿真建模.根据深反应离子刻蚀中Footing效应的实验特征,提出了针对这一现象的表面描述方程,并借助实验手段确定了该表面描述方程中的参数,从而为模型添加了一种简单有效的Footing效应模拟模块.最后对Deep-RIE和Footing效应刻蚀表面进行模拟,验证了模型的有效性和可用性.     

SOI材料的缺陷及其表征

简述了利用注氧隔离法(SIMOX)制备的SOI材料中产生的一些不同于体硅材料的特殊缺陷,涉及表面缺陷、Si/SiO2界面缺陷和埋氧层缺陷,包括这些缺陷的产生机制、表征方法以及一些降低和消除措施.     

基于SCR的SOI ESD保护器件研究

本文具体分析了体硅SCR(晶闸管)和SOI SCR的抗静电特性,利用软件Sentaurus对埋氧层3μm,顶层硅1.5μm的SOI衬底上的SCR进行了工艺和性能仿真,仿真结果达到了4.5kV的抗静电能力,符合目前人体模型的标准2KV.研究发现,注入剂量(9*13 -8*14cm-2)增加会引起触发电压减小,维持电压升高...     

Fabrication and Characterization of Silicon (100) Membranes for a Multi-beam Superconducting Heterodyne Receiver

We fabricated silicon (100) membranes of 3 mm in diameter on the surface of silicon-on-insulator (SOI) substrates and investigated the characteristics of the membranes. The handle layer of one SOI substrate was etched using deep reactive ion etching process with the buried oxide (BOX) layer that remained together with the device layer. The BOX layer of the other SOI substrate was removed using C₄F₈-based plasma etching after the handle layer etching. The surfaces of both silicon (100) membranes were observed using the scanning white light interferometer system at room temperature. Both silicon (100) membranes have dome-like deformations. The silicon (100) membranes are effectively flattened by etching the BOX layer under the device layer. Both silicon (100) membranes were cooled from room temperature to 4 K by a Gifford–McMahon refrigerator. Wrinkles appeared on the surfaces of both silicon (100) membranes when the temperature dropped to about 200 K. However, the wrinkles disappeared below about 180 K. This phenomenon indicates the wrinkles at low temperature would depend on the properties of the silicon (100) of the device layers and independent of the properties of the BOX layers under the silicon (100) membranes.     

Study of chip strength due to backside grinding on wafer

Abstract

The strength distribution of semiconductor chips on a wafer was studied for this paper using the three‐point bending test method that complies with ASTM standard E855. It was found from thousands of testing results that a weak region in a wafer always exists when the wafer has been thinned by mechanical backside grinding method. This weak region was distributed in two sectorial regions 45 degrees wide and symmetric to the wafer center. The averaged chip strength in the weak region was found to be at least 30% lower than the averaged chip strength of the whole wafer, and was independent of chip aspect ratio, metallization, diameter of the wafer, and the equipment that the backside grinding process used. The existence of the weak region was due to the grinding mark produced by the equipment, and was physically explained by the experimental results in this study. This weak region was able to be eliminated by using either plasma etching or polishing after the mechanical backside grinding.     

Single electron transistor fabricated with SOI wafer

The single electron transistor (SET) is the most sensitive device for measuring the charge of electron. It has been proposed by Kane that the SET can be used for readout of calculated results in Si-based quantum computer. We fabricated the SET with SOI substrate utilizing the suspended mask of SiO₂ and Si for the purpose of using it for readout of calculation in Si-Based quantum computer. By using only the above materials for the mask, high temperature processes including ion implantation and activation annealing could be possible and it was never achieved in conventional methods with the suspended mask with photoresist. First, the suspended mask with enough undercut in SOI was made by removing the box oxide of SOI wafer combining with pattern delineation by electron beam lithography, anisotropically reactive ion etching and isotropic wet etching. After forming the suspended mask, Al films were evaporated from two different angles to make an overlap just below the bridge, resulting in completing the SET in the undercut region possible to measure the electron spin. After making the Al/Al₂O₃/Al SET, we measured the I–V characteristic between source and drain at 1.8 K. The Coulomb blockade and the Coulomb oscillation were observed.     

制备AlN薄膜为绝缘埋层的新型SOI材料

采用离子束增强技术（IBED）在Φ100mm硅片上合成了AlN薄膜。以速率0.05nm/s蒸发高线Al得到AlN样品，XPS结果证实了成功合成了AlN薄膜，其N／Al比为0.618：1，扩展电阻结果表明其绝缘性能良好，原子力显微镜（AFM）显示其表面平整光滑，均方根粗糙度（RMS）为0.13nm，满足键合需要。利用智能剥离技术（Smart-cut process)成功地制备了以AlN薄膜为埋层的SOI（silicon-on-insulator)材料。剖面透射电镜照片（XTEM）给出了此SOI结构，高分辨TEM实验结果表明上层硅具有与衬底硅相似的结晶质量可满足器件制造的要求。     

Fabrication of thin-film thermopile micro-bridge with XeF2 etching process

These days, MEMS-based thin-film thermopiles are mainly fabricated anisotropically by wet-etching process at the back of the wafer. Their backside etching process is, however, complex, expensive, and wastes a large amount of silicon real estate. On the other hand, the front-side etching has better reliability of photolithography and also makes it possible to fabricate smaller micro-thermopile, as compared to that obtained from backside etching. In this paper, a thin-film thermopile is fabricated on a micro-bridge structure created by using the front-side etching with XeF₂ gas. The resulting device is about 50% smaller in size than that of the conventional chip. The output voltage of the device is found to increase by 2.13 times and the Seebeck coefficient to enhance by 0.17 μV/°C, due to less heat-flow from hot junction to cold junction and the increase in aluminum etching hole area.     

Improvement in thickness uniformity of thick SOI by numerically controlled local wet etching

Silicon-on-insulator (SOI) wafers are promising semiconductor materials for high-speed LSIs, low-power-consumption electric devices and micro electro mechanical systems (MEMS). The thickness distribution of an SOI causes the variation of threshold voltage in electronic devices manufactured on the SOI wafer. The thickness distribution of a thin SOI, which is manufactured by applying a smart cut technique, is comparatively uniform. On the other hand, a thick SOI has a large thickness distribution because a bonded wafer is thinned by conventional grinding and polishing. For a thick SOI wafer with a thickness of 1 microm, it is required that the tolerance of thickness variation is less than 50 nm. However, improving the thickness uniformity of a thick SOI layer to a tolerance of +/- 5% is difficult by conventional machining because of the fundamental limitations of these techniques. We have developed numerically controlled local wet etching (NC-LWE) technique as a novel deterministic subaperture figuring and finishing technique, which utilizes a localized chemical reaction between the etchant and the surface of the workpiece. We demonstrated an improvement in the thickness distribution of a thick SOI by NC-LWE using an HF/HNO3 mixture, and thickness variation improved from 480 nm to 200 nm within a diameter of 170 mm.     

Fabrication of 380 nm ultra violet light emitting diodes on nano-patterned n-type GaN substrate

380 nm ultraviolet (UV) light emitting diodes (LEDs) were grown on patterned n-type GaN substrate (PNS) with silicon dioxide (SiO2) nano pattern to improve the light output efficiency. Wet etched self assembled indium tin oxide (ITO) nano clusters serves as dry etching mask for converting the SiO2 layer grown on n-GaN template into SiO2 nano patterns by inductively coupled plasma etching. Three different diameter of ITO such as 200, 250 and 300 nm were used for SiO2 nano pattern fabrication. PNS is obtained by n-GaN regrowth on SiO2 nano patterns and UV LEDs were grown on PNS template by MOCVD. Enhanced light output intensity was observed by employing SiO2 nano patterns on n-GaN. Among different PNS UV LEDs, LED grown on PNS with 300 nm ITO diameter showed enhancement in light output intensity by 2.1 times compared to the reference LED without PNS.