A 0.13μm CMOS Δ ∑ fractional-N frequency synthesizer for WLAN transceivers

A fractional-N frequency synthesizer fabricated in a 0.13μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network(WLAN) transceivers.A monolithic LC voltage controlled oscillator(VCO) is implemented with an on-chip symmetric inductor.The fractional-TV frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping(MASH)△Σmodulator with noise-shaped dithering techniques.Measurement results show that in all channels,phase noise of the synthesizer achieves -93 dBc/Hz and -118 dBc/Hz in band and out of band respectively with a phase-frequency detector (PFD) frequency of 20 MHz and a loop bandwidth of 100 kHz.The integrated RMS phase error is no more than 0.8°.The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm~2.     

A 0.13μm CMOS △∑ fractional-N frequency synthesizer for WLAN transceivers

A fractional-N frequency synthesizer fabricated in a 0.13 μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network (WLAN) transceivers.A monolithic LC voltage controlled oscillator (VCO) is implemented with an on-chip symmetric inductor.The fractional-N frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping (MASH) △ ∑ modulator with noise-shaped dithering techniques.Measurement results show that in all channels,phase noise of the synthesizer achieves -93 dBc/Hz and -118 dBc/Hz in band and out of band respectively with a phase-frequency detector (PFD) frequency of 20 MHz and a loop bandwidth of 100 kHz.The integrated RMS phase error is no more than 0.8°.The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm2.     

Design of a dual-channel multi-mode GNSS receiver with a∑△fractional-N synthesizer

A 72 mW highly integrated dual-channel multimode GNSS(global navigation satellite system) receiver with aΣ△fractional-N synthesizer which covers GPS L1 and the Compass B1/B2/B3 band is presented.This chip was fabricated in a TSMC CMOS 0.18μm process and packaged in a 48-pin 3×3 mm~2 land grid array chip scale package.This work achieves NF≤5.3 dB without an external LNA,channel gain = 105 dB for channel one (Compass B2 and B3 band),and channel gain = 110 dB for channel two(GPS L1 and Compass B1 band).Image rejection(IMRR) = 36 dB,phase noise is -115.9 dBc @ 1 MHz and -108.9 dBc @ 1 MHz offset from the carrier for the two channels separately.At the low power consumption,multibands of GNSS are compatible in one chip, which is easy for consumers to use,when two different navigation signals are received simultaneously.     

A △∑ fractional-N frequency synthesizer for FM tuner using low noise filter and quantization noise suppression technique

A △∑ fractional-N frequency synthesizer fabricated in a 130 nm CMOS technology is presented for the application of an FM tuner. A low noise filter, occupying a small die area and decreasing the output noise, is integrated on a chip. A quantization noise suppression technique, using a reduced step size of the frequency divider, is also adopted. The proposed synthesizer needs no off-chip components and occupies an area of 0.7 mm2. The in-band phase noise （from 10 to 100 kHz） below -108 dBc/Hz and out-of-band phase noise of -122.9 dBc/Hz （at 1 MHz offset） are measured with a loop bandwidth of 200 kHz. The quantization noise suppression technique reduces the in-band and out-of band phase noise by 15 dB and 7 dB respectively. The integrated RMS phase error is no more than 0.48°. The proposed synthesizer consumes a total power of 7.4 mW and the frequency resolution is less than 1 Hz.     

A 0.18μm CMOS Gilbert low noise mixer with noise cancellation

正This paper presents a broadband Gilbert low noise mixer implemented with noise cancellation technique operating between 10 MHz and 0.9 GHz.The Gilbert mixer is known for its perfect port isolation and bad noise performance.The noise cancellation technique of LNA can be applied here to have a better NF.The chip is implemented in SMIC 0.18μm CMOS technology.Measurement shows that the proposed low noise mixer has a 13.7-19.5 dB voltage gain from 10 MHz to 0.9 GHz,an average noise figure of 5 dB and a minimum value of 4.3 dB.The core area is 0.6 x 0.45 mm~2.     

A 900 MHz fractional-N synthesizer for UHF transceiver in 0.18μm CMOS technology

A 900 MHz fractional-N synthesizer is designed for the UHF transceiver. The VCO with a 4 bits capacitor bank covers 823–1061 MHz that implements 16(24)sub-bands. A 7/8 dual-modulus prescaler is implemented with a phase-switching circuit and high-speed flip–flops, which are composed of source coupled logic. The proposed synthesizer phase-locked loop is demonstrated with a 50 k Hz band width by a low 12.95 MHz reference clock, and offers a better phase noise and band width tradeoff. To reduce the out-band phase noise, a 4-levels 3-order single-loop sigma–delta modulator is applied. When its relative frequency resolution is settled to 10-6, the testing results show that the phase noises are –120.6 d Bc/Hz at 1 MHz and –95.0 d Bc/Hz at 100 k Hz. The chip is2.1 mm2 in UMC 0.18μm CMOS. The power is 36 m W at a 1.8 V supply.     

A very low noise preamplifier for extremely low frequency magnetic antenna Feng Shimin(冯士民), Zhou Suihua(周穗华), and Chen Zhiyi(陈志毅)

Besides the electrode-pair antenna,the magnetic antenna is also used for the extremely low frequency （ELF） submarine communication.To receive the weak ELF signals,the structure of a small sized magnetic antenna determines its specific electrical characteristics.The ELF magnetic antenna shows high internal resistance, alternating-current impedance,and a resonance frequency near the operating bandwidth.In accordance with the electrical characteristics of ELF magnetic antenna,a low noise preamplifier and frequency compensation circuit were designed and realized.The preamplifier is a three-stage negative feedback circuit,which is composed of parallel JFET,common-emitter amplifier with a Darlington structure and a common-collector amplifier in push-pull connection.And a frequency compensation circuit is cascaded to compensate the characteristic in low frequency range.In the operating bandwidth f = 30-200 Hz,the circuit has a gain of 39.4 dB.The equivalent input noise is 1.97 nV/Hz^1/2 and the frequency response keeps flat in operating bandwidth.The proposed preamplifier of the ELF magnetic antenna performs well in receiving ELF signals.     

A fractional-N frequency divider for multi-standard wireless transceiver fabricated in 0.18 μm CMOS process

With the rapid evolution of wireless communication technology,integrating various communication modes in a mobile terminal has become the popular trend.Because of this,multi-standard wireless technology is one of the hot spots in current research.This paper presents a wideband fractional-N frequency divider of the multi-standard wireless transceiver for many applications.High-speed divider-by-2 with traditional sourcecoupled-logic is designed for very wide band usage.Phase switching technique and a chain of divider-by-2/3 are applied to the programmable frequency divider with 0.5 step.The phase noise of the whole frequency synthesizer will be decreased by the narrower step of programmable frequency divider.△-Σ modulator is achieved by an improved MASH 1-1-1 structure.This structure has excellent performance in many ways,such as noise,spur and input dynamic range.Fabricated in TSMC 0.18 μm CMOS process,the fractional-N frequency divider occupies a chip area of 1130 × 510μm2 and it can correctly divide within the frequency range of 0.8-9 GHz.With 1.8 V supply voltage,its division ratio ranges from 62.5 to 254 and the total current consumption is 29 mA.     

一种应用于无线局域网收发机集成低噪声滤波器的55nm CMOS ΔΣ分数型频率综合器

本文提出一种应用于IEEE 802.11b/g 无线局域网收发机的全集成ΔΣ 分数型频率综合器,该设计采用了55nm CMOS 工艺。该设计集成了一种占据很小芯片面积的低噪声滤波器,并使用一种高电源抑制比和低噪声的稳压源为其供电。该频率合成器不需要使用片外元器件,不包含焊盘占用0.72 mm2的面积。测试结果表明,参考频率为40 MHz,环路带宽为200 kHz的情况下,该设计所有信道的相位噪声性能均可达到带内-99dBc/Hz,带外-119 dBc/Hz,积分均方相位误差小于0.6°。整个设计消耗15.6 mW的功耗。     

A 0.18μm CMOS low noise amplifier using a current reuse technique for 3.1-10.6 GHz UWB receivers

A new,low complexity,ultra-wideband 3.1-10.6 GHz low noise amplifier(LNA),designed in a chartered 0.18μm RFCMOS technology,is presented.The ultra-wideband LNA consists of only two simple amplifiers with an inter-stage inductor connected.The first stage utilizing a resistive current reuse and dual inductive degeneration technique is used to attain a wideband input matching and low noise figure.A common source amplifier with an inductive peaking technique as the second stage achieves high flat gain and wide -3 dB bandwidth of the overall amplifier simultaneously.The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB,and a high reverse isolation of—45 dB,and good input/output return losses are better than -10 dB in the frequency range of 3.1-10.6 GHz.An excellent noise figure(NF) of 2.8-4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V.An input-referred third-order intercept point(IIP3) is -7.1 dBm at 6 GHz.The chip area,including testing pads,is only 0.8×0.9 mm2.     

A Class-C VCO Based Σ-Δ Fraction-N Frequency Synthesizer with AFC for 802.11ah Applications

A 1.4-2 GHz phase-locked loop (PLL) Σ-Δ fraction-N frequency synthesizer with automatic frequency control (AFC) for 802.11ah applications is presented. A class-C voltage control oscillator (VCO) ranging from 1.4 to 2 GHz is integrated on-chip to save power for the sub-GHz band. A novel AFC algorithm is introduced to maintain the VCO oscillation at the start-up and automatically search for the appropriate control word of the switched-capacitor array to extend the PLL tuning range. A 20-bit third-order Σ-Δ modulator is utilized to reduce the fraction spurs while achieving a frequency resolution that is lower than 30 Hz. The measurement results show that the frequency synthesizer has achieved a phase noise of < -120 dBc/Hz at 1 MHz offset and consumes 11.1 mW from a 1.7 V supply. Moreover, compared with the traditional class-A counterparts, the phase noise in class-C mode has been improved by 5 dB under the same power consumption.     

A wide-band low phase noise LC-tuned VCO with constant K_(VCO)/ω_(osc) for LTE PLL

正A wideband LC-tuned voltage-controlled oscillator(LC-VCO) applied in LTE PLL frequency synthesizers with constant AVco/ω_(osc) is described.In order to minimize the loop bandwidth variations of PLL,a varactor array is proposed,which consists of a series of differential variable capacitor pairs and a series of single-pole double-throw(SPDT) switches to connect V_(tune) or V_(dd).The switches are controlled by switching bits.With this scheme,the ratio of K_V =(?)C_(var)/(?)V_(tune) and the capacitance value of the capacitor array maintains relatively constant; furthermore,the loop bandwidth of the PLL fluctuation is suppressed.The 3.2—4.6-GHz VCO for multi-band LTE PLL is fabricated in a 0.13-μm RF-CMOS process.The VCO exhibits a maximum variation of A_(VCO)/ω_(osc) of only±4%.The VCO also exhibits a low phase-noise of-124 dBc/Hz at a 1-MHz offset frequency and a low current consumption of 18.0 mA with a 1.2-V power supply.