5-GHz Oscillator Array With Reduced Flicker Up-Conversion in 0.13-$muhboxm$CMOS

Voltage supply scaling in CMOS processes requires lower inductance and higher capacitance in conventional LC oscillators. Forcing several LC oscillators to run in phase is a valuable means of achieving the wanted phase noise with practical values of inductances and capacitances. However, in-phase oscillator arrays suffer from the up-conversion of transistors' flicker noise, in the presence of oscillator mismatches. A multitank oscillator topology is proposed, which has superior tolerance to mismatches and removes this mechanism of noise degradation. In order to assess such topology, an 802.11 a-compliant VCO with four coupled oscillators has been designed in a 0.13-mum CMOS technology. A phase noise better than -120 dBc/Hz at 1-MHz offset has been achieved along the 4.7-5.9-GHz tuning range     

Phase Noise and Jitter in CMOS Ring Oscillators

A simple, physically based analysis illustrate the noise processes in CMOS inverter-based and differential ring oscillators. A time-domain jitter calculation method is used to analyze the effects of white noise, while random VCO modulation most straightforwardly accounts for flicker ($1/f$) noise. Analysis shows that in differential ring oscillators, white noise in the differential pairs dominates the jitter and phase noise, whereas the phase noise due to flicker noise arises mainly from the tail current control circuit. This is validated by simulation and measurement. Straightforward expressions for period jitter and phase noise enable manual design of a ring oscillator to specifications, and guide the choice between ring and LC oscillator.     

采用CMOS工艺中寄生V-NPN改进低频相位噪声的压控振荡器

本文将CMOS工艺中的寄生垂直NPN管(V-NPN)用于压控振荡器的交叉耦合单元来改善其低频偏处的相位噪声. 相对于MOS晶体管, V-NPN管拥有更低的闪烁噪声. 为了便于后续的电路设计, 本文对V-NPN管的直流和交流特性进行了测试. 提出的V-NPN VCO最终在SMIC 0.18-μm CMOS 射频/混合信号工艺上流片验证. 测试结果显示, 相比于一个类似的用MOS管充当交叉耦合管的VCO, 提出的V-NPN VCO在100Hz到10KHz频偏内的相位噪声改善了3.5~9.1dB. 在1.5V的电源电压下, 其消耗的电流仅为0.41mA.     

RF CMOS low-phase-noise LC oscillator through memory reduction tail transistor

Based on the understanding of flicker noise generation in "silicon metal-oxide semiconductor field-effect transistors" (MOSFETs), a novel method for improving the phase noise performance of a CMOS LC oscillator is presented. Zhou et al. and Hoogee have suggested that the 1/f noise can be reduced through a switched gate, and the flicker noise generated is inversely proportional to the gate switching frequency. The novel tail transistor topology is compared to the two popular tail transistor topologies, namely, the fixed biasing tail transistor and without tail transistor. Through this technique, a figure of merit of 193 dB is achieved using a fully integrated CMOS oscillator with a tank quality factor of about 9.     

A Low Phase Noise LC VCO in 65 nm CMOS Process Using Rectangular Switching Technique

A low phase noise and low power LC voltage-controlled oscillator (VCO) has been designed using a 65-nm CMOS process. The phase noise is minimized by switching the differential core using a rectangular shaped voltage waveform, which is formed by a harmonic tuned LC tank assisted by a g_m3 boosting circuit. The g_m3 boosting circuit effectively maximizes the slope at the zero crossing point and reduces the transition time in which the switching transistor is operated at the triode region. The rectangular switching technique has improved the phase noise of the oscillator by 10 dB. The 450 mum times 540 mum chip consumes 4.34 mW. The proposed VCO has phase noises of -83.3, -110.7, and -131.8 dBc/Hz at 10 KHz, 100 KHz, and 1 MHz offset frequencies, respectively, from the 1.6-GHz carrier frequency.     

锁相环电路中压控振荡器的分析与设计

本文设计了一个应用于高频锁相环（PLL）系统的负阻LC压控振荡器,在传统LC压控振荡器基础上,通过采用二次谐波滤波技术降低了振荡器的相位噪声,并完成了电路的仿真。仿真结果表明,该压控振荡器的振荡频率在1．9—2．1GHz,其频率调节范围达到200MHz,并且在距中心频率1MHz处其相位噪声为-148．825dBc／Hz...     

Low phase noise wide tuning range digitally-controlled LC oscillator using switchable inductor

By adding a switched-loop around the inductor of a traditional LC oscillator, a single oscillator with 36% tuning range covers all American and European GSM cellular bands and meets the stringent phase noise requirements under +/-25% capacitor process variation. With the switch in the 'open' state, the measured phase noise at a 20 MHz offset from a 915 MHz carrier is -165 dBc/Hz, while at the same frequency with the switch 'closed' the phase noise performance only degrades by 2 dB. This circuit technique improves the tuning range of an LC oscillator dramatically without increasing die area.     

Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion

The tuning curve of an LC-tuned voltage-controlled oscillator (VCO) substantially deviates from the ideal curve 1//spl radic/(LC(V)) when a varactor with an abrupt C(V) characteristic is adopted and the full oscillator swing is applied directly across the varactor. The tuning curve becomes strongly dependent on the oscillator bias current. As a result, the practical tuning range is reduced and the upconverted flicker noise of the bias current dominates the 1/f/sup 3/ close-in phase noise, even if the waveform symmetry has been assured. A first-order estimation of the tuning curve for MOS-varactor-tuned VCOs is provided. Based on this result, a simplified phase-noise model for double cross-coupled VCOs is derived. This model can be easily adapted to cover other LC-tuned oscillator topologies. The theoretical analyses are experimentally validated with a 0.25 /spl mu/m CMOS fully integrated VCO for 5 GHz wireless LAN receivers. By eliminating the bias current generator in a second oscillator, the close-in phase noise improves by 10 dB and features -70 dBc/Hz at 10 kHz offset. The 1/f/sup 2/ noise is -132 dBc/Hz at 3 MHz offset. The tuning range spans from 4.6 to 5.7 GHz (21%) and the current consumption is 2.9 mA.     

A 12-GHz Fully Integrated Cascode CMOS LC VCO With Q-Enhancement Circuit

A fully integrated complementary metal oxide semiconductor (CMOS) cascode LC voltage controlled oscillator (VCO) with Q-enhancement technique has been designed for high frequency and low phase noise. The symmetrical cascode architecture is implemented with negative conductance circuit for improving phase noise performance in 0.18 mum CMOS technology. The measured phase noise is -110.8 dBc/Hz at the offset frequency of 1 MHz. The tuning range of 630 MHz is achieved with the control voltage from 0.6 to 1.4 V. The VCO draws 4.5 mA in a differential core circuit from 1.8 V supply.     

CMOS LC-oscillator phase-noise analysis using nonlinear models

In this paper, a second-order stochastic differential equation is used as a tool for the analysis of phase noise in a submicron CMOS LC oscillator. A cross-coupled topology typical of integrated CMOS designs is considered. Nonlinear limiting and mobility degradation effects in the circuit are modeled and used to predict the statistics of the random amplitude and phase deviations in terms of design variables. Assuming Gaussian noise disturbances and describing the phase noise as a random diffusion process, the average phase-noise power spectrum is derived and its accuracy verified with measurement and simulation results. Calculations for phase noise arising from stationary tank noise, nonstationary channel thermal noise, and flicker noise are discussed. The analysis is used to emphasize the fundamental power/performance tradeoff associated with compensation of tank losses via adjustments in the power supply and device size.     

Design issues in CMOS differential LC oscillators

An analysis of phase noise in differential cross-coupled inductance-capacitance (LC) oscillators is presented. The effect of tail current and tank power dissipation on the voltage amplitude is shown. Various noise sources in the complementary cross-coupled pair are identified, and their effect on phase noise is analyzed. The predictions are in good agreement with measurements over a large range of tail currents and supply voltages. A 1.8 GHz LC oscillator with a phase noise of -121 dBc/Hz at 600 kHz is demonstrated, dissipating 6 mW of power using on-chip spiral inductors     

Transposed flicker noise suppression in microwave oscillators usingfeedforward amplifiers

The authors describe the design of a low noise 7.6 GHz oscillator which achieves reduced transposed flicker noise by using a feedforward GaAs based power amplifier as the oscillator feedback amplifier, 20 dB noise suppression is demonstrated, at 12.5 kHz offset, in the oscillator when the error correcting amplifier is switched on. The phase noise in the error corrected version rolls off at (1/Δf)² at offsets >10 kHz. The phase noise performance, in the thermal noise region, is within 1 dB of the theoretical minimum     

Standing wave oscillators utilizing wave-adaptive tapered transmission lines

In this paper, we introduce a novel standing wave oscillator (SWO) utilizing standing-wave-adaptive tapered transmission lines. This structure enhances Q and lowers phase noise through loss-reducing shaping of the transmission line, such that it is adapted to the position-dependent amplitudes of standing waves. Measurements validate the advantages of the proposed technique. The phase noise of a MOS SWO with the tapered line is 5-10 dB less than that of a uniform-line MOS SWO over a wide range of offset frequencies, centered about 15 GHz. Demonstrating a valuable exploitation of standing wave properties, the novel design concept boosts the potential for the emergence of standing wave oscillators as a useful alternative to the traditional lumped LC oscillator.     

A 1.2-V RF front-end with on-chip VCO for PCS 1900 direct conversion receiver in 0.13-/spl mu/m CMOS

In this paper, a 1.2-V RF front-end realized for the personal communications services (PCS) direct conversion receiver is presented. The RF front-end comprises a low-noise amplifier (LNA), quadrature mixers, and active RC low-pass filters with gain control. Quadrature local oscillator (LO) signals are generated on chip by a double-frequency voltage-controlled oscillator (VCO) and frequency divider. A current-mode interface between the downconversion mixer output and analog baseband input together with a dynamic matching technique simultaneously improves the mixer linearity, allows the reduction of flicker noise due to the mixer switches, and minimizes the noise contribution of the analog baseband. The dynamic matching technique is employed to suppress the flicker noise of the common-mode feedback (CMFB) circuit utilized at the mixer output, which otherwise would dominate the low-frequency noise of the mixer. Various low-voltage circuit techniques are employed to enhance both the mixer second- and third-order linearity, and to lower the flicker noise. The RF front-end is fabricated in a 0.13-/spl mu/m CMOS process utilizing only standard process options. The RF front-end achieves a voltage gain of 50 dB, noise figure of 3.9 dB when integrated from 100 Hz to 135 kHz, IIP3 of -9 dBm, and at least IIP2 of +30dBm without calibration. The 4-GHz VCO meets the PCS 1900 phase noise specifications and has a phase noise of -132dBc/Hz at 3-MHz offset.     

推–推振荡器共用谐振器分析与低相位噪声设计

为实现低相位噪声平面振荡器,对推-推振荡器的共用谐振器与相位噪声优化方法进行了研究。提出一种基于多环式开口谐振环的差分传输线,通过加载一对耦合谐振环的方式实现2个单元振荡器之间的弱耦合,提高了共用谐振器的频率选择特性。基于该结构设计并实现了一种X波段推-推振荡器,在设计中采用一种基于振荡器有源品质因子的相位噪声优化方法。测试结果表明：该振荡器在输出二次谐波9.52 GHz处的相位噪声为-115.48 dBc/Hz@100 kHz,基波抑制度达到-54.55 dBc。     

A 1-V 3.8 - 5.7-GHz wide-band VCO with differentially tuned accumulation MOS varactors for common-mode noise rejection in CMOS SOI technology

In this paper, a 1-V 3.8 - 5.7-GHz wide-band voltage-controlled oscillator (VCO) in a 0.13-/spl mu/m silicon-on-insulator (SOI) CMOS process is presented. This VCO features differentially tuned accumulation MOS varactors that: 1) provide 40% frequency tuning when biased between 0 - 1 V and 2) diminish the adverse effect of high varactor sensitivity through rejection of common-mode noise. This paper shows that, for differential LC VCOs, all low-frequency noise such as flicker noise can be considered to be common-mode noise, and differentially tuned varactors can be used to suppress common-mode noise from being upconverted to the carrier frequency. The noise rejection mechanism is explained, and the technological advantages of SOI over bulk CMOS in this regard is discussed. At 1-MHz offset, the measured phase noise is -121.67 dBc/Hz at 3.8 GHz, and -111.67 dBc/Hz at 5.7 GHz. The power dissipation is between 2.3 - 2.7-mW, depending on the center frequency, and the buffered output power is -9 dBm. Due to the noise rejection, the VCO is able to operate at very low voltage and low power. At a supply voltage of 0.75 V, the VCO only dissipates 0.8 mW at 5.5 GHz.     

A 20-GHz InP-HBT voltage-controlled oscillator with wide frequencytuning range

This paper presents the design and implementation of a 20-GHz-band differential voltage-controlled oscillator (VCO) using InP heterojunction-bipolar-transistor process technology. Aimed at 20- or 40-Gb/s fiber-optic applications, the design is based on a single-stage feedback amplifier with no intentional L or C. The salient features of the proposed VCO are wide frequency tuning range compared to LC oscillators, and low power consumption and transistor count compared to ring-oscillator counterparts. The implemented VCO has an adjustable frequency range from 13.75 to 21.5 GHz and provides two complementary outputs. Total power consumption at 18.6 GHz is 130 mW, while the phase noise is -90.0 dBc/Hz measured at 1-MHz offset frequency     

LC振荡器相位噪声的非线性摄动分析技术

相位噪声是振荡器的重要性能指标,通过对振荡器的非线性微分方程的推导,从而引入新的参数来考虑振幅噪声和相位噪声之间的相关性同时把这些参数和振荡器的工作点联系起来。并且这些公式推导也考虑了LC谐振回路中振幅噪声和相位噪声之间的相关性。在此基础上这里研究了如何在时域状态方程下将噪声看成是对振荡输出信号的小扰动,并建立引入噪声后的随机微分方程,实现LC振荡器的相位噪声分析技术。     

一个8GHz高功率AlGaN/GaN HEMT VCO

基于中科院微电子所的AlGaN/GaN HEMT工艺研制了一个X波段高功率混合集成压控振荡器（VCO）。电路采用源端调谐的负阻型结构,主谐振腔由开路微带和短路微带并联构成,实现高Q值设计。在偏置条件为VD=20V, VG=-1.9V, ID=150mA时,VCO在中心频率8.15 GHz处输出功率达到28 dBm,效率21%,相位噪声-85 dBc/Hz@100 KHz,-128 dBc/Hz@1 MHz。调谐电压0~5V时,调谐范围50 MHz。分析了器件闪烁噪声对GaN HEMT基振荡器相位噪声性能的主导作用。测试结果显示了AlGaN/GaN HEMT工艺在高功率低噪声微波频率源中的应用前景。     

Design of an Optimized 2.5 GHz CMOS Differential LC Oscillator with Nonlinear Analysis for MOS Varactor

The oscillation amplitude and supply current relations for a differential CMOS oscillator are derived by using an analytic method. A simplified model to predict the phase noise performance of the oscillator is developed. The large signal analysis of a nonlinear inversion mode MOS varactor is presented. The derived expressions can help to design an optimized oscillator in terms of minimum phase noise and power consumption. The validity of the method has been verified by designing an LC CMOS oscillator in a 0.25 μm CMOS technology. The predictions are in good agreement with simulation results over a wide range of supply voltage.