一种用于Bluetooth发接器的倍频式VCO

介绍了一种适用于 Bluetooth发接器的 ,可以单片集成的倍频式压控振荡器 ( VCO)。这种 VCO由两部分组成 ,主 VCO的振荡频率是所需本振频率的一半 ,然后采用“注入锁频”原理对主 VCO的振荡频率进行倍频以产生本振信号。主 VCO和倍频电路都使用了片上集成螺旋电感 ,调谐用的变容元件使用 PMOS晶体管实现。经过版图设计和后仿真 ,在 TSMC0 .35 μm数字 COMS工艺 ,3.3V电源电压下 ,该 VCO在 2 .4GHz中心频率附近可以达到的相位噪声指标为 -1 2 5 d Bc/Hz( 60 0 k Hz) ,在输出摆幅为 60 0 m Vp- p时 ,功耗为 2 2 m W。     

基于锁相环的时钟相位插值电路设计与实现

千兆以太网收发器模拟前端的时钟恢复电路要求锁相环(PLL)能够提供"128相"等相位差的时钟信号.为了满足此要求,设计了一种相位插值电路,它在不增加四级VCO级数的基础上,对其输出时钟的相邻相位进行16插值.仿真结果表明,该插值电路使PLL的输出时钟相位从8相增加至128相,证明了电路的有效性.     

适用于半速率CDR改进型VCO的设计与实现

在0.13μm数字CMOS工艺下设计实现了一种改进型的差分振荡器电路,该电路采用四级环形结构,其中心工作频率为1.25 GHz,版图面积为50μm×50μm,工作范围1.1～1.4 GHz,VCO的增益约为300 MHz/V,在1.2 V电源电压下、工作频率为1.25 GHz时的平均功耗约为10 mW.版图后模拟结果表明,该VCO输出的四相时钟信号间隔均匀,占空比接近50%,可适用于基于PLL的2.5 Gbps的半速率时钟数据恢复电路.     

一种高速低过冲电荷泵电路的设计

为了有效降低传统电荷泵电路的充放电过冲电流,提高电荷泵输出控制电压的稳定性,提出、设计并实现了一种高速低过冲的电荷泵结构,该电路适用于高速锁相环及时钟数据恢复电路.电路在电源电压为1.2 V的0.13 μm CMOS工艺下设计实现,并对版图数据进行了HSPICE模拟,其结果表明,电路在2.5 GHz的速度下能很好的工作,同时电流过冲相比传统电荷泵下降了70%.     

0.25μm CMOS千兆以太网发送器设计

分析了千兆以太网体系结构,给出了符合IEEE 802.3z标准中1000BASE-X规范的发送器电路结构,并采用TSMC 0.25 μm CMOS 混合信号工艺设计了符合该规范的高速复接电路和锁相环时钟倍频电路.芯片核心电路面积分别为(0.3×0.26)mm2和(0.22×0.12)mm2.工作电压2.5 V时,芯片核心电路功耗分别为120 mW和100 mW.时钟倍频电路的10倍频输出时钟信号频率为1.25 GHz,其偏离中心频率1MHz处的单边带相位噪声仅为-109.7 dBc/Hz.在驱动50 Ω输出负载的条件下,1.25 Gbit/s的高速输出数据信号摆幅可达到410 mV.     

一种用于千兆以太网发接器的高速串-并转换电路

高速串—并转换电路是数字基带传输系统中的重要单元。在对几种常见串—并转换电路的结构和性能进行比较的基础上，利用动态D触发器实现了一种简单实用的结构，并用它设计了适用于十兆以太网发接器的串—并转换电路。同时，对电路中可能存在的问题，如时钟信号的分布，以及动态单元的电荷泄漏，进行了讨论。     

采用0.25μmCMOS工艺、适用于LVDS驱动器的高性能多相时钟生成器的设计

提出了一种适用于 L VDS驱动器的电荷泵锁相环 (PL L)多相时钟生成器的设计方法 ,特别是在压控环形振荡器 (VCO)设计中采用了高温度补偿和高电源抑制比的新技术 ,使得 VCO的固定频率基本不受温度和电源电压变化的影响 .采用 U MC的 0 .2 5 μm CMOS工艺模型 ,在 Cadence的环境下用 spectre S仿真器模拟 ,结果表明设计的 PL L 对于不同的 PVT:SSS、TTT、FFF、SFS、FSF(头两个字母表示工艺变化引起的模型参数的变化 ,第三个字母表示系统工作条件 :T为 75℃ ,3.3V;S为 12 5℃ ,3.0 V;F为 0℃ ,3.6 V) ,均能得到符合标准要求的7相时钟信号 ,其中 VCO固定频     

一种改进型的CMOS电荷泵锁相环电路

设计了一种宽频率范围的CMOS锁相环(PLL)电路,通过提高电荷泵电路的电流镜镜像精度和增加开关噪声抵消电路,有效地改善了传统电路中由于电流失配、电荷共享、时钟馈通等导致的相位偏差问题。另外,设计了一种倍频控制单元,通过编程锁频倍数和压控振荡器延迟单元的跨导,有效扩展了锁相环的锁频范围。该电路基于Dongbu HiTek 0.18μm CMOS工艺设计,仿真结果表明,在1.8 V的工作电压下,电荷泵电路输出电压在0.25~1.5 V变化时,电荷泵的充放电电流一致性保持很好,在100 MHz~2.2 GHz的输出频率内,频率捕获时间小于2μs,稳态相对相位误差小于0.6%。     

采用0.25μm CMOS工艺、适用于LVDS驱动器的高性能多相时钟生成器的设计

提出了一种适用于LVDS驱动器的电荷泵锁相环(PLL)多相时钟生成器的设计方法,特别是在压控环形振荡器(VCO)设计中采用了高温度补偿和高电源抑制比的新技术,使得VCO的固定频率基本不受温度和电源电压变化的影响．采用UMC的0.25μm CMOS工艺模型,在Cadence的环境下用spectreS仿真器模拟,结果表明设计的PLL对于不同的PVT：SSS、TTT、FFF、SFS、FSF(头两个字母表示工艺变化引起的模型参数的变化,第三个字母表示系统工作条件：T为75℃,3.3V;S为125℃,3.0V;F为0℃,3.6V),均能得到符合标准要求的7相时钟信号,其中VCO固定频率所对应的温度系数为32ppm/℃,电源反射比为0.2%/V．     

锁相环中的充电泵电路的研究

针对消除传统电荷泵电路存在的MOS开关的电荷注入效应,时钟馈通效应,电荷泄露和充放电电流失配等产生的锁相环的相位偏差问题,设计了两种新型的电荷泵电路.这两种电路的设计和仿真采用了0.6 μm CMOS工艺,电源电压为5 V,功耗分别为0.65 mW和0.7 mW.仿真结果表明,两种新型电荷泵电路的转换速度得到了提高,输出电压近似于电源电压到地的全摆幅并具有稳定的充放电步长,可用于高速锁相环电路.     

A 1.41–1.72 GHz sigma-delta fractional-N frequency synthesizer with a PVT insensitive VCO and a new prescaler

A 1.41–1.72 GHz fractional-N phase-locked loop (PLL) frequency synthesizer with a PVT insensitive voltage-controlled oscillator (VCO) is presented. In this PLL, a VCO with process, voltage, and temperature (PVT) insensitive bias circuit, and a divided-by-7/8 prescaler with improved multi-phase frequency divider are adopted. A novel multi-stage noise shaping (MASH) sigma-delta modulator (SDM) is adopted here. A new combination of low-current-mismatch charge pump (CP) and a phase/frequency detector (PFD) is proposed in this paper. Using Hejian Technology CMOS 0.18 μm analog and digital mixed-mode process, a fractional-N PLL prototype circuit is designed, the VCO in the prototype circuit can operate at a central frequency of 1.55 GHz, and its phase noise is −121 dBc/Hz at 1.0 MHz, the variety of phase noise is depressed by about 1.4 dB with the help of PVT insensitive bias. Under a 1.8-V supply voltage, the phase noise of the PLL is −113 dBc/Hz at 1.0 MHz.     

Frequency multiplier using pulse-width control loop

A frequency multiplier circuit based on a well-known pulse-width control loop is presented. The proposed circuit can be used to enhance the output frequency range of a phase-locked loop (PLL) by using multiple phases of the voltage-controlled oscillator. It can be used for enhancing the output frequency range of new as well as existing PLL designs with minimum impact on PLL loop dynamics. The circuit is generic in nature and can be used with any multi-phase oscillator type. The circuit is designed in 65 nm complimentary metal oxide semiconductor (CMOS) technology and has been simulated across process, voltage and temperature (PVT) corners with temperature variation from ?40°C to 125°C, analogue supply voltage variation from 1.62 V to 1.98 V, and digital supply voltage variation from 1.1 V to 1.3 V.     

低相噪超多频段VCO宽带锁相环的研究

为了解决宽带锁相环设计中相位噪声和输出频率范围的矛盾,分析并设计了一种基于超多频段压控振荡器(VCO)锁相环的方案。该方案通过降低VCO的频率灵敏度和每个VCO 配置LC矩阵等效多个VCO的方法,使VCO在保证输出的频率范围的同时,优化了相位噪声。实验结果发现,该方案可以使锁相环在保证较大的输出频率范围前提下拥有更低的相位噪声。     

一种新型非线性PLL模型及其在毫米波集成防撞雷达中的应用

提出了一种新的非线性PLL用于VCO的非线性补偿,利用声表面波延迟线来实现延时混频,并将混频后的中频信号锁定PLL结构,深入分析了这种PLL的环路相位模型,使用Agilent ADS软件对锁相环路进行了仿真,验证了所提出的环路相位模型的准确性,所有的理论推导和仿真结果表明,建立的PLL环路相位模型可以用来实现防撞雷达中VCO(电压控制振荡器)的线性化,准确可靠,利于雷达系统的集成化和高精度。     

A 2.5-Mb/s GFSK 5.0-Mb/s 4-FSK automatically calibratedΣ-Δ frequency synthesizer

This paper describes a new sigma-delta (Σ-Δ) frequency synthesizer for Gaussian frequency and minimum shift keying (GFSK/GMSK) modulation. The key innovation is an automatic calibration circuit which tunes the phase-locked loop (PLL) response to compensate for process tolerance and temperature variation. The availability of this new calibration method allows the use of precompensation techniques to achieve high data rate modulation without requiring factory calibration. The calibration method can be applied to GFSK/GMSK modulation and also M-ary FSK modulation. The PLL, including 1.8-GHz voltage controlled oscillator (VCO), Σ-Δ modulator, and automatic calibration circuit, has been implemented in a 0.6-μm BiCMOS integrated circuit. The test chip achieves 2.5 Mb/s using GFSK and 5.0 Mb/s using 4-FSK     

A local oscillator for WCDMA band VII based on frequency multiplication

This work explores the generation of a local oscillator for WCDMA band VII based on frequency multiplication of a GSM reference. The frequency multiplier is based on a PLL, which includes a compact VCO based on a ring oscillator. A proper PLL design allows to sufficiently reject the relative high VCO phase noise, complying with the WCDMA requirements. The effectiveness of the proposed approach is proved with the design of the whole multiplier in a 90?nm CMOS technology. The generated oscillation ranges from 3 to 6?GHz, while the simulated phase noise is ?120 and ?144?dBc/Hz at a frequency offset of 0.6?and 20?MHz, respectively, dissipating 6.3?mW.     

A 1.2-V-only 900-mW 10 gb ethernet transceiver and XAUI interface with robust VCO tuning technique

This paper describes the design and the implementation of a fully integrated 10 Gb Ethernet transceiver in a 0.13-/spl mu/m CMOS process using only a 1.2 V supply. A coarse control algorithm that combines a voltage range monitoring circuit with a frequency lock detector provides a robust operation against process, voltage, and temperature (PVT) variations for a VCO with a ring oscillator. With the use of a blind oversampling DPLL architecture, four channels of XAUI transceivers can share a single PLL, eliminating the clock synchronization problem between channels. Also, the total number of clock domains for the entire chip is reduced to three, making the integration of the XAUI with the 10G transceiver much simpler. The test chip consumes 898 mW from a 1.2 V supply.     

锁相环设计中的功率分配与分频器配置方法

针对锁相环频率合成器工程设计中的问题,对锁相环参考频率输入端的馈电电路提出改进措施,增强了锁相环参考频率信号的输入功率,为提高相位噪声性能创造了有利条件。对传统的VCO输出T型电阻功率分配网络进行改进,减小了因功率过多分配给锁相环反馈支路所造成的损失,最大限度地把VCO的功率分配给端口负载。并给出了锁相环频率合成器在多频点和单频点信号输出时分频器的通用配置方法。实验验证该理论分析和设计方法的正确性。     

锁相环产生具有高线性度三角调频信号的方法

介绍了一种利用锁相环电路产生三角调频信号的方案,并对信号线性度的优化进行了研究。通过快速改变锁相环系统中分频器的分频比N,产生相应的控制电压控制VCO输出三角调频信号。文中方案实施的关键在于分频比N的跳变周期Δt的选择,在跳变周期Δt大于锁定时间的前提下,Δt越小调频信号的线性度越好。通过对实际电路的测量,验证了此方案的可行性。相比于其他方案,文中方案具有电路结构成熟,可靠性高且方便调节等优点。     

A 6-GHz integrated phase-locked loop using AlGaAs/GaAsheterojunction bipolar transistors

A fully integrated 6-GHz phase-locked-loop (PLL) fabricated using AlGaAs/GaAs heterojunction bipolar transistors (HBTs) is described. The PLL is intended for use in multigigabit-per-second clock recovery circuits for fiber-optic communication systems. The PLL circuit consists of a frequency quadrupling ring voltage-controlled oscillator (VCO), a balanced phase detector, and a lag-lead loop filter. The closed-loop bandwidth is approximately 150 MHz. The tracking range was measured to be greater than 750 MHz at zero steady-state phase error. The nonaided acquisition range is approximately 300 MHz. This circuit is the first monolithic HBT PLL and is the fastest yet reported using a digital output VCO. The minimum emitter area was 3 μm×10 μm with f_t=22 GHz and f_max=30 GHz for a bias current of 2 mA. The speed of the PLL can be doubled by using 1-μm×10-μm emitters in next-generation circuits. The chip occupies a die area of 2-mm×3-mm and dissipates 800 mW with a supply voltage of -8 V