基于混沌映射的相关跳频系统转移函数构造

频率转移函数是相关跳频的关键技术之一,将直接影响相关跳频通信系统的性能.本文在深入分析转移函数数学模型和Logistic映射特点的基础上,提出了一种基于Logistic满映射混沌序列的转移函数构造方法.性能分析结果表明,基于该类转移函数的相关跳频序列具有良好的随机性和均匀性,能获得最佳相关纠错性能.     

Viterbi译码算法在55系列DSP上的C语言实现

为了在DSP中实现Viterbi译码,用C语言编程实现了一种全并行连续译码的Viterbi译码算法。其各功能模块用函数设计,纠错性能的测试和验证采用文件读写的方法,便于处理大容量的编译码数据,且能容易地修改错误的形式。仿真测试结果表明,该Viterbi译码算法的纠错性能完全达到甚至优于Viterbi理论算法纠错性能的极限,采用C语言设计,程序可读性好,且便于在不同系列DSP平台之间移植。     

一种串行Turbo-DFH迭代解调译码方案

该文将差分跳频(DFH)系统的频率转移过程视为一种编码,提出了一种串行Turbo-DFH迭代解调译码方案。该方案的编码器由外编码器,交织器和差分跳频转移函数串行级联组成,译码器采用串行迭代结构译码。并针对DFH系统的特点,推导了一种新的DFH系统软输入软输出算法。仿真结果表明,该解调译码方案相对传统的DFH解调算法,性能得到了明显的改善。     

多序列跳频系统及其在瑞利衰落信道下性能分析

差分跳频中,用户数据对频率选择的约束性比较弱。对此本文提出多序列跳频（MSFH）系统,其发送频率不仅是用户数据的函数,也受同步跳频序列严格约束,因此可以采用窄带接收更好地抑制带外干扰。具体地,数据分组从一簇相互正交的跳频序列中选出一个序列,该序列的当前频率由射频端直接发送,而无需对发送信号进行调制。得到了瑞利衰落信道中,未编码和采用卷积编码-硬/软判决Viterbi译码时MSFH符号误码率性能。计算和仿真表明,在相同编码增益下,MSFH误码率低于常规跳频系统;与差分跳频译码复杂度相当时,MSFH性能亦具有一定优势。      

一种稳健的水声差分跳频通信体制

基于水下目标的通信保密、安全可靠性要求,提出一种新的水声差分跳频通信体制,与传统跳频通信不同,它是利用相邻跳频调制信息.通过分析其频率转移函数的构造方法和差分跳频信号的多途特征,提出一种基于自相关的短时傅里叶变换的跳频检测方法,并利用Viterbi算法纠正部分错码.仿真结果表明,该文提出的通信体制和检测方法能有效的克服水下干扰、多途和多普勒频偏,在较低信噪比下,仍有较好的误码性能,适用于水下安全保密通信场合.     

卷积码差分跳频系统抗部分频带干扰的性能

基于对无编码差分跳频系统抗部分频带干扰性能的研究,将卷积码引入差分跳频系统,研究了在有精确干扰状态信息的情况下,采用无迭代译码和迭代译码时相对于无编码系统的性能改善.同时,在无法得到精确干扰状态信息的情况下,提出了一种迭代干扰状态估计及译码算法.理论分析结果表明:在有精确干扰状态信息的情况下,采用卷积纠错编码和无迭代译码,对可用频率数为8的差分跳频系统,当比特误码率(BER)为10~(-6)时,性能改善约为2.5dB;而采用迭代译码,当BER为10~(-10)时,相对于无迭代译码,性能可进一步改善6dB.仿真结果则验证了迭代估计及译码算法的正确性,采用该算法可使编码系统在无精确干扰状态信息的情况下,仍能保持良好的抗干扰能力.     

基于混沌映射的差分跳频频率编

针对差分跳频系统频率编码及跳频序列的设计问题,提出利用混沌映射构造差分频率编码,并分析了其频率状态转移的Markov性和编译码特点。最后检验了基于混沌映射的差分跳频频率编码的统计性能,结果表明,其产生的跳频序列具有较好的均匀性和随机性,不失为一种具有较高线性复杂度的有效的差分跳频转移函数。     

（2,1,7）卷积码编译码器的FPGA实现

卷积码是一种重要的前向纠错信道编码方式,其纠错性能常常优于分组码,且（2,1,7）卷积码已应用于现代卫星通信系统中。Viterbi译码算法能最大限度地发挥卷积码的优异性能。这里采用Verilog HDL语言设计出（2,1,7）卷积码的编码器模块和基于Viterbi算法的译码器模块,译码器采用全并行结构,译码速度快。阐述了编译码器各模块的设计原理,并在ModelSim给出各模块的仿真测试结果。同时对译码器进行纠错性能测试,测试结果表明该Viterbi译码器有良好的纠错性能。     

SOVA算法对Viterbi算法的修正

在Viterbi算法中引入软值进行修正之后的算法称作SOVA算法(Soft Output Viterbi Algorithm)。SOVA算法在Viterbi算法的基础上,路径量度引入了比特先验信息,对每位译码比特以后验概率似然比的形式提供软输出,因而可提供更高的译码性能。特别,SOVA算法可用于级联码的迭代译码,采用Tuobo原理使不同分量码之间交换软信息,从而可显著提高这类码的纠错能力。     

相关跳频转移函数的双随机矩阵模型及其应用

该文分别从状态空间的分解和平稳分布等角度对双随机矩阵以及双随机马氏(Markov)链的性质进行了研究,并将这些性质应用到相关跳频转移函数的分析和建模。文中证明了转移函数的双随机矩阵数学模型就状态转移过程的均匀性来说是完备的。基于对该模型的分析,提出了一种转移函数构造方法周期分组法,通过将频率转移过程构造成一个周期性双随机马氏链,可以获得纠错性能和频率间隔性能俱佳的转移函数。     

Viterbi decoding algorithm for convolutional codes with repeat request

Using the Viterbi decoding algorithm with repeat request for convolutional codes is proposed, and the resulting performance is analyzed by random coding and generating function arguments and by simulation. It is shown that the reliability function of the proposed decoding algorithm is asymptotically twice that of the Viterbi decoding algorithm without repeat request, and that in certain practical situations the proposed algorithm can save about 50 percent in constraint length over the ordinary Viterbi algorithm for a given performance.     

卷积码Viterbi译码器的硬件实现

第三代移动通信系统标准中普遍采用卷积码和Turbo码作为信道编码方案.本文首先阐述了维特比译码算法,然后论述了(2,1,3)卷积码编码电路和维特比译码的单片机实现方案.最后把维特比算法与交织方案相结合,统计结果表明纠错性能有较大改善.     

A Multiple Stack Algorithm for Erasurefree Decoding of Convolutional Codes

A new algorithm for erasurefree sequential decoding of convolutional codes is introduced which achieves low error probabilities at substantially higher decoding speeds than the Viterbi decoding algorithm. The algorithmic properties of the Multiple Stack Algorithm (MSA) are investigated and it is demonstrated that the MSA reaches a decision with an exponentially rather than Pareto distributed computational effort. The MSA's error probability on the binary symmetric channel is studied as a function of its parameters and its performance and complexity compared to that of the Viterbi algorithm. The MSA is seen to achieve equal and lower error probabilities with a significantly lower average decoding effort. The new algorithm can thus be considered an attractive alternative to the Viterbi algorithm where low error probabilities and high decoding speeds are required simultaneously.     

An efficiently implementable maximum likelihood decoding algorithm for tailbiting codes

Convolutional tailbiting codes are widely used in mobile systems to perform error-correcting strategies of data and control information. Unlike zero tail codes, tailbiting codes do not reset the encoder memory at the end of each data block, improving the code efficiency for short block lengths. The objective of this work is to propose a low-complexity maximum likelihood decoding algorithm for convolutional tailbiting codes based on the Viterbi algorithm. The performance of the proposed solution is compared to that of another maximum likelihood decoding strategy which is based on the A* algorithm. The computational load and the memory requirements of both algorithms are also analysed in order to perform a fair comparison between them. Numerical results considering realistic transmission conditions show the lower memory requirements of the proposed solution, which makes its implementation more suitable for devices with limited resources.     

乘积合并接收的差分跳频通信系统在瑞利衰落信道上抗部分频带干扰的性能分析

该文介绍了一种新型短波跳频通信技术差分跳频,频率转移函数设计和信号的检测方法是差分跳频中的关键技术。在瑞利衰落信道上,在有部分频带干扰和加性高斯白噪声共存的条件下,采用乘积合并接收的方法,对差分跳频通信系统的误符号性能进行了理论分析,同时做出相应的计算机仿真。结果证实了,在瑞利衰落信道上差分跳频通信系统采用乘积合并接收的方法要比采用线性合并接收的方法具备更好的抗部分频带干扰的性能。     

A reconfigurable, power-efficient adaptive Viterbi decoder

Error-correcting convolutional codes provide a proven mechanism to limit the effects of noise in digital data transmission. Although hardware implementations of decoding algorithms, such as the Viterbi algorithm, have shown good noise tolerance for error-correcting codes, these implementations require an exponential increase in very large scale integration area and power consumption to achieve increased decoding accuracy. To achieve reduced decoder power consumption, we have examined and implemented decoders based on the reduced-complexity adaptive Viterbi algorithm (AVA). Run-time dynamic reconfiguration is performed in response to varying communication channel-noise conditions to match minimized power consumption to required error-correction capabilities. Experimental calculations indicate that the use of dynamic reconfiguration leads to a 69% reduction in decoder power consumption over a nonreconfigurable field-programmable gate array implementation with no loss of decode accuracy.