Integrated packaging of over 100 GHz bandwidthuni-traveling-carrier photodiodes

Hybrid packaging techniques, in which the device substrate is different from the package substrate, and wire bonding or solder interconnections are used, are inadequate for ultrahigh-speed (>100 GHz) wideband applications. By employing wafer-bonding techniques, an integrated packaging (IP) technology was developed, in which devices are fabricated directly on the package substrate, and the interconnections are made as a part of the device fabrication process. This IP process was used to fabricate uni-traveling-carrier photodiodes (UTC-PD's) integrated with millimeter-wave coplanar waveguides (CPW) on package compatible sapphire with high yield. The performance of wafer-bonded UTC-PD's with 3-dB bandwidth of 102 GHz was similar to that of conventional devices, and the CPW's exhibited low dispersion     

Thermal resistance calculation of AlGaN-GaN devices

We present an original accurate closed-form expression for the thermal resistance of a multifinger AlGaN-GaN high electron-mobility transistor (HEMT) device on a variety of host substrates including SiC, Si, and sapphire, as well as the case of a single-crystal GaN wafer. The model takes into account the thickness of GaN and host substrate layers, the gate pitch, length, width, and thermal conductivity of GaN, and host substrate. The model's validity is verified by comparing it with experimental observations. In addition, the model compares favorably with the results of numerical simulations for many different devices; very close (1%-2%) agreement is observed. Having an analytical expression for the channel temperature is of great importance for designers of power devices and monolithic microwave integrated circuits. In addition, it facilitates a number of investigations that are not practical or possible using time-consuming numerical simulations. The closed-form expression facilitates the concurrent optimization of electrical and thermal properties using standard computer-aided design tools.     

Steady state thermal characterization and junction temperatureestimation of multichip module packages using the response surfacemethod

The steady state thermal performance of semiconductor packages has been traditionally reported through the utilization of a single junction-to-ambient thermal resistance constant commonly referred to as &thetas;_ja. This is particularly inadequate for multichip modules where several devices reside within the same package structure. This paper discusses how a central composite design of experiments can be applied to provide a more accurate thermal characterization of a multichip module package. The end product is a series of linear or polynomial equations which can be utilized by the customer to calculate individual device junction temperatures over a wide variation of convection cooling environments and multiple device power dissipations. A 352 plastic ball grid array package, which encompasses three individual integrated circuit devices, is used as an example. The paper steps through the sensitivity analysis and evaluates the accuracy of the resulting equations. This method of thermal characterization can be easily applied to single chip modules of varying power and cooling regimes, or multiple output devices where several power junctions reside within the same integrated circuit     

An analytical method for direct calculation of E and H-fieldpatterns of conductor-backed coplanar waveguides

A new direct method of computing the electromagnetic field patterns surrounding the conductor-backed coplanar waveguide (CPW) structure is proposed. Analytical closed-form expressions describing the quasi-TEM field pattern in both the air and the dielectric substrate for conductor-backed CPW's are presented. This approach is based on a new technique which employs a series of inverse conformal mappings to transform a known field pattern from a rectangular structure back into the CPW structure in order to obtain its unknown field pattern directly. A computer program based on this method has demonstrated the speed at which the fields can be plotted compared to existing methods which require repetitive application. Graphical results of these field patterns are presented as a function of the CPW's geometry and dielectric substrate thickness. These held maps which have been directly drawn with true curvilinear squares enable the determination of power flow density, since the same power flows through each square. This direct method of characterizing the power flow density throughout the CPW structure could become an important design tool for the modeling of coplanar monolithic microwave integrated circuits (CMMIC's)     

An enhanced quasi-monolithic integration technology for microwave and millimeter wave applications

A new technology for integration of high frequency active devices into low cost silicon substrate has been introduced. The novel fabrication process gives excellent advantages such as extremely low thermal resistance, and a much lower thermo-mechanical stress than the earlier quasimonolithic integration technology (QMIT) concept . This highly improves the packaging lifetime and electrical characteristics of the active devices. The fabrication process is simple and compatible with fabrication of high-Q passive elements. Successful integration of high-Q passive elements on low resistivity silicon substrate in this technology has been possible for the first time. In comparison to the earlier concept of QMIT, elimination of air-bridges in this technology not only reduces the parasitic elements but also enables the fabrication of the rest of the circuit after measuring the microwave characteristics of the embedded active devices. This makes very accurate microwave and millimeter-wave designs possible. Using the new fabrication process, microwave and millimeter-wave circuits (with both coplanar and microstrip lines) containing power devices have for the first time been possible. Furthermore, the enhanced QMIT can be considered as an organic deposited multi chip module (MCM-D), which is a potential candidate for integration an system on a package (SOP) at microwave and millimeterwave frequencies.     

Optimization and Fabrication of a Thick Printed Thermoelectric Device

Thermoelectric power generation technology aims to convert thermal energy into electricity. Micromodule design optimization depends directly on the thermal environment. For low thermal energy input, optimized thermoelectric devices require 100 μm to 500 μm element thickness. These dimensions currently present a challenge for standard mass-production manufacturing techniques. In this paper, a unique printing technology for micromodule fabrication is presented. This technology is compared with a traditional bulk thermoelectric manufacturing process to highlight the advantages of the printing process to obtain scalable thermoelectric devices. Initial thermoelectric materials have been integrated in inks and then deposited by a spray technology onto a polymer substrate. A complete micromodule for application on nonplanar surfaces is also presented.     

Flip-chip on flex integrated power electronics modules for high-density power integration

Three-dimensional flip-chip on flex (FCOF) integrated power electronics modules (IPEMs) have been fabricated for high-density power applications. In this FCOF-IPEM structure, solder-bumped devices were flip-soldered to a flexible substrate with electrical circuits etched on both sides. One side of the flex provides interconnection to power devices while the other is used to construct a simple gate-drive circuit; via holes through the flex integrate the power stage and gate-drive together. Solder-bumped MOSFET devices were obtained by a metallization processing and were used in the FCOF power module construction to improve thermal performance, power density, and integration. With this packaging approach, the multiple solder bumps, instead of the thin, long bonding wires were utilized to connect the power devices to the flex substrate and to improve heat dissipation, lower parasitic oscillations, and reduce package size. Reliability of solder joints has been dealt with through selection of materials, such as use of flexible substrates and underfill encapsulation, and design of joint shape for lower thermomechanical stresses. A comparative study of continuous switching test results have shown that the FCOF-IPEMs have better electrical performance than commercial wire bonded power modules.     

Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods

The growing packing density and power consumption of very large scale integration (VLSI) circuits have made thermal effects one of the most important concerns of VLSI designers. The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnections. Recent data shows that more than 50% of all integrated circuit failures are related to thermal issues. This paper presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power VLSI circuits. The paper is concluded with an overview of techniques to improve the full-chip thermal integrity by means of off-chip versus on-chip and static versus adaptive methods.     

Thermal modeling of power gallium arsenide microwave integratedcircuits

Manufacturers are developing power devices for ever higher frequencies using GaAs MESFETs and heterojunction bipolar devices constructed with III-V compounds on GaAs substrates, as well as integrated power devices on monolithic microwave integrated circuits (MMICs). A problem with the technology is the low thermal conductivity of gallium arsenide, giving rise to thermal design problems that must be solved if good reliability is to be achieved. A three-dimensional numerical simulator is used to study this problem. In particular, the approximations which are possible in performing realistic assessments of the thermal resistance of typical GaAs power device structures under steady-state conditions are examined     

Three-dimensional flip-chip on flex packaging for power electronicsapplications

We have extended the concept of flip-chip technology, which is widely used in IC packaging, to the packaging of three-dimensional (3-D) integrated power electronics modules (IPEMs). We call this new approach flip-chip on flex IPEM (FCOF-IPEM), because the power devices are flip-chip bonded to a flexible substrate with control circuits. We have developed a novel triple-stacked solder bump metallurgy for improved and reliable device interconnections. In this multilayer structure, we have carefully selected packaging materials that distribute the thermo-mechanical stresses caused by mismatching coefficients of thermal expansion (CTEs) among silicon chips and substrates. We have demonstrated the feasibility of this packaging approach by constructing modules with two insulated gate bipolar transistors (IGBTs), two diodes, and a simple gate driver circuit. Fabricated FCOF-IPEMs have been successfully tested at power levels up to 10 kW. This paper presents the materials and reliability issues in the package design along with electrical, mechanical, and thermal test results for a packaged IPEM     

Electrical characterization and reliability study of integrated GaN power amplifier in multi-layer thin-film technology

In this work, the degradation of a GaN power amplifier (PA) integrated in a thin film multi-chip module (MCM-D) interconnect technology is investigated by means of DC and RF measurements. Failure analysis has demonstrated that improper thermal contact may cause the PA module performance degradation. Moreover, we have experimentally studied the thermal effects on the RF performance of MCM-D and low-temperature co-fired ceramic (LTCC) PAs. It shows that the device exhibits a higher output power density on a thinned MCM-D substrate than on an LTCC substrate with thermal vias, and also that the output power density can be further improved by reducing the heat spread distance between active devices and heat sink.     

硅衬底上共面线的特性及应用

基于理论和实验结果对深亚微米硅集成电路中的共面传输线的特性进行了研究,提出了硅衬底上传输线分布参数的提取方法和减小共面线衰减的一些设计准则.成功地将共面线应用在深亚微米高速集成电路的设计中,并给出了放大器芯片和共面线的测试结果.测试结果表明:在深亚微米CMOS高速集成电路中,用共面线实现电感是一种行之有效的方法.     

Coplanar Waveguide: A Surface Strip Transmission Line Suitable for Nonreciprocal Gyromagnetic Device Applications

A coplanar waveguide consists of a strip of thin metallic film on the surface of a dielectric slab with two ground electrodes running adjacent and parallel to the strip. This novel transmission line readily lends itself to nonreciprocal magnetic device applications because of the built-in circularly polarized magnetic vector at the air-dielectric boundary between the conductors. Practical applications of the coplanar waveguide have been experimentally demonstrated by measurements on resonant isolators and differential phase shifters fabricated on low-loss dielectric substrates with high dielectric constants. Calculations have been made for the characteristic impedance, phase velocity, and ripper bound of attenuation of a transmission line whose electrodes are all on one side of a dielectric substrate. These calculations are in good agreement with preliminary experimental results. The coplanar configuration of the transmission system not only permits easy shunt connection of external elements in hybrid integrated circuits, but also adapts well to the fabrication of monolithic integrated systems. Low-loss dielectric substrates with high dielectric constants may be employed to reduce the longitudinal dimension of the integrated circuits because the characteristic impedance of the coplanar waveguide is relatively independent of the substrate thickness; this may be of vital importance for Iow-frequency integrated microwave systems.     

X 波段四通道MMCM 基板设计

低温共烧陶瓷（LTCC）是制作微波多芯片组件（MMCM）基板的理想材料。本文介绍了基于LTCC 工艺的微 波传输线、集成腔体、功分器和散热过孔的设计。对于多通道微波组件,采用带状传输线和腔体结构有利于实现通道 间的高隔离度,集成功分器和浆料电阻有利于实现组件的小型化并可获得较好的微波性能,而矩阵散热过孔可以显著 改善基板导热性能,满足小功耗器件的散热要求。     

某设备电子控制模块的热设计

随着电子元器件的高度集成化及加工制造工艺手段的不断提高,电子设备功率密度越来越大,对电子设备进行热设计在电子设备设计过程中越来越重要.该文首先介绍了电子设备热设计的层次、研究内容和任务,然后具体介绍了选择冷却方式的准则,并根据准则选取了合理的冷却方式,设计了散热系统结构,并通过数值模拟计算得到了设备内部的热流场和温度分...     

Micromachining of Air-Bridges on SU-8 Substrates

This paper describes a procedure developed to fabricate air-bridges on coplanar transmission lines using a SU-8 substrate. SU-8 is attractive for micromachined multilayer circuit fabrication because it is photo-polymerizable resin, leading to safe, economical processing. The ability to fabricate air-bridges provides a means of suppressing the coupled slotline mode, thereby enabling single-mode design. The air-bridges also provide ground equalization at coplanar discontinuities. The properties of the air-bridge are investigated and compared to similar structures without air-bridges. As examples of possible device applications of this technology, an asymmetrical slot antenna and coplanar waveguide both operating at 35 GHz are presented. The return loss of both devices is 5 dB lower on structures that contain the air-bridge. This technology is promising for extending the use of SU-8 at millimeter-wave frequencies.     

GaAs SAMP Device for Ku-Band Switching

Switchable attenuating medium propagation (SAMP) devices are coplanar transmission lines on an epitaxial semiconductor (GaAs) substrate. These transmission lines can be switched rapidly between states of high and low attenuation by controlling the width of a depletion layer under the center conductor. SAMP devices can easily be characterized by the use of transmission line theory. They are well suited for use in monolithic microwave integrated circuits (MMIC's). Experimental performance data and theoretical background will be presented.     

Surface-to-Surface Transition via Electromagnetic Coupling of Coplanar Waveguides

A transition is investigated which couples coplanar waveguide on one substrate surface (a motherboard) to coplanar waveguide on another substrate surface (a semiconductor chip or subarray) placed above the first. No wire bonds are necessary. A full-wave analysis using coupled line theory is presented and verified experimentally. The use of this transition for coupling to millimeter-wave integrated circuits is discussed.     

一种基于SiP的数字光收发微系统设计与验证

根据整机小型化需求,设计了一种数字光收发微系统.以系统级封装技术为基础,采用管壳与基板一体化陶瓷针栅阵列封装,对光收发系统所需的各类集成电路裸芯片、光器件和阻容等无源元件进行高密度集成.通过版图设计、信号完整性、电源完整性及热应力仿真,研制出样品.经测试,信号接收SNR大于65 dBFs,SFDR大于86 dBc.模块...     

High frequency electrical circuits on a planar lightwave circuitplatform

We investigated the propagation losses and the characteristic impedances Z_L of coplanar waveguides (CPWs) and microstrip lines (MSLs) on a planar lightwave circuit (PLC)-platform formed on a silica/silicon substrate. The loss of the CPWs was 2.7 dB/cm at 10 GHz on the PLC-platform with 30 μm thick silica layer. Thus, a cm-order circuit of this CPW is difficult to fabricate in the 10 Gb/s module. This is because the silicon substrate has a large loss tangent (tan δ). On the other hand, the loss of the MSLs, where a ground plane shielded the high loss silicon substrate, could be improved to 0.9 dB/cm at 10 GHz with 30 μm thick polyimide. These lower loss MSLs on a PLC-platform can be applied to module operation at 10 Gb/s. Furthermore they have the advantage that they are suitable for application to array device circuits or circuits in a module where several devices are integrated because unlike CPWs the ground planes are not divided by signal lines or DC bias lines. The structure of CPWs and MSLs on a PLC-platform with a Z_L of 50 Ω was also studied in detail