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1.
介绍了在系统级芯片(SoC)测试中所用到的基于扫描结构的全速测试。首先介绍了转换故障模型和路径延迟故障模型,以及测试时采用的具体的两种测试方法,然后总结了一些测试时要注意的事项。最后结合上述理论,对一款基于ARM的自主研发SoC芯片进行了实验,并用时序测试矢量对stuck-at故障进行模拟,减少了测试矢量的个数,节约了测试成本,得到了预期的结果。 相似文献
2.
On broad-side delay test 总被引:1,自引:0,他引:1
Savir J. Patil S. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》1994,2(3):368-372
A broad-side delay test is a form of a scan-based delay test, where the first vector of the pair is scanned into the chain, and the second vector of the pair is the combinational circuit's response to this first vector. This delay test form is called “broad-side” since the second vector of the delay test pair is provided in a broad-side fashion, namely through the logic. This paper concentrates on generation of broadside delay test vectors; shows the results of experiments conducted on the ISCAS sequential benchmarks, and discusses some concerns of the broad-side delay test strategy 相似文献
3.
We present an approach to prevent overtesting in scan-based delay test. The test data is transformed with respect to functional constraints while simultaneously keeping as many positions as possible unspecified in order to facilitate test compression. The method is independent of the employed delay fault model, ATPG algorithm and test compression technique, and it is easy to integrate into an existing flow. Experimental results emphasize the severity of overtesting in scan-based delay test. Influence of different functional constraints on the amount of the required test data and the compression efficiency is investigated. To the best of our knowledge, this is the first systematic study on the relationship between overtesting prevention and test compression. 相似文献
4.
Low-power scan design using first-level supply gating 总被引:5,自引:0,他引:5
Bhunia S. Mahmoodi H. Ghosh D. Mukhopadhyay S. Roy K. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2005,13(3):384-395
Reduction in test power is important to improve battery lifetime in portable electronic devices employing periodic self-test, to increase reliability of testing, and to reduce test cost. In scan-based testing, a significant fraction of total test power is dissipated in the combinational block. In this paper, we present a novel circuit technique to virtually eliminate test power dissipation in combinational logic by masking signal transitions at the logic inputs during scan shifting. We implement the masking effect by inserting an extra supply gating transistor in the supply to ground path for the first-level gates at the outputs of the scan flip-flops. The supply gating transistor is turned off in the scan-in mode, essentially gating the supply. Adding an extra transistor in only one logic level renders significant advantages with respect to area, delay, and power overhead compared to existing methods, which use gating logic at the output of scan flip-flops. Moreover, the proposed gating technique allows a reduction in leakage power by input vector control during scan shifting. Simulation results on ISCAS89 benchmarks show an average improvement of 62% in area overhead, 101% in power overhead (in normal mode), and 94% in delay overhead, compared to the lowest cost existing method. 相似文献
5.
Myung-Hoon Yang Yongjoon Kim Sunghoon Chun Sungho Kang 《Journal of Electronic Testing》2008,24(6):591-595
Power consumption for test vectors is a major problem in SOC testing using BIST. A new low power testing methodology to reduce
the peak power and average power associated with scan-based designs in the deterministic BIST is proposed. This new method
utilizes an auxiliary LFSR to reduce the amount of the switching activity in the deterministic BIST. Excessive transition
detector (ETD) monitors the number of transitions in the test pattern generated by LFSR and the low transition pattern is
generated for excessive transition region using an auxiliary LFSR. Experimental results for the larger ISCAS 89 benchmarks
show that reduced peak power and average power can indeed be achieved with little hardware overhead compared to previous schemes. 相似文献
6.
7.
Growing test data volume and excessive test application time are two serious concerns in scan-based testing for SoCs. This paper presents an efficient test-independent compression technique based on block merging and eight coding (BM-8C) to reduce the test data volume and test application time. Test compression is achieved by encoding the merged blocks after merging consecutive compatible blocks with exact eight codewords. The proposed scheme compresses the pre-computed test data without requiring any structural information of the circuit under test. Therefore, it is applicable for IP cores in SoCs. Experimental results demonstrate that the BM-8C technique can achieve an average compression ratio up to 68.14 % with significant low test application time. 相似文献
8.
Pomeranz I. Reddy S.M. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2004,12(7):780-788
Functional test sequences were shown to detect unique defects in VLSI circuits. This is thought to be due to the fact that they are applied at-speed. However, functional test sequences do not achieve complete stuck-at fault coverage. Therefore, scan-based stuck-at tests, as well as other types of tests, are typically also applied. This increases the amount of test resources required for test application. We describe a procedure for inserting (limited) scan operations into a functional sequence in order to improve its stuck-at fault coverage, thus reducing or eliminating the need for separate scan-based stuck-at tests. Between scan operations, the functional test sequence can still be applied at-speed; however, a higher stuck-at fault coverage is achieved. 相似文献
9.
This paper proposes a novel method to reduce the peak power of multiple scan chain based circuits during testing. The peak periodicity and the peak width of the power waveforms for scan-based circuits are analyzed. An interleaving scan architecture based on adding delay buffers among the scan chains is developed which can significantly reduce the peak power. This method can be efficiently integrated with a recently proposed broadcast multiple scan architecture due to the sharing of scan patterns. The effects of the interleaving scan technique applied to the conventional multiple scan and the broadcast multiple scan with 10 scan chains are investigated. Up to 51% peak power reduction can be achieved when the data output of a scan cell is affected by the scan path during scan. When the data output is disabled during scan, up to 76% of peak-power reduction is observed. 相似文献
10.
11.
To obtain satisfactory fault coverage for testing a logic circuit, linear feedback shift registers (LFSRs) have been used to generate not only the pseudorandom, but also the deterministic patterns in the scan-based built-in self-test environment. However, like other scan-based methods, the LFSR based pattern generation schemes take a long test application time to feed deterministic patterns from the LFSR into a scan chain. In this paper we derive a general relationship between the bits in the scan chain and the states of the LFSR and show that any bit to be generated by an LFSR in any future clock cycle can be pre-generated by a linear function of the current LFSR state. With this relationship, we can divide a scan chain into multiple sub-chains and use one LFSR-based multiple sequence generator to simultaneously generate all the subsequences required by the sub-chains, hence can greatly reduce the test application time for deterministic patterns. Moreover, due to the scan time reduction, test power wasted during the scan operation can also be significantly reduced. 相似文献
12.
Test data compression using alternating variable run-length code 总被引:1,自引:0,他引:1
Bo YeAuthor Vitae Qian ZhaoAuthor VitaeDuo ZhouAuthor Vitae Xiaohua WangAuthor VitaeMin LuoAuthor Vitae 《Integration, the VLSI Journal》2011,44(2):103-110
This paper presents a unified test data compression approach, which simultaneously reduces test data volume, scan power consumption and test application time for a system-on-a-chip (SoC). The proposed approach is based on the use of alternating variable run-length (AVR) codes for test data compression. A formal analysis of scan power consumption and test application time is presented. The analysis showed that a careful mapping of the don’t-cares in pre-computed test sets to 1s and 0s led to significant savings in peak and average power consumption, without requiring slower scan clocks. The proposed technique also reduced testing time compared to a conventional scan-based scheme. The alternating variable run-length codes can efficiently compress the data streams that are composed of both runs 0s and 1s. The decompression architecture was also presented in this paper. Experimental results for ISCAS'89 benchmark circuits and a production circuit showed that the proposed approach greatly reduced test data volume and scan power consumption for all cases. 相似文献
13.
Bahukudumbi S. Chakrabarty K. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2007,15(10):1144-1154
Product cost is a major driver in the consumer electronics market, which is characterized by low profit margins and the use of core-based system-on-chip (SoC) designs. Packaging has been recognized as a significant contributor to the product cost for such SoCs. To reduce packaging cost and the test cost for packaged chips, wafer-level testing (wafer sort) is used in the semiconductor industry to screen defective dies. However, since test time is a major practical constraint for wafer sort, even more so than for package test, not all the scan-based digital tests can be applied to the die under test. We present an optimal test-length selection technique for wafer-level testing of core-based SoCs. This technique, which is based on a combination of statistical yield modeling and integer linear programming, allows us to determine the number of patterns to use for each embedded core during wafer sort such that the probability of screening defective dies is maximized for a given upper limit on the SoC test time. We also present a heuristic method to handle large next-generation SoC designs. Simulation results are presented for five of the ITC'02 SoC Test benchmarks, and the optimal test-length selection approach is compared with the heuristic method. 相似文献
14.
Sybille Hellebrand Hua-Guo Liang Hans-Joachim Wunderlich 《Journal of Electronic Testing》2001,17(3-4):341-349
In this paper a new scheme for deterministic and mixed mode scan-based BIST is presented. It relies on a new type of test pattern generator which resembles a programmable Johnson counter and is called folding counter. Both the theoretical background and practical algorithms are presented to characterize a set of deterministic test cubes by a reasonably small number of seeds for a folding counter. Combined with classical approaches for test width compression and with pseudo-random pattern generation these new techniques provide an efficient and flexible solution for scan-based BIST. Experimental results show that the proposed scheme outperforms previously published approaches based on the reseeding of LFSRs or Johnson counters. 相似文献
15.
《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2009,17(12):1730-1741
16.
17.
LPTest: a Flexible Low-Power Test Pattern Generator 总被引:1,自引:1,他引:0
This paper presents a low power test pattern generator, LPTest, that minimizes the peak power consumption during the shift
and capture cycles for scan-based stuck-at and transition fault testing. LPTest incorporates both power-aware ATPG and low-power
X-filling techniques to achieve higher power reduction. Its enabling technique is a power estimation method which assesses
the lower-bounds of the shift-in, shift-out, and capture powers of a partially specified test pattern. The lower-bound estimation
method is utilized in LPTest’s ATPG engine, dynamic compaction, and X-filling. LPTest has been validated using ISCAS89 benchmark circuits. When considering all cycles, LPTest achieves better
than 22% peak WSA (weighted switching activity) reduction for stuck-at and transition faults compared to a commercial ATPG
with high merge ratio and random-fill options. Meanwhile, the average power reduction is better than 43%. When only capture
power is of concern, LPTest attains more than 46% WSA reduction for stuck-at and transitions. 相似文献
18.
Delay fault testing using a scan design facilitating two-pattern testing, called Chiba scan testing, requires a long test
application time (TAT) compared with well-known delay fault testing. This paper presents an improved Chiba scan testing with
short TAT by providing a test compaction. In addition, it presents a test generation for the Chiba scan testing improved by
the proposed compaction. Evaluation shows that, for robust path delay fault testing on ISCAS89/ ADDENDUM benchmark circuits,
the TAT of Chiba scan testing with the proposed compaction is, on average, 47% and 21% shorter than that of Chiba scan testing
without test compaction and that of enhanced scan testing with the conventional test compaction, respectively. In addition,
in many cases, the fault coverage of the proposed testing is higher than that of launch-off-capture (LoC) and launch-off-shift
(LoS) testing with the same TAT. 相似文献
19.
3D integration of ICs is an emerging technology where multiple silicon dies are stacked vertically. The manufacturing itself
is based on wafer-to-wafer bonding, die-to-wafer bonding or die-to-die bonding. Wafer-to-wafer bonding has the lowest yield
as a good die may be stacked against a bad die, resulting in a wasted good die. Thus the latter two options are preferred
to keep yield high and manufacturing costs low. However, these methods require dies to be tested separately before they are
stacked. A problem with testing dies separately is that the clock network of a prebond die may be incomplete before stacking.
In this paper we present a solution to address this problem. The solution is based on on-die Delay Lock Loop (DLL) implementations
that are only activated during testing prebond unstacked dies to synchronize disconnected clock regions. A problem with using
DLLs in testing is that they cannot be turned on or off within a single cycle. Since scan-based testing requires that test
patterns be scanned in at a slow clock frequency before fast capture clocks are applied, On-Product Clock Generation (OPCG)
must be used. The proposed solution addresses the above problems and allows a prebond with an incomplete clock network to
be tested with low skew. 相似文献
20.
《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2007,15(5):493-494
The five papers in this special section focus on autonomous silicon validation and testing of microprocessors and microprocessor-based systems. The papers cover several important aspects of the technical area: from first silicon validation and debug to manufacturing and production testing, including both software-based and hardware-based techniques and design-for-test methods that range from pure functional instruction-based to structural scan-based tests. The scope of the papers extends from embedded uniprocessors to multicore microprocessors. 相似文献