Joint Synchronization and Decoding for Photon-Limited Optical Channels: Code Design and Complexity Reduction

The problem of joint symbol synchronization and decoding of pulse position modulation (PPM) sequences in the deep-space photon-limited optical channel is considered. A new joint synchronizer and decoder for PPM on this channel is presented along with the design of codes having both good error control and synchronization properties for use with PPM signaling on this channel. The new approach presented in this paper provides a significant reduction in synchronizer/decoder complexity when compared to previous methods for joint synchronization and decoding.     

一种高速Viterbi译码器的设计与实现

Viterbi算法是卷积码的最优译码算法.设计并实现了一种高速(3,1,7)Viterbi译码器,该译码器由分支度量单元(BMU)、加比选单元(ACSU)、幸存路径存储单元(SMU)、控制单元(CU)组成.在StratixⅡ FPGA上实现、验证了该Viterbi译码器.验证结果表明,该译码器数据吞吐率达到231Mbit/s,在加性高斯白噪声(AWGN)信道下的误码率十分接近理论仿真值.与同类型Viterbi译码器比较,该译码器具有高速、硬件实现代价低的特点.     

Design Methodology for a DVB Satellite Receiver ASIC

This contribution describes design methodology and implementation of a single-chip timing and carrier synchronizer and channel decoder for digital video broadcasting over satellite (DVB-S). The device consists of an A /D converter with AGC, timing and carrier synchronizer with matched filter, Viterbi decoder including node synchronization, byte and frame synchronizer, convolutional de-interleaver, Reed Solomon decoder, and a descrambler.The system was designed in accordance with the DVB specifications. It is able to perform Viterbi decoding at data rates up to 56 Mbit /s and to sample the analog input values with up to 88 MHz. The chip allows automatic acquisition of the convolutional code rate and the position of the puncturing mask. The symbol synchronization is performed fully digitally by means of interpolation and controlled decimation. Hence, no external analog clock recovery circuit is needed.For algorithm design, system performance evaluation, co-verification of the building blocks, and functional hardware verification an advanced design methodology and the corresponding tool framework are presented which guarantee both short design time and highly reliable results. The chip has been fabricated in a 0.5 µm CMOS technology with three metal layers. A die photograph is included.     

An effective simplifying scheme for Viterbi decoder

A Viterbi decoding algorithm with a scarce-state transition-type circuit configuration, namely the probability selecting states (PSS) mode decoder, is presented. The algorithm has reduced complexity compared to a conventional Viterbi decoder. It is shown that this method has three advantages over the general Viterbi algorithm: it is suitable to the quick look-in code, it applies the optimum decoding in a PSS-type decoder, and it makes full use of the likelihood concentration property. The bit-error-rate (BER) performance of a r=1/2, k=7 (147,135) code and PSS-type Viterbi decoder approximates the optimum performance of the standard Viterbi decoder and reduces the hardware of the conventional Viterbi decoder to about half     

An artificial neural net Viterbi decoder

The Viterbi algorithm is a maximum likelihood means for decoding convolutional codes and has thus played an important role in applications ranging from satellite communications to cellular telephony. In the past, Viterbi decoders have usually been implemented using digital circuits. The speed of these digital decoders is directly related to the amount of parallelism in the design. As the constraint length of the code increases, parallelism becomes problematic due to the complexity of the decoder. In this paper an artificial neural network (ANN) Viterbi decoder is presented. The ANN decoder is significantly faster than comparable digital-only designs due to its fully parallel architecture. The fully parallel structure is obtained by implementing most of the Viterbi algorithm using analog neurons as opposed to digital circuits. Several modifications to the ANN decoder are considered, including an analog/digital hybrid design that results in an extremely fast and efficient decoder. The ANN decoder requires one-sixth the number of transistors required by the digital decoder. The connection weights of the ANN decoder are either +1 or -1, so weight considerations in the implementation are eliminated. This, together with the design's modularity and local connectivity, makes the ANN Viterbi decoder a natural fit for VLSI implementation. Simulation results are provided to show that the performance of the ANN decoder matches that of an ideal Viterbi decoder     

An Area-Effective Cell-Based Channel Decoder LSI For a Digital Satellite TV Broadcasting

A new channel decoder LSI, which will be used in digital satellite TV broadcasting Set-Top Boxes, has been designed. This LSI's functions include AD/DA conversion, QPSK demodulating, Viterbi decoding, frame synchronization, convolutional deinterleaving, Reed-Solomon (RS) decoding, and descrambling. We use a new method for Viterbi Decoding called the Tracking Survivor State Information (TSSI) method, which not only reduces power consumption, but also solves the problem of increasing memory size. To reduce the size of RS decoder circuit, we used a three-stage-pipeline structure as well as designed a new architecture to realize Euclid's algorithm. This device has been fabricated in a 0.35 µm 3-metal CMOS standard cell-based process and is composed of 670 K transistors. In this paper, we describe the TSSI method of the Viterbi Decoder and the Reed-Solomon Decoder's new 3-stage pipeline architecture.     

Performance Bounds for Convolutional Codes with Digital Viterbi Decoders in Gaussian Noise

With digital implementations of the Viterbi decoding algorithm for convolutional codes, soft quantization is preferred over hard quantization because it generally yields superior performance. Since the decoder needs to know the signal energy and channel noise variance with soft quantization, inaccurate information can result in a mismatch between the channel and decoder. Bounds which are tight for high signal-to-noise ratios are obtained on the bit error probability using the generating function approach. Automatic gain control level inaccuracies, imperfect carrier phase, symbol timing synchronization error, and path metric digitization are discussed in the context of a mismatch between the channel and decoder.     

数字流水Viterbi译码器的VLSI设计

本文介绍了高速数字流水Ｖｉｔｅｒｂｉ译码器的ＶＬＳＩ设计。在符号４值系统的基础上，给出Ｖｉｔｅｒｂｉ算法的新的功能分解公式，并介绍了用于译码器实现的两个重要的快速运算部件ＡＤＤ和ＭＡＸ的原理及其现场可编程（序）门阵列（ＦＰＧＡ）实现。文中详细讨论了译码器的ＶＬＳＩ结构、设计和性能分析。本文给出的Ｖｉｔｅｒｂｉ译码器可塑性强，并具有高度的并行性和很高的数据吞吐率。     

一种高速Viterbi译码器的优化设计及Verilog实现

文章设计了一种高速Viterbi译码器，该设计基于卷积码编码及其Viterbi译码原理，完成了Viterhi译码的核心单元算法的优化，并采用Verilog语言编程实现了卷积码编码器和译码器。仿真和综合的结果表明本文设计的译码器速率达50Mbit／s，同时译码器的电路规模也通过算法得到了优化。     

DVB-T中Viterbi译码器的设计及FPGA实现

Viterbi作为一种最大似然译码算法广泛应用在数字地面视频广播中,但由于其较高算法复杂程度,对实现高速低功耗时延小且逻辑结构简单的译码器带来了挑战。首先为了实现高速的Vit-erbi译码器,ACSU采用全并行结构,度量值的溢出控制采用取模归一化方法,并简化比较器。其次为了实现低功耗时延小且控制逻辑简单的Viterbi译码器,SMU采用改进的前向追溯结构,只用一组单口的RAM实现译码输出。该译码器在Xilinx Virtex6上实现并验证通过,并具有较好的译码性能。     

一种基于FPGA的Viterbi译码器的研究与设计

针对通信系统中传统维特比(Viterbi)译码器结构复杂、译码延时大、资源消耗大的问题,提出了一种新的基于FPGA的Viterbi译码器设计。结合(2,1,7)卷积编码器和Viterbi译码器的工作原理,设计出译码器的核心组成模块,具体采用3比特软判决译码,用曼哈顿距离计算分支度量,32个碟型加比选子单元并行运算,完成幸存路径和幸存信息的计算。幸存路径管理模块采用Viterbi截短译码算法,回溯操作分成写数据、回溯读和译码读,以改进的流水线进行并行译码操作,译码延时和储存空间分别降低至和。     

Viterbi-based algorithm for side-match vector quantization overnoisy channels

Side-match vector quantization is a finite-state technique for image coding. This research shows that the side-match vector quantization is an error-propagating code and it is similar to a catastrophic convolutional code. Here, we propose a Viterbi-based algorithm to solve this problem. Various noise detection algorithms are integrated into the Viterbi algorithm (to yield the Viterbi-based algorithm) for a much better performance. According to the simulation of a binary symmetric channel with random bit-error rate (BER) 0.1%-0.01%, the Viterbi-based algorithm provides 2.8-9.6 dB and 2.3-8.4 dB gain compared with the conventional side-match vector quantization decoder and the Viterbi decoder, respectively. In addition, the proposed algorithm requires much fewer computations than the Viterbi algorithm     

Limited search trellis decoding of convolutional codes

The least storage and node computation required by a breadth-first tree or trellis decoder that corrects t errors over the binary symmetric channels is calculated. Breadth-first decoders work with code paths of the same length, without backtracking. The Viterbi algorithm is an exhaustive trellis decoder of this type; other schemes look at a subset of the tree or trellis paths. For random tree codes, theorems about the asymptotic number of paths required and their depth are proved. For concrete convolutional codes, the worst case storage for t error sequences is measured. In both cases the optimal decoder storage has the same simple dependence on t. The M algorithm and algorithms proposed by G.J. Foschini (ibid., vol.IT-23, p.605-9, Sept. 1977) and by S.J. Simmons (PhD. diss., Queens Univ., Kingston, Ont., Canada) are optimal, or nearly so; they are all far more efficient than the Viterbi algorithm     

一种M-FSK信号的能量度量Viterbi软译码算法性能分析

Viterbi译码算法广泛应用于无线数字通信系统,一般采用比特对数似然信息(LLR)作为译码器的输入。针对M-FSK信号,该文提出一种采用信号解调得到的M维能量信息,直接作为译码器分支度量值,并给出了相应的Viterbi译码算法。在加性高斯白噪声(AWGN)和瑞利(Rayleigh)衰落信道下对所提算法的BER性能进行了理论推导,得到了闭合表达式。通过仿真验证了理论推导的正确性,与常规Viterbi算法相比,所提算法避免了比特LLR和分支度量值的计算,降低了算法复杂度和减少了信息损失,提高了M-FSK信号软解调Viterbi译码算法的BER性能,是一种更适用于工程实现的M-FSK信号的Viterbi译码算法。     

Adaptive Viterbi algorithm with ARQ for bounded complexity decoding

Adaptive bounded computational and memory requirements for a Viterbi decoder can be achieved using an error trapping Viterbi decoder algorithm initially develop for hybrid automatic repeat request (ARQ) implementations. Partial path metrics and a sliding window are used to eliminate unreliable paths in the decoder trellis thus reducing the computational and memory requirements. An ARQ is issued if all paths are eliminated. The algorithm is adaptive allowing the receiver to dynamically allocate memory and processing, to improve reliability or received packets, or to reject packets with lower reliability to avoid buffer overruns. The result is the ability to trade off resources versus delay and throughput.     

Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition

In this paper, a low-power Viterbi decoder design based on scarce state transition (SST) is presented. A low complexity algorithm based on a limited search algorithm, which reduces the average number of the add-compare-select computation of the Viterbi algorithm, is proposed and seamlessly integrated with the SST-based decoder. The new decoding scheme has low overhead and facilitates low-power implementation for high throughput applications. We also propose an uneven-partitioned memory architecture for the trace-back survivor memory unit to reduce the overall memory access power. The new Viterbi decoder is designed and implemented in TSMC 0.18-mum CMOS process. Simulation results show that power consumption is reduced by up to 80% for high throughput wireless systems such as Multiband-OFDM Ultra-wideband applications.     

基于级联码的信道编译码设计与FPGA实现

介绍了RS(255,223)码级联卷积(4,3,3)码编译码器的实现,对于编码和译码端不同的结构特点.分别采用并行和串行结构实现.其中RS译码采用欧几里德算法,卷积译码采用维特比算法.同时给出了该编译码器的FPGA实现,按照自上而下的设计流程,在保证速度的同时最大限度地减少了资源占用.     

基于FPGA的高速Viterbi译码器设计与实现

Viterbi算法是卷积码最常用的译码算法,在卷积码约束长度较大,译码时延要求较高的场合,如何实现低硬件复杂度的Viterbi译码器成为新的课题。本文提出新颖的Viterbi路径权重算法、双蝶形译码单元结构、高效的状态度量存储器等技术,使Viterbi算法充分和FPGA灵活原片内存储和逻辑单元配置方法相结合,发挥出最佳效率。用本算法在32MHz时钟下实现的256状态的Viterbi译码器译码速率可达400Kbps以上,且仅占用很小的硬件资源,可以方便地和Furbo译码单元等集成在单片FPGA,形成单片信道译码单元。     

Joint Erasure Marking and List Viterbi Algorithm for Decoding in Unknown Non-Gaussian Noise

In many real-world communication systems, the channel noise is non-Gaussian due to the presence of impulsive noise as well as the background Gaussian noise. In such situations, the conventional Euclidean distance based decoder may suffer from the problem of severe metric mismatch. To overcome the problem, we recently proposed the joint erasure marking and Viterbi algorithm (JEVA) as a robust trellis decoder that does not require an estimate of the impulsive noise distribution. In this work, two ways to further improve JEVA are presented for systems with an error detecting code. Specifically, the JEVA is integrated with the list Viterbi algorithm (LVA) to form the two-dimensional joint erasure marking and list Viterbi algorithm (JELVA) and the switched JELVA, respectively. By combining the respective strengths of the JEVA and the LVA, the integrated decoding schemes are able to achieve significant performance gains over the original JEVA and achieve a wide range of performance-complexity-delay tradeoffs.     

Viterbi译码蝶型算法的实现及性能分析

研究在TD-SCDMA系统中,一种有利于软件实现的Viterbi译码蝶型算法蝶实现方法,并与MATLAB中Viterbi译码库函数进行仿真比较。根据仿真结果,分析蝶型实现方法的性能,论证它的可行性。