基于FPGA的等占空比任意整数分频器的设计

给出了一种基于FPGA的等占空比任意整数分频电路的设计方法。首先简要介绍了FPGA器件的特点和应用范围，接着讨论了一些常见整数分频的方法，而本文运用一种新的可控分频器设计方法——脉冲周期剔除法，主要是对半周期进行计数，配合时钟反相电路，可以实现占空比50％的任意整数分频，分频系数由控制端给定。本设计在Max＋PlusⅡ开发软件下，利用VHDL硬件描述语言和原理图输入方式，可以方便地实现分频器电路的设计。在文中给出了N=3时分频电路设计，并对电路进行了仿真和测试，实验结果符合设计要求。     

基于FPGA可配置任意整数半整数50%占空比时钟分频的实现

基于FPGA,采用FPGA内部相移时钟,设计了一种可配置任意整数半整数50%占空比的时钟分频电路。以环形触发器电路为主要分频电路,根据各相移时钟的相位关系调整输出时钟占空比。设计结合时钟的相位关系与分频时钟周期的关键点,以多输入差分锁存结构完成输出时钟的占空比调整,最终实现整数、半整数分频。最后对电路进行了仿真验证。     

基于CPLD的任意整数半整数分频器设计

在电子系统的设计中经常需要对输入时钟信号进行分频,以满足不同系统设计模块的需要。分频方法很多,但设计方法简单且具有一定通用性的较少,而在基于CPLD(复杂可编程逻辑器件)的系统设计中,利用时钟的上升沿和下降沿控制计数器产生两路输出波形,对这两路波形进行逻辑或操作,进而可简易实现对输入时钟信号进行任意整数和半整数分频,其中整数分频为等占空比,半整数分频的高低电平只差半个输入时钟周期。     

一种由多级2/3分频单元级联而成的通道可编程分频器设计

介绍了一种由多级2/3分频单元级联的可编程分频器,可应用于扇出缓冲器的通道中.分频器采用0.18μm BiCMOS工艺实现.分频器的电源电压为3.3V,分频比支持1、3、5以及4～4 094的所有偶数分频,且所有分频输出信号的占空比为50％.     

CMOS高性能奇数分频器的设计

本论文提出了一种占空比为50％奇数分频器的实现方法,基于0.25μmCMOS工艺参数,使用Cadence Spectre对分频器进行了仿真.当分频比为5,电源电压为2.5V,工作温度为27℃,分频器的输入频率为650MHz时,输出信号的占空比可达49.94%.     

一种新型小数/整数分频器

提出了一种新型小数/整数分频器电路结构,详细分析了该小数/整数分频器的工作原理.该分频器与传统分频器相比,具有控制简单、电路复杂度低、工作频率高等特点.设计基于TSMC 0.25 μm 2.5 V 1P5M CMOS工艺,最高工作频率为4.5 GHz,功耗为10.37 mA,并可以实现128到264之间小数、整数分频.后仿真结果表明,该分频器对频率合成器相位噪声特性有很好的改善作用.     

基于FPGA的任意数值分频器的设计

介绍了基于FPGA的任意分频系数的分频器的设计,该分频器能实现分频系数和占空比均可以调节的3类分频：整数分频、小数分频和分数分频。所有分频均通过VHDL语言进行了编译并且给出了仿真图。本设计中的分频器没有竞争冒险,可移植性强,占用的FPGA资源少。本设计在Altera公司的CycloneⅡ系列EP2C35型FPGA芯片中完全可实现,结果表明设计是正确和可行的。由于分频器应用非常广泛,故本设计具有很强的实用价值。     

分频系数为半整数分频器的CPLD设计

以分频系数为半整数分频器的设计为例,介绍了在ＭＡＸ＋ＰＬＵＳⅡ开发平台下,利用ＶＨＤＬ硬件描述语言和原理图输入方式,设计数字逻辑电路的过程。     

一种基于FPGA的任意分频器设计与实现

根据直接数字频率合成器(DDS)工作原理,介绍了一种基于FPGA的任意分频系数的分频器的设计,该分频器能实现分频系数和占空比。通过Verilog语言进行了编译并且给出了仿真图。该设计中的分频器没有竞争冒险,可移植性强,占用的FPGA资源少。本设计在友晶公司DE0的开发板上可完全实现,结果表明设计是正确和可行的。分频器在FPGA开发设计中应用非常广泛,故本设计具有很强的实用价值。     

基于FPGA的多种分频设计与实现

简要介绍了FPGA设计中各种分频器的设计方法,给出了分别利用Veriog硬件描述语言和原理图对整数分频、半整数分频等多种分频方式进行设计的方法,同时给出了通过QuartusⅡ5.0开发平台并使用Altera公司的FPGA进行实现的具体方案.     

A wide division-ratio range programmable frequency divider with driving-capability improved

This letter presents an improved architecture of wide division ratio range programmable frequency divider with driving-capability improved. The proposed architecture combines the traditional 2/3 cells and the revised ones to retain the high speed feature and broaden the output duty-cycle. Only less OR and AND gates are added to select the proper output. All of the added circuits are operating at the lower frequency. Thus it enhances the divider’s driving-capability with almost adding no power consumption. This improvement makes it applicable to drive various clocked circuits, which need different frequencies. The presented equation can be used to predict the output duty-cycle with the expected division ratio accurately. Test results show that the output duty-cycle is between 33 and 66%, which corroborate the calculations.     

Wide division ratio range programmable frequency divider with close-to-50% output duty-cycle

A novel wide division ratio (DR) range programmable frequency divider is presented in this article, which is based on the proposed divide-by-2/3/4 cell. The divider's output is buffered by a divide-by-2 cell; hence, it can achieve the close-to-50% output duty-cycle. The DRs can be set via the convenient provisions of binary bits. When the DR is even, the output duty-cycle is exactly 50%. If the DR is odd, the output duty-cycle is k/(2?k?+?1), where k is a natural number, therefore, it becomes close-to-50% with an increasing k. A divider with eight DR control bits, which can realise the DRs from 8 to 511, is implemented in standard 0.18?µm complementary metal-oxide semiconductor technology, the die area is 0.02?mm². The measured results show that the divider can obtain 44.4–50% output duty-cycle which corroborates with the calculation.     

A power-efficient 14.8-GHz CMOS programmable frequency divider with quadrature outputs in 40-nm CMOS process

This paper presents a power-efficient CMOS frequency divider (FD) with wide-band programmable division ratio and quadrature outputs for high-speed data transmission applications. The proposed FD consists of a power-efficient programmable divider (PD), a complementary volt-age-to-time converter based duty-cycle correction circuit, and a compact quadrature divider (QD). In the chain of PD, a sense-amplifier based dynamic flip-flop is proposed for 2/3 divider cell to achieve high-speed operation with significantly reduced power consumption. In addition, a simple but effective QD based on two pseudo-differential voltage-controlled tri-state inverters, is beneficial for generating precise quadrature output signals. Measurement results in 40-nm CMOS process show that the proposed FD achieves a wide division range from 16 to 254 and operates up to 14.8 GHz while consuming the power of 540.6 μW at 1.1-V supply, and occupying the active area of 0.00267 mm² (114.6 μm × 23.3 μm).     

A 50 GHz Divide-by-4 Injection Lock Frequency Divider Using Matching Method

A fully integrated divide-by-4 frequency divider has been designed, fabricated, and measured in the standard bulk 0.18-m complementary metal-oxide semiconductor (CMOS) technology. A newly proposed matching technique was used to eliminate the unwanted low frequency mixing terms at the common node of the circuit so as to achieve a high division ratio of 4. The frequency divider exhibits a measured operation range of 5 GHz from 45.9 to 50.9 GHz. It consumes a dc power of 7.56 mW at a 1.2 V supply in the steady state operation. The phase noise of the free running divider is 88.51 dBc/Hz at 1 MHz offset and the locked divider is 110.74 dBc/Hz at 1 MHz offset. The chip size is only 0.35 mm 0.5 mm including the pad frame. To our knowledge, this divider has the highest operation frequency to date among the high division ratio injection-lock type frequency dividers in commercial CMOS 0.18-m process.     

A Multigigahertz Multimodulus Frequency Divider in 90-nm CMOS

This brief presents a multimodulus frequency divider with division ratio between 64 and 127 fabricated in 90-nm CMOS. By using a load-switching technique, high operating frequency, and low power static divider was achieved. The divider consists of six 2/3 divider stages. The maximum operating frequency is 4.7 GHz with current consumption 2.3 mA at low voltage supply 1.2 V and rms cycle-to-cycle jitter lower than 1 ps     

应用于26 GHz-41 GHz频率综合器的高速可编程分频器的设计

毫米波频率综合器中的重要模块之一高速可编程多模分频器,它主要用于对VCO的输出信号进行分频从而获得稳定的本振信号,它的性能影响整个毫米波频率综合器性能。本文设计的一种高速、低功耗、分频比可变的分频器具有非常重要的意义[1]。根据26 GHz-41 GHz硅基锁相环频率综合器的系统指标,本文基于TSMC 45nm CMOS工艺,设计实现了一种高速可编程分频器。本文采用注入锁定结构分频结构实现高速预分频,该结构可以实现在0 d Bm的输入功率下实现25 GHz-48 GHz的分频范围、最低功耗为:2.6 m W。基于脉冲吞咽计数器的可编程分频器由8/9双模分频器和可编程脉冲吞咽计数器组成。其中8/9双模分频器由同步4/5分频器和异步二分频构成,工作频率范围10 GHz-27 GHz,最低输入幅度为:300 m V,最低功耗为:1.6 m V。可编程吞咽计数器采用改进型带置数功能的TSPC D触发器,该可编程分频器的最大工作范围:25 GHz;最小功耗为:363μW。本文设计的高速可编程多模分频器,可以实现32-2 062的分频比;当工作于28 GHz时,相位噪声小于-159 dBc/Hz。动态功耗为5.2 m W。     

应用于频率合成器的宽分频比CMOS可编程分频器设计

提出一种应用于射频频率合成器的宽分频比可编程分频器设计。该分频器采用脉冲吞吐结构,可编程计数器和吞脉冲计数器都采用改进的CMOS源极耦合（SCL）逻辑结构的模拟电路实现,相对于采用数字电路实现降低了电路的噪声和减少了版图面积。同时,对可编程分频器中的检测和置数逻辑做了改进,提高分频器的工作频率及稳定性。最后,采用TSMC的0.13μm CMOS工艺,利用Cadence Spectre工具进行仿真,在4.5 GHz频率下,该分频器可实现200515的分频比,整个功耗不超过19 mW,版图面积为106μm×187μm。     

A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer

A 1-Gb/s/pin 512-Mb DDRII SDRAM has been developed using a digital delay-locked loop (DLL) and a slew-rate-controlled output buffer. The digital DLL has a frequency divider for DLL input, performs at an operating frequency of up to 500 MHz at 1.6 V, and provides internal clocking with 50% duty-cycle correction. The DLL has a current-mirror-type interpolator, which enables a resolution as high as 14 ps, needs no standby current, and can operate at voltages as low as 0.8 V. The slew-rate impedance-controlled output buffer circuit reduces the output skew from 107 to 10 ps. This SDRAM was tested using a 0.13-/spl mu/m 126.5-mm/sup 2/ 512-Mb chip.     

A Novel (N + 1/2) Pulse Swallow Programmable Divider for the Prescaler PLL Frequency Synthesizer

In this paper, we propose a new speedup method of frequency switching time of the prescaler PLL frequency synthesizer using (N + \tfrac12)(N + \tfrac{1}{2}) pulse swallow programmable divider. The (N + \tfrac12)(N + \tfrac{1}{2}) pulse swallow programmable divider can set half the division ratio (\tfracD2)(\tfrac{D}{2}) in comparison with the desired division ratio D. In the improved prescaler method, since the total division ratio including (\tfrac12)(\tfrac{1}{2}) fixed prescaler becomes desired division ratio D, the reference frequency which is two times bigger than that of the conventional prescaler method can be used. Therefore, the loop gain, the natural angular frequency and the damping factor are increased, and the frequency switching time can be speeded up. By the experimental results, it is observed that the frequency switching time of the improved prescaler method is two times faster than that of the conventional prescaler method.