Self-tuning adaptive delay sequential elements

Random manufacturing variations and changes in operating conditions can alter the relative timing of data and clock signals and cause timing violations. Increasing relative magnitude of manufacturing variations and accommodating a wide range of operating conditions necessitate large design margins and decrease circuit performance. In-circuit tuning of clock latencies allows recovering some of the performance loss. In this paper, we introduce self-tuning adaptive-delay sequential elements (SASEs) that use PMOS floating gates to tune clock latencies of individual flip-flops. SASEs are capable of concurrent, in-circuit optimization of clock latencies under varying operating conditions. We use examples of implicit and explicit pulsed flip-flops to present SASEs operations and tuning methods. Our experiments with fabricated prototypes show that SASEs can tune their clock latencies with picosecond resolution over one half of the clock period. Our experiments also show that SASEs’ sensitivities are comparable to non-adaptive flip-flops and do not pose any practical limitations. We also present a tuning procedure for pipeline circuits that tunes SASEs’ clock latencies to maximize performance.     

High-accuracy and low signal distortion on-chip auto-calibrating architecture for continuous-time filters

A high-accuracy on-chip auto-calibrating architecture is presented to compensate the process and temperature parameter variations in high-linearity continuous-time filter. The on-chip auto-calibrating architecture consists of a clock generating circuit, a voltage comparator, a digital tuning engine, and an analog integrator with similar time-constants as the tuned filter. Discrete capacitor arrays are utilized to tune filter automatically for preserving a high linearity. A fourth-order RC filter for GNSS receivers is fabricated in 0.18 µm CMOS process to verify the performance of proposed tuning architecture. With adjustment, this filter achieves less than 5 % frequency uncertainty. The whole circuit consumes 5.2 mA under a 1.8 V supply and occupies a die area of 0.55 mm². Both the post-layout simulation and measured results indicate that the auto-calibrating architecture is a useful and adequate solution to compensate the errors caused by factors such as fabrication tolerances, changes in operating conditions, parasitic effects and aging.     

Sequential delay budgeting with interconnect prediction

Delay budgeting is a process of determining upper bounds for net delays to guide timing-driven placement. The existing approaches deal de facto only with combinational circuits. However, incorporating retiming into delay budgeting introduces more freedom to optimize sequential circuits. In this paper, we propose an approach for budgeting sequential circuits. We propose a new linear programming formulation for timing-aware sequential budgeting, which guarantees that the clock period constraints are met. We demonstrate the usefulness of our approach in the context of field-programmable gate arrays placement flow. We have performed two experiments. The first experiment compares sequential budgeting with traditional budgeting and retiming. The results show that the new placement flow reduces budget violations by 16% and improves timing by 9%. In the second experiment, we demonstrate methods of interconnect length prediction that are useful to estimate delay and to decide net weighting in sequential budgeting. We compare net delay predictions using traditional delay budgeting, the Donath's method, and mutual contraction. The results from this experiment show that sequential budgeting, using the new net weighting and predicted delays, can improve circuit speeds on average by 12.29%, compared to traditional timing-driven placement. The new net weighting method also performs better than a uniform weighting method.     

Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating

A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power clocking schemes are promising approaches for low-power design. We propose four novel energy recovery clocked flip-flops that enable energy recovery from the clock network, resulting in significant energy savings. The proposed flip-flops operate with a single-phase sinusoidal clock, which can be generated with high efficiency. In the TSMC 0.25-$mu$m CMOS technology, we implemented 1024 proposed energy recovery clocked flip-flops through an H-tree clock network driven by a resonant clock-generator to generate a sinusoidal clock. Simulation results show a power reduction of 90% on the clock-tree and total power savings of up to 83% as compared to the same implementation using the conventional square-wave clocking scheme and flip-flops. Using a sinusoidal clock signal for energy recovery prevents application of existing clock gating solutions. In this paper, we also propose clock gating solutions for energy recovery clocking. Applying our clock gating to the energy recovery clocked flip-flops reduces their power by more than 1000 $times$ in the idle mode with negligible power and delay overhead in the active mode. Finally, a test chip containing two pipelined multipliers one designed with conventional square wave clocked flip-flops and the other one with the proposed energy recovery clocked flip-flops is fabricated and measured. Based on measurement results, the energy recovery clocking scheme and flip-flops show a power reduction of 71% on the clock-tree and 39% on flip-flops, resulting in an overall power savings of 25% for the multiplier chip.      

An up-transition edge-triggered single-shot pulse generator with Josephson devices

The circuit is constructed with two cross-coupled DC flip-flops, resulting in a square-wave output signal without an external special clock signal. The circuit has been fabricated and its operating margin has been examined. An improved circuit for a wider operating margin is proposed and discussed.     

Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers

The thermal gradients existing in high-performance circuits may significantly affect their timing behavior, in particular, by increasing the skew of the clock net and/or altering hold/setup constraints, possibly causing the circuit to operate incorrectly. The knowledge of the spatial distribution of temperature can be used to properly design a clock network that is able to compensate such thermal non-uniformities. However, redesign of the clock network is effective only if temperature distribution is stationary, i.e., does not change over time. In this paper, we specifically address the problem of dynamically modifying the clock tree in such a way that it can compensate for temporal variations of temperature. This is achieved by exploiting the buffers that are inserted during the clock network generation, by transforming them into tunable delay elements. Temperature-induced delay variations are then compensated by applying the proper tuning to the tunable buffers, which is computed offline and stored in a tuning table inserted in the design. We propose an algorithm to minimize the number of inserted tunable buffers, as well as their tunable range (which directly relates to complexity). Results show that clock skew is kept within original bounds with worst-case power and area penalty of 3.5% and 5.5%, respectively.      

A falling edge-triggered single shot pulse generator with Josephson devices

The circuit is constructed with two cross-coupled DC flip-flops, resulting in a square wave output signal without any external special clock signal. The circuit configuration and operating principle are described. The circuit has been experimentally fabricated and its operating margin has been examined. The analysis successfully explains the experimental results.     

A Low-Power Delay Buffer Using Gated Driver Tree

This paper presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. A novel gated-clock-driver tree is then applied to further reduce the activity along the clock distribution network. Moreover, the gated-driver-tree idea is also employed in the input and output ports of the memory block to decrease their loading, thus saving even more power. Both simulation results and experimental results show great improvement in power consumption. A 256$,times,$8 delay buffer is fabricated and verified in 0.18 $mu {hbox {m}}$ CMOS technology and it dissipates only 2.56 mW when operating at 135 MHz from 1.8-V supply voltage.      

A high-frequency CMOS multi-modulus divider for PLL frequency synthesizers

A high-frequency divide-by-256–271 programmable divider is presented with the improved timing of the multi-modulus divider structure and the high-speed embedded flip-flops. The D flip-flop and logic flip-flop are proposed by using a fast pipeline technique, which contains single-phase, edge-triggered, ratioed, and high-speed technologies. The circuits achieve high-speed by reducing the capacitive load and sharing the delay between the combination logic blocks and the storage elements. By the way, it is suitable for realizing high-speed synchronous counters. The programmable divider using proposed flip-flops is measured in 0.25-μm CMOS technology with the operating clock frequency reaching as high as 4.7 GHz under the supply voltage of 3V.     

High-speed demonstration of single-flux-quantum cross-bar switch up to 50 GHz

We have been developing a single-flux-quantum (SFQ) cross-bar switch, which is a main component of a network packet switch. We think that a network switch is an application in which the high speed of SFQ technology would be advantageous. Anticipating general and large-scale SFQ logic circuit design, we used the cell-based design method and the CONNECT standard SFQ cell library. The two-input and two-output cross-bar switch, a core switch component, consists of 13 logic cells connected by Josephson-transmission-line (JTL) cells. Because of the large size of JTL cells and the large delay in them, timing adjustment becomes more difficult as the operating speed and circuit size increase. After using a commercially available automatic router to find appropriate routes efficiently, we used a static timing analyzer for fine timing adjustment. Timing violations were fixed by changing JTL path delays using the tools we developed. The target operating frequency of the switch was 40 GHz, which corresponds to a clock period of 25 ps. Careful timing adjustment was necessary to ensure correct operations at such a high speed. The test chip was fabricated by using an NEC standard Nb process. The circuit, including on-chip test circuitry, was composed of about 1500 Josephson junctions. We confirmed its correct operations up to 50 GHz with a bias margin of /spl plusmn/20%.     

A Fast-Lock Wide-Range Delay-Locked Loop Using Frequency-Range Selector for Multiphase Clock Generator

This brief describes a fast-lock mixed-mode delay-locked loop (DLL) for wide-range operation and multiphase outputs. The architecture of the proposed DLL uses the mixed-mode time-to-digital-converter scheme for a frequency-range selector and a coarse tune circuit to reduce the lock time. A multi-controlled delay cell for the voltage-controlled delay line is applied to provide the wide operating frequency range and low-jitter performance. The charge pump circuit is implemented using a digital control scheme to achieve adaptive bandwidth. The chip is fabricated in a 0.25-mum standard CMOS process with a 2.5-V power-supply voltage. The measurements show that this DLL can be operated correctly when the input clock frequency is changed from 32 to 320 MHz, and can generate ten-phase clocks within a single cycle without the false locking problem associated with conventional DLLs and wide-range operation. At 200 MHz, the measured rms random jitter and peak-to-peak deterministic jitter are 4.44 and 15 ps, respectively. Moreover, the lock time is less than 22 clock cycles. This DLL occupies less area (0.07 mm²) and dissipates less power (15 mW) than other wide-range DLLs.     

Comparative analysis of yield optimized pulsed flip-flops

In this paper, the influence of random process variations on pulsed flip-flops is analyzed. Monte Carlo simulation results demonstrate that using transistor reordering and dual threshold voltage transistors timing, energy and energy-delay-product yields of more than 1.98, 1.62 and 1.99 times higher are obtained, without requiring architectural modifications and without increasing silicon area requirement. Several flip-flops optimized as described here are compared taking into account the effects due to random process variations and to environmental variations (caused by power supply voltage and temperature fluctuations). Obtained results show that among the compared circuits the Conditional Precharge Flip-Flop achieves the highest delay, energy and energy-delay-product yields.     

An IDDQ sensor for concurrent timing error detection

Error control is a major concern in many computer systems, particularly those deployed in critical applications. Experience shows that most malfunctions during system operation are caused by transient faults, which often manifest themselves as abnormal signal delays that may result in violations of circuit element timing constraints. We present a novel complementary metal-oxide-semiconductor-based concurrent error-detection circuit that allows a flip-flop (or other timing-sensitive circuit element) to sense and signal when its data has been potentially corrupted by a setup or hold timing violation. Our circuit employs on-chip quiescent supply current evaluation to determine when the input changes in relation to a clock edge. Current through the detection circuit should be negligible while the input is stable. If the input changes too close to the clock time, the resulting switching transient current in the detection circuit exceeds a reference threshold at the time of the clock transition, and an error is flagged. We have designed, fabricated, and evaluated a test chip that shows that such an approach can be used to detect setup and hold time violations effectively in clocked circuit elements     

触发器的广义特性方程及其应用

本文建立了触发器的广义特性方程，并介绍了它在时序逻辑电路分析中的应用     

A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting

This paper describes an interconnect technique for subthreshold circuits to improve global wire delay and reduce the delay variation due to process-voltage-temperature (PVT) fluctuations. By internally boosting the gate voltage of the driver transistors, operating region is shifted from subthreshold region to super-threshold region enhancing performance and improving tolerance to PVT variations. Simulations of a clock distribution network using the proposed driver shows a 66%-76% reduction in 3sigma clock skew value and 84%-88% reduction in clock tree delay compared to using conventional drivers. A 0.4-V test chip has been fabricated in a 0.18-mum 6-metal CMOS process to demonstrate the effectiveness of the proposed scheme. Measurement results show 2.6times faster switching speed and 2.4times less delay sensitivity under temperature variations.     

SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus

In this paper, a variation-tolerant low-power source-synchronous multicycle bus (SSMCB) interconnect scheme is proposed. This scheme is scalable and suitable for transferring data across different clock domains such as those in “many-core” SoCs and in 3-D ICs. SSMCB replaces intermediate flip-flops by a source-synchronous synchronization scheme. Removing the intermediate flip-flops in the SSMCB scheme enables better averaging of delay variations across the whole interconnect, which reduces bit-rate degradation due to within-die process variations. Monte Carlo circuit simulations show that SSMCB eliminates 90% of the variation-induced performance degradation in a six-cycle 9-mm-long 16-bit conventional bus.      

面向电荷泵的占空比可调四相时钟发生电路北大核心

针对传统四相时钟发生电路产生的时钟波形信号易发生交叠、驱动电荷泵易发生漏电等问题，提出了一种占空比可调四相时钟发生电路。电路在每两相可能出现交叠的时钟信号之间都增加了延时单元模块，通过控制延时时间对输出时钟信号的占空比进行调节，避免了时钟相位的交叠。对延时单元进行了改进，在外接偏置电压条件下，实现了延时可控。基于55 nm CMOS工艺的仿真结果表明，在10～50 MHz时钟输入频率范围内，该四相时钟发生电路可以稳定输出四相不交叠时钟信号，并能在1.2 V电压下驱动十级电荷泵高效泵入11.2 V。流片测试结果表明，该四相时钟发生电路能够产生不相交叠的四相时钟波形，时钟输出相位满足电荷泵驱动需求。     

Post-fabrication clock-timing adjustment using genetic algorithms

To solve the problem of fluctuations in clock timing (also known as "clock skew" problems), we propose an approach for the implementation of post-fabrication clock-timing adjustment utilizing genetic algorithms (GAs). This approach is realized by the combination of dedicated adjustable circuitry and adjustment software, with the values for multiple programmable delay circuits inserted into the clock lines being determined by the adjustment software after fabrication. The proposed approach has three advantages: 1) enhancement in clock frequencies leading to improved operational yields; 2) lower power supply voltages, while maintaining operational yield; and 3) reductions in design times. Two different LSIs have been developed: the first is a programmable delay circuit, developed as an element of the clock-timing adjustment, while the second is a medium-scale circuit, developed to evaluate these advantages in a real chip. Experiments with these two LSIs, as well as a design experiment, have demonstrated these advantages with an enhancement in clock frequency of 25% (max), a reduction in the power-supply voltage of 33%, and a 21% shorter design time.     

Wide-range synchronous mirror delay with arbitrary input duty cycle

A wide-range synchronous mirror delay (SMD) with arbitrary input duty cycle is presented. The proposed SMD utilises the time-to- digital converter for a frequency-range selector and a multiband delay monitor circuit to achieve a wide range of operating frequencies. The simulation results show that the operating frequency is from 200 MHz to 1 GHz and the static phase error is 6.7 ps. The locking time is less than eight clock cycles: two cycles with coarse tune and six cycles with fine tune.     

A digital automatic tuning technique for high-order continuous-time filters

A digital automatic tuning technique for high-order continuous-time filters is proposed. Direct tuning of overall response is achieved without separating individual biquad sections, eliminating switches and their parasitics. Output phase of each biquad section is tuned to known references, which are generated by a frequency synthesizer. The core tuning circuit consists of D flip-flops (DFF) and simple logic gates. DFFs are utilized to perform binary phase detection. Frequency and quality factor tuning loops for each biquad are controlled digitally, providing more stable tuning by activating only one loop at a given time. The tuning system was verified by a prototype sixth-order bandpass filter which was fabricated in a conventional 0.5 /spl mu/m CMOS process with /spl plusmn/1.5 V power supply.