Performance characteristics of diazo-type photoresists under e-beam and optical exposure

The performance characteristics of three different diazotype positive photoresists such as Shipley AZ2400, Kodak 809, and Polychrome PC129, are compared after optical exposure and electron-beam exposure. The development rates for both e-beam and optically exposed resists are measured by an in-situ automated technique using the IBM Film Thickness Analyzer. The optical exposure parameters are obtained at three wavelengths (4358, 4047, and 3650) by computer-controlled transmission measurements. The optical exposure and development parameters permit direct quantitative comparisons for these photoresists. The development rates of e-beam and optically exposed resists are compared. Also a comparison of e-beam sensitivity between the three resist systems is made by studying the resist profile shape after development in the scanning-electron microscope (SEM).     

High-resolution fused silica mold fabrication for UV-nanoimprint

This paper describes the fabrication steps developed to pattern nano scale features on thin silica wafers. The optimization of e-beam exposure dose is presented. The use of a chrome layer on top of the silica wafer implies higher doses to crosslink the negative NEB22 resist, but the results show a very large window process. Specific etching processes have been developed. It is demonstrated how the micro-trenching and CD bias are reduced. Thanks to the optimization of both the exposure dose during e-beam lithography and the plasma dry etch steps, features with a resolution as low as 30 nm have been achieved.     

掩模制作中的邻近效应

计算模拟了激光束和电子束直写加工的掩模畸变,并分别用理想掩模和有畸变的掩模进行投影光学光刻过程的模拟和比较,讨论了光学邻近效应校正掩模在加工过程中所产生的畸变对传递到最终基片上的图形的影响。模拟分析指出,掩模加工中的邻近畸变应在设计光学邻近校正掩模时予以注意,即在掩模设计时,应把掩模加工中的邻近效应和光刻图形传递过程的邻近效应进行总体考虑,以便设计出最优化的掩模,获得最好的邻近效应校正效果。     

Fabrication of large scale arrays of metallic nanodots by means of high resolution e-beam lithography

We present the fabrication of large nanodot arrays with very small single dot sizes made of different metals and on different substrates using e-beam lithography and lift-off techniques. Nanodot arrays have a high potential for bioanalytical applications aiming towards single molecule detection. In addition, they can be used as well defined models of heterogeneous catalysts. For this purpose an independent control of the dot size and the distance between the dots is necessary. This is a limitation for many fabrication techniques, which can be overcome by e-beam lithography. However, aiming for the dot size of few tens of nanometers, we observed a strong influence of the beam focusing and astigmatism on the quality of the fabricated nanodot arrays. A significant improvement, i.e. reduction of defect density as well as better control of the dot size, was achieved by modification of the fine focus and stigmation system of the used e-beam writer. Using lift-off technique, we successfully fabricated platinum dot arrays on glassy carbon with target dot diameter ranging from 25 to 35 nm. By applying additional annealing step, we could fabricate nanodot arrays made of gold on SiO₂ with very small dot sizes down to 6 nm and pitch of 100 nm. Furthermore, the generation of large area arrays of nanosized pillars was demonstrated using the same exposure strategy in a negative tone HSQ resist.     

Nanostructure patterning

Research at the US Naval Research Laboratory (NRL) in the lithography, patterning, and fabrication of structures of nanometer scale dimensions is reviewed. Electron-beam (e-beam) lithography at high (50 keV) and low (5 eV) energies on resist systems developed at NRL is described. The low energy lithography takes advantage of the spatially confined e-beam available in a scanning tunneling microscope type probe. This instrument allows an in situ exposure and characterization of an e-beam sensitive material. A novel approach for implementing dose correction for proximity effects in e-beam lithography is presented using an error measure based on the physical realities of lithography. The compositional disordering of GaAs-Ga_xAl_1-xAs heterostructures as a technique for pattern replication is described. Introducing silicon into the heterostructure (by implantation or diffusion) enhances the aluminum and gallium interdiffusion which can be used for patterning. A complete bibliography of recently published results is included     

Comparison of quartz and silicon as a master mold substrate for patterned media UV-NIL replica process

Nanoimprint lithography (NIL) is a promising candidate technology to fabricate patterned media for the next generation hard disk drives (HDD). The requirement of pattern pitch for the HDD or discrete-track recording (DTR) media will be as small as from 40 to 50 nm by 2011 or 2012. However not only to create such fine pitch but also long e-beam writing time such as 1 week with conventional high resolution resist ZEP520A are critical. This paper addresses the fabrication processes to combine silicon substrate and a new chemically amplified resist (CAR) for the master molds of this NIL. The e-beam writing speed with this new CAR was achieved over 3-times faster while 50 nm fine DTR patterns were demonstrated with rotary stage e-beam writer. Furthermore, the replication with J-FIL from the master mold into quartz working mold was also demonstrated.     

High resolution techniques for the fabrication of small area Josephson tunnel junctions

Superconducting tunnel junction devices as small as 10^-10cm²have been made using novel self-aligning techniques in conjunction with optical or e-beam lithography. This process has been used to fabricate complete circuits and multijunction arrays under well controlled conditions, using a single resist patterning step.     

Fabrication of nanometer metal structures by a combination of techniques of metal evaporation and E-beam nanolithography

A simple but effective technique is described in which a multiple strand filament source for thermal evaporation of metals is used in conjunction with e-beam nanolithography. It is capable of fabricating nanometer metal structures with dimensions smaller than the resist opening by e-beam nanolithography. Preliminary results presented in this paper illustrate that this technique can be extended to dimensions which are beyond the present resolution limit (∼ 15-20nm), achievable with e-beam lithography and positive polymer resist. The pattern generation capability of e-beam nanolithography is extended to the fabrication of complex and high-density nanometer structures with dimensions ∼ 10 nm or less.     

E-beam direct wafer writing process using a water-solubleconductive layer

The water-soluble conductive layer(WSCL) is ammonium poly (p-styrene sulfonate) having ionic conductivity and water solubility. The process consists of applying thin WSCL to the e-beam resist surface prior to the conventional exposure step. WSCL is subsequently removed and the e-beam resist developed in the ordinary way. The process has general utility for various resists, eliminating charging effects caused by -beam exposure     

Deep-submicrometer MOS device fabrication using aphotoresist-ashing technique

A photoresist-ashing process has been developed which, when used in conjunction with conventional g-line optical lithography, permits the controlled definition of deep-submicrometer features. The ultrafine lines were obtained by calibrated ashing of the lithographically defined features in oxygen plasma. The technique has been successfully used to fabricate MOSFETs with effective channel length as small as 0.15 μm that show excellent characteristics. An NMOS ring oscillator with 0.2-μm devices has been fabricated with a room-temperature propagation delay of 22 ps/stage. Studies indicate that the thinning is both reproducible and uniform so that it should be usable in circuit as well as device fabrication. Since most polymer-based resist materials are etchable with an oxygen plasma, the basic technique could be extended to supplement other lithographic processes, including e-beam and X-ray processes, for fabricating both silicon and nonsilicon devices and circuits     

Metallic nanogaps with access windows for liquid based systems

A new method has been established for the reproducible fabrication of high quality, metallic nanogaps on silicon chips suitable for liquid based nanometer scale devices. Realization of μm structures connected to nanogaps with gap sizes down to 30 nm has been achieved by a combination of an optical and an electron-beam (e-beam) lithography step using an optimised adhesion layer/metallic layer combination (Ti/Pt/Au—three layer combination) and an adopted two layer e-beam resist. The quality of the interconnects between optically and e-beam lithographically defined structures and the surface roughness of the gold nanogaps have been improved by a controlled temperature treatment. With this method the production of a variety of different gap shapes could be demonstrated. Specifically the lithographic structures have been successfully covered by a protection layer, except of a 200 nm×400 nm size access window located on top of the nanogaps, making it suitable for applications in liquid environment such as molecular and/or electrochemical metal deposition.     

An inorganic resist technology and its applications to LSI fabrication processes

An Ag/Se-Ge inorganic resist technology is applied to photolithographic processes in LSI fabrication. This paper describes exposure latitude, RIE characteristics, resist fabrication and exposure throughputs, pattern alignment, defocus tolerances and fabrication yields of Al interconnection.Lateral Ag diffusion does not effectively improve the exposure tolerance. The technology exhibits good compatibility with other equipment and technologies, offering satisfactory throughput. Excellent accuracy in pattern alignment is obtained owing to dry-deposition fabrication and the suitable optical properties of the Se-Ge inorganic film, which result in regulated and distinct alignment signals. Defocus tolerance in the resist is larger than that of polymer resist by 2 ∽ 3 μm in the submicron pattern. Al interconnections using this resist demonstrate a short-circuit failure rate of less than 1% and small variation in linewidth having a standard deviation of σ_w = 0.08 μm.In practical processes, the significant advantages of this resist are its bilayer resist structure (doped Ag-Se-Ge and underlying Se-Ge) and its dry deposition, very thin, favorable optical characteristics.     

Quantitative evaluation of shape of image on photoresist of squareapertures

Simulation of images of two-dimensional structures in optical lithography is considered to have become quite important with the patterning of near-micrometer geometries in complex structures encountered in VLSI. Here, the results are presented of theoretical computations performed to calculate the aerial image of square apertures in a projection system using a partially coherent light source. The resist has been modeled by its sensitivity curve in order to compute the image profile on the resist after development. A figure of merit (FOM) has been proposed that quantifies the shape of the aerial as well as the resist image. Such an FOM has been proposed that can be used very effectively to optimize a lithographic process     

Developer selection for T-shaped gate FET's usingPMMA/P[MMA-co-MAA]/PMMA

A T-shaped gate fabrication process has been developed based on a triple-layer resist system with gate cross section control by resist developer formulation. The new procedure allows a conventional e-beam exposure and single develop step to accomplish what requires position dependent e-beam doses or multiple exposures and multiple develop steps in other processes. General considerations in developer selection are discussed. For the process conditions used in this study, gate lengths from 80 to 280 nm were obtained from doses from 250 to 350 μC/cm² with 20-keV electrons. Initial results on RF performance for a 1.2-mm periphery power FET are given     

Exposure latitude and CD control study for additively patterned X-ray mask with GBit DRAM complexity

40 kV electron beam lithography has been used to pattern gold plated x-ray masks containing GBit DRAM complexity layouts. The two commercial e-beam resists used, namely PMMA and SAL 601, both showed 0.12 μm resolution capability in dense and large layouts patterning and also, under optimised exposure and development conditions, exhibited good exposure latitudes which were also evaluated for two different beam spot sizes. Futhermore, a study of development technique and effect of e-beam spot size indicated a marked dependence of ultimate resolution and exposure latitude on such parameters. A statistical analysis of 0.12 μm resolution SAL patterning on large chip dies (30 × 30 mm²) resulted in a dimensional control of 10 nm (3σ value).     

A high resolution negative electron resist by image reversal

The use of AZ 1350 family photoresists as negative electron resists is described. Conventional photolithographic technology is used to coat and process the resist, with the exception of an e-beam exposure for patterning. A flood UV exposure is used for image reversal. Using 1.5 µm initial thickness, the exposure threshold for 6 s development in 1 : 1 AZ : H2O developer is 7 µC/cm². The resist contrast under these conditions is 1.3; and the sensitivity is about 25 µC/cm²(70% thickness remaining). Useful resolution on SiO2/Si and Al/SiO2/Si substrates is demonstrated to be at least 0.5 µm, and the resist is shown to mask the plasma etching of Al.     

电子束曝光中的邻近效应修正技术

邻近效应是指电子在抗蚀剂和基片中的散射引起图形的改变，它严重地影响了图形的分辨率。有多种方法对邻近效应进行修正和剂量调整、图形调整等。我们以ＪＢＸ－５０００ＬＳ为手段，用三种方法：１．图形尺寸修正，１２大小图分类和剂量分配，３图形分层和大小电流混合曝光，对邻近效应进行了修正，均取得较好效果。     

Resolution and linewidth tolerances in electron beam and optical projection lithography

In order to understand the practical limits of electron beam direct-write and optical projection lithography techniques in device fabrication with micrometer and submicrometer geometries, we have exercised two computer simulation programs to estimate resolution limits and linewidth control. Latent image contrast and developed resist thickness contrast were calculated as a function of line-array spatial frequency. The linewidth tolerances were calculated by varying exposure, development time, focusing, line/space Pattern, resist thickness, etc. These simulation results indicate that the lithographic performance of the two techniques using state-of-the-art exposure tools are comparable at 1-µm dimensions. Some relevant experimental data also are presented.     

A model for the thermal degeneration of a positive opticalphotoresist

Positive optical photoresists have been used extensively in the semiconductor industry and in the manufacture of thin-film disk- and tape-drive heads. Mathematical models for the exposure and development phases of the lithography process have been well defined, but scant information on modeling of the pre-bake phase is available. A pre-bake model which describes the deterioration of the photoactive component in a positive optical resist is derived. A mass balance and the kinetics of the situation are used to describe the change in the Dill exposure model parameters. Experimental verification of the model is shown with three photoresists whose parameters are calculated for different wavelengths of light. The effect of the resist solvent on the exposure model parameters is discussed     

Fabrication of integrated circuits using the electron image projection system (ELIPS)

ELIPS is based on the use of an electron image tube principle to project large area (5-cm diameter) ultrahigh resolution (1 micron) electron images from a patterned photocathode onto an electron-sensitive resist layer, thereby replacing the conventional photoresist optical procedures in integrated circuit fabrication [1]. Integrated circuits of minimum linewidths of 0.5 mil have been fabricated to show the practicality of the technique through the full set of mask exposures necessary for a DZTL quad dual input NAND gate. The necessary alignments between successive masks were achieved by an optical dead reckoning technique which allowed the electron image to be adjusted in position and orientation from a known "zero" position to the separately determined location of the pre-existing pattern on the sample. Accuracy of such alignments was ± 2 micron. The much more desirable alignment technique, in which simple devices in the form of alignment marks on the target wafer detect separate electron beams emanating from the cathode, allows rapid alignment to submicron registration and the potential for the complete automation of alignment and exposure. The system provides for the rapid registration and exposure of wafers at high resolution over large areas with great depth of focus under vacuum clean, contactless conditions using an electroresist insensitive to ambient light. It makes practical the fabrication of very high-density planar devices allowing extremely complex large area circuits to be formed. Patterned photocathodes were fabricated by conventional photoresist techniques for the DZTL circuit discussed. For high-resolution (1 micron) patterns, cathodes can be defined in the electron micro-plotter (computer-controlled scanning electron microscope).