恶性斗殴为何屡禁不止？——运营商互殴：粗暴宣泄何以为“道”!

“我有一个梦想：某一天三大运营商员工不摆摊了,不打架了,员工年收入差距缩小了,前端营业员待遇提高了,后端装维与资源矛盾化解了,服务质量提高了,恶性竞争消除了,重复建设停止了,不再破坏对手广告了,不互挖墙角搞策反了,不再零元购机了,不打价格战了,都能活的有尊严了”.     

Wedding……

兄弟结婚了，朋友结婚了，朋友的朋友结婚了；男的结婚了，女的结婚了，不男不女的也结婚了；有感情的结婚了，没感情的结婚了，认识不认识的结婚已经无所谓了……     

对VoWLAN技术的MAC研究与改进

提出了一种适合VoWLAN技术DEDCA接入机制,引入了信道状态CS因子,提出了基于信道状态的动态的退避窗口机制和一种新的退避方式.确立了退避窗户最大值和最小值的与信道关系的公式,确立了退避方式阀值的公式,最后通过进行了仿真,DEDCA不但对视频和音频有QoS保证,整个信道的性能都提高了,验证了DEDCA的正确性和适合在VoWLAN技术中的应用.     

论装配式配电站的建设

装配式配电站的建设与发展,为电力行业的发展带来了全新的力量,极大地供应了整个社会的用电需求,提高了供电系统的运转水平,也为配电站建设节省了空间,削减了施工程序和周期,减少了环境污染,为整个社会创造了良好的经济效益和环境效益。本文分析了装配式配电站建设的方案、优势、技术以及效益。     

基于ZEMAX的红外光学系统设计与优化

阐述了该光学系统研究的意义,确定了基本设计原则。然后进行了平行光管和望远镜的高斯光学结构模型及设计,建立了具体的数学模型并进行求解。最后根据目标耦合光路结构,利用ZEMAX软件对该光学系统进行了优化设计,对优化结果进行了像质评价,得出了结论。该系统解决了红外光学精确制导系统动态跟踪特性的内场测试的一系列问题,促进了红外黑体跟踪目标地面等效测试的发展,对提升仿真试验技术能力提供了重要的硬件支撑。     

基于公平性的自相似业务接纳控制研究

文中研究了基于分形稳定运动有效带宽的计算方法,利用迭代过程推导出了聚合流有效带宽的计算公式,提出了一种基于有效带宽的公平性的自相似业务接纳控制算法,在接纳判断过程中引入了公平性机制,保证了业务接纳的公平性,通过MATLAB和OPNET相结合的仿真方法证明了该算法的有效性.结果证明了文中提出的算法保障了网络的服务质量,保证了各业务接纳的公平性,同时保持了网络高的利用率.     

基于XSLT和XML改进的Struts框架研究

介绍了Struts的框架模式以及流程,XML和XSLT的特点,分析了目前Struts的框架的优缺点,提出了新的改进方法,给出并分析了改进方法的流程图,还讲解了新方案的核心类的实现。重点讲解了如何用XSLT和XML改进Struts,最后阐述了改进后的优势。     

对我国车联网发展的思考

作为当今汽车工业和无线通信领域新宠,车联网引起了全球广泛关注。本文概述了车联网及其特征,介绍了美国、日本等一些国家车联网应用发展的情况,分析了车联网发展面临的问题,对我国车联网产业发展进行了探讨,并展望了未来车联网时代的生活。     

娱乐——未来企业营销大趋势

几周前,我去华尔街做了一次路演.在整个路演当中,盛大的股价提升了30%,从15块一股变成了20块.随后,一家国内著名媒体登出了这么一篇报道,题目是:"唐骏用45分钟忽悠了540万美金".虽然其中我确实花了45分钟时间说服投资者购买了30万股,但那个记者用了一个让我难以接受的方式--说我"忽悠"了540万美金."忽悠"这个词确实很不好听,所以我打电话对他说,你怎么可以这么写唐骏呢?     

恶性斗殴为何屡禁不止?

"我有一个梦想:某一天三大运营商员工不摆摊了,不打架了,员工年收入差距缩小了,前端营业员待遇提高了,后端装维与资源矛盾化解了,服务质量提高了,恶性竞争消除了,重复建设     

注钼纯铝的研究

利用从金属蒸汽真空弧离子源（简称ＭＢＶＶＡ源）引出的强束流钼离子对纯铝进行了不同束流密度的离子注入。加速电压为４８ｋＶ，剂量为３×１０￣（１７）ｃｍ￣（－２），束流密度为２５和４７μＡ·ｃｍ￣（－２），Ｘ衍射分析证明在注入层内可形成Ａｌ＿（１２）Ｍｏ晶体，背散射（ＲＢＳ）分析证明Ａｌ＿（１２）Ｍｏ的厚度可达６００至７００ｎｍ。     

高速高精度A/D转换器

本文介绍了用于观测太阳磁场的天文望远镜系统的高速高精度局部级联式多阈值A/D转换器。文章着重讨论了,为实现高速、高精度所采用的技术要点,并提出了研制高速高精度A/D转换器所必须考虑的有关问题。 我们所研制的A/D转换器,分辨率为1mV,相对误差0.025％,字长12位,前面接采样保持电路后,速度为10万次/秒。     

A charge-balancing monolithic A/D converter

The quest for a minimum-parts-count DPM led to the development of this monolithic, low power analog-to-digital converter. It incorporates the analog and digital functions historically implemented separately with specialized process technologies into a chip with full /spl plusmn/3 digit accuracy. The integration of resistors, compensation capacitors, and an oscillator reduces the external component complement to three capacitors and one adjustable reference. TTL compatible outputs include sign, overrange, and under range information in addition to the three digit strobes and the BCD data outputs. The logic operates between +5 V and ground, the linear section between +5 V and -5 V. The paper describes the conversion algorithm and its CMOS implementation, emphasizing the analog design of this innovative device.     

A Convenient Multivariate Gram-Charlier Type A Series

It is often necessary to approximate the probability density function of a random variable from given statistical moments. The Gram-Charlier Type A series is one well known method for such representations. In this note, the Gram-Charlier Type A series is generalized to the multidimensional case.     

一种识别说话者的新方法

在能够自动识别视频中的说话者的系统中,大部分采用的是声音和唇部运动相结合的方法。文中则采用了另一种方法有效地达到了目的,即通过检测人体头部和手部的运动来鉴别说话者。基于演讲者在说话时通常会伴有头部运动或是手部运动,该方法既能实现说话者的检测,又能避免由于观测点过远而导致无法判断人唇部运动的局限性。在系统的实施过程中,运用了多种图像处理方法,并且对三帧差运动法做出了改善,使其能更高效、更准确地检测到头部和手部的运动。经过多个不同的视频测试后,本系统的F1 score高达91．91％,从而验证了该系统的可行性。     

A Nyquist-rate delta-sigma A/D converter

This paper describes an analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time oversampling may be reduced or even eliminated. By doubling the number of Lth-order delta-sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta-sigma modulators in parallel with no oversampling is similar to operating the same modulator with an oversampling rate of M. A parallel delta-sigma A/D converter implementation composed of two, four, and eight second-order delta-sigma modulators is described that does not require oversampling. Using this prototype, the design issues of the parallel delta-sigma A/D converter are explored and the theoretical performance with no oversampling and with low oversampling is verified. This architecture shows promise for obtaining high speed and resolution conversion since it retains much of the insensitivity to nonideal circuit behavior characteristic of the individual delta-sigma modulators     

A charge-domain D/A conversion system

In this article, a new multiplication type D/A conversion system using CCD is proposed and the result of simulations for evaluating its performance is reported. The system consists of a recursive charge divider which divides input charge-packet Qin sequentially into output charge-packets Qin · 2^-i and two charge-packet accumulators which accumulates output charge-packets from the recursive divider selectively according to digital input signal bits starting from MSB. The system converts input digital signal bit by bit, fully in charge-domain, thus the power consumption for this system is supposed to be very low. Also in this article, an effective method to achieve higher accuracy for splitting a charge-packet into two equal-sized packets using very simple hard-ware structure is proposed. As the result of simulations, we have found that the upper limit of accuracy for the conversion is determined by transfer efficiency of CCD, and within this range a trade-off relationship exists among conversion-accuracy, circuit-size and conversion-rate. This unique relationship enables to reduce the circuit size of D/A converter significantly maintaining the accuracy of conversion by slowing down the conversion-rate. This D/A converter is appropriate especially for the system integration because of its simple structure, tolerance to the fabrication error and low power consumption inherrent in the nature of CCD. By using of this system, it is expected to be possible to realize a focal plane image processor performing parallel analog operations such as DCT conversion with CCD imager incorporated on the same Si chip by the same MOS process technology.     

A monolithic video A/D converter

The design and measured performance of a fully parallel monolithic 8-bit A/D converter is reported. The required comparators and combining logic were designed and fabricated with a standard high-performance triple-diffused technology. A bipolar comparator circuit giving good performance with high input impedance is described. Circuit operation is reported at sample rates up to 30 megasamples per second (MS/s), with analog input signal power at frequencies up to 6 MHz. Full 8-bit linearity was achieved. An SNR of 42-44 dB was observed at input signal frequencies up to 5.3 MHz.     

没有管理者的密钥共享方案

一般的密钥共享方案中都假设有一个管理者,管理者的作用是分发密钥,因此对管理者的可信要求很高,而现实生活中很难找到符合要求的管理者.文中利用单调存取结构上的张成方案构造了一个没有管理者的密钥共享方案,并证明其是一个可行的实用的密钥共享方案.基于这个的方案,构造了一个分布式密钥生成器.     

一种新的多值A/D转换器

通过对三值 A/ D转换数学表示的分析 ,设计了二种三值 A/ D转换器电路。该转换器电路具有结构简单、低功耗、小型化和高信息密度等优点 ,它可进一步完善多值数字系统的研究